ADF-2 Circuit Board Check-In -------------------------------- Original Rev. 3-MAY-2004 Most Recent Rev. 10-Jun-2005 This note describes the procedure for checking in and testing an ADF-2 circuit board. There are three basic underlying principles in the way that we go about doing this. They are: - Keep track of what is going on so that we do not waste time re-discovering the same problems and solutions. This is done by recording everything that is done to a card in the Trailer Sheets. see http://www.pa.msu.edu/hep/d0/ftp/run2b/l1cal/hardware/adf_2/cards_and_crates/ adf_2_trailer_sheets.txt - Discover a particular problem as early as you can in the process when there is a simple clean way to see that type of problem. Problems missed at this point when you are explicitly looking for them can sometimes exist for the life of the card un-discovered. - Modify the check-in testing process as we learn what kind of problems these cards will typically have. List of the basic steps: 1. Start the Trailer Sheet for this card. Fill in the Serial Number (S/N), the gain species, and the Final Assebly/Check-in date. see http://www.pa.msu.edu/hep/d0/ftp/run2b/l1cal/hardware/adf_2/cards_and_crates/ adf_2_trailer_sheets.txt 2. Mechanical Inspection: Look for the following on the card and note possible card rejection at this point. missing components backwards components tombstoned components damaged components: I1410 casing is damaged on some boards; The plastic inductor casing on the DC/DC convertors sometimes is loose and needs to be glued down. component to pads alignment problem solder problems: bridges, leads not soldered, excess solder (especially along the sides of 0603 capacitors) pcb problems: damaged corners, de-lamination, missing pads Solder on swipes on the bottom side of P1 and P2 Confirm that P3 was properly inserted: On some boards the center pins of the P3 connector were not inserted into the circuit board so that the board and the connector were flexed. Check for connector damage that causes holes to be closed on the face of P3. Cleaning problems: Flux, white residue 3. Final Assembly: Add MSU Serial Number lablel to the P0 connector. Place the label as far from the metal contacts on the connector as possible. Install the front panel and its mounting brackets using the proper screws and washers and torque. Check backplane connector screws and nuts to ensure that they are on tight. Add the MSU Serial Number and the gain species to the front panel with the label maker. Add the "Maestro" label to the front panel and install jumpers W1021 - W1027 if this card is a Maestro card. 4. Ohm Meter Tests: Check the resistance between the nets GROUND, VCC_LOGIC, VDD_ANALOG, VCC_ANALOG, VEE_ANALOG, VDD_LOGIC and VCCINT. This tests for shorts between the power nets and gross connections to the power planes. Access to these nets is provided in the table below. For the component locations see http://www.pa.msu.edu/hep/d0/ftp/run2b/l1cal/hardware/adf_2/manufacturing/ adf_2_inspect_top.ps. NET COMPONENT LOCATION ------------------------------------------- GROUND P3 Shielding on top of connector VCC_LOGIC F1302 A lead on the fuse VDD_ANALOG F1303 A lead on the fuse VCC_ANALOG F1301 A lead on the fuse VEE_ANALOG F1304 A lead on the fuse VDD_LOGIC C1333 The "+" terminal of the capacitor VCCINT C1323 The "+" terminal of the capacitor The acceptable values are listed in the table below. Place the COMMON probe at the net listed in the top row of the table and the "+" probe at the net listed in the left column of the table. All values are in Ohms. Sample Entry +--------+ | 3.3K | This entry means that values between 2.7K Ohms and 3.3K Ohms | - | are acceptable. The Ohm meter should be set at the 20K Ohm |c 2.7K | range. +--------+ a - 200 Ohm range b - 2K Ohm range c - 20K Ohm range d - 200K Ohm range e - M Ohm range "+" PROBE COMMON PROBE (BLACK) (RED) +------------+--------+-------+--------+--------+--------+-------+--------+ | | | VCC_ | VDD_ | VCC_ | VEE_ | VDD_ | | | | GROUND | LOGIC | ANALOG | ANALOG | ANALOG | LOGIC | VCCINT | +------------+--------+-------+--------+--------+--------+-------+--------+ | | 3.3K | | | | | | | | VCC_LOGIC | - |XXXXXXX|XXXXXXXX|XXXXXXXX|XXXXXXXX|XXXXXXX|XXXXXXXX| | |c 2.7K | | | | | | | +------------+--------+-------+--------+--------+--------+-------+--------+ | | 80 | 3.4K | | | | | | | VDD_ANALOG | - | - |XXXXXXXX|XXXXXXXX|XXXXXXXX|XXXXXXX|XXXXXXXX| | |c 60 |c 2.8K | | | | | | +------------+--------+-------+--------+--------+--------+-------+--------+ | | 1030 | 4.4K | 1060 | | | | | | VCC_ANALOG | - | - | - |XXXXXXXX|XXXXXXXX|XXXXXXX|XXXXXXXX| | |c 830 |c 3.6K |c 860 | | | | | +------------+--------+-------+--------+--------+--------+-------+--------+ | | 1030 | 4.4K | 1060 | 1.9K | | | | | VEE_ANALOG | - | - | - | - |XXXXXXXX|XXXXXXX|XXXXXXXX| | |c 830 |c 3.6K |c 860 |c 1.5K | | | | +------------+--------+-------+--------+--------+--------+-------+--------+ | | 2.5K | 5.7K | 2.4K | 3.5K | 3.3K | | | | VDD_LOGIC | - | - | - | - | - |XXXXXXX|XXXXXXXX| | |c 1.5K |c 4.7K |c 2.0K |c 2.5K |c 2.7K | | | +------------+--------+-------+--------+--------+--------+-------+--------+ | | 170 | 3.5K | 260 | 1.1K | 1.1K | 695 | | | VCCINT | - | - | - | - | - | - |XXXXXXXX| | |c 130 |c 2.9K |c 160 |c 0.9K |c 0.9K |b 655 | | +------------+--------+-------+--------+--------+--------+-------+--------+ 5. Initial Power Up: Turn off the crate power and insert the card under test in slot 10. Turn on the power to the crate. Record voltage and current values for the 4 crate power supplies. The nominal values are listed below for a crate with 3 cards inserted: a vertical interconnect slave, a maestro card with its PAL programmed and a non-maetsro card with its PAL not programmed. These values are typical values observed when testing cards and are not from calculations. Power 25 W U5 5.00 V 0.9 A +3v3 3.30 V 3 A U1 5.00 V 1.1 A +5v0 5.00 V 1 A Check (feel) for hot spots. The ADCs will feel hot because they are initially on because the PAL has not been programmed yet so it cannot disable them. Check the output from the on-board DC/DC Converters. This is to be done by experts only. Use a multimeter to test VCCINT at C1323 and VDD_LOGIC at C1333. Check both DC and AC while the probe is on the capacitor lead. The AC signal should be 0V otherwise the output is oscillating. The nominal values are listed below. VDD_LOGIC DC 3.30 V AC 0 V VCCINT DC 1.50 V AC 0 V 6. JTAG Configuration: Perform the JTAG configuration of the Board Control PAL. Instructions for doing this are at http://www.pa.msu.edu/hep/d0/ftp/run2b/l1cal/hardware/adf_2/general/ board_control_pal_configuration.txt Fill in the BC_PAL Firmware Version and program date in the Trailer Sheet. 7. Verify that the on-board clock generator is running and that it tracks the input clock. To do this, plug in the Monitor PLL cable into the top of the P4 connector so that the red cable is on the top. After the crate has been on for 5 minutes look at the reading on the multimeter. Acceptable values are 1.5V - 2.5V and not changing more than 2uV/s or 1mV/10min after the power has been on for 15 min. The PLL_Monitor signal will vary by as much as 30mV in the first 15 min. This is based on observation. Move to a computer controlled VME environment. The remaining steps assume the ADF-2 card under test is in slot 10. 8. Push the button "0) Basic IO" or run the command file "Step0_PalFpgaIo.cmd This tests VME Read/Write I/O to a set of registers in the Board Control PAL and each FPGA. It also tests the front panel LEDs controlled by the PAL and FPGAs. This command file writes all 0's and 1's to the Board Control Register 1, Board Control Register 2, and the Configuration Control Register in the PAL. A write operation also includes a read operation that reads back from the register written to in order to confirm the data was written. The command file then configures both FPGAs with firmware "dp_t2.exo". This confirms that configuration works prooperly and is an exercise of VME I/0 because there needs to be about 1M sucessfull VME I/O cycles for this to conclude successfully. Next all 1's and 0's are written to a register in each FPGA. This tests both writing and reading to the FPGA for same reason stated for the PAL above. The last thing that the command file does is to cycle the front panel LEDs controlled by the PAL and FPGA on and off 5 times. There should not be any red text in the remote console from this test. All of the red front panel LEDs should blink several times at the end of the test. 9. Press the button "1) Slots" or run the command file "Step1_AddressAllSlots.cmd" This tests if there are problems with the VME Geographic Address Lines. This scans the crate to see what slots are populated. The command file assumes only slots 10 and 20 are populated. It reports an error if it finds cards in slots (1-7,9-19,21) or does not find cards in slots 10 and 20. This test is performed by attempting to write to register 7. A window will pop up at the end of the test with a summary. Any errors will be reported in the summary. There should be no enrties in the summary with "Error!" at the end. 10. Press the button "2) RandomReg" or run the command file "Step2_RandomRegister.cmd" This exercises VME IO to the card and tests the address space on the ADF_2 card and inside the FPGAs. This loads the FPGAs in slots 10 and 20 with the firmware "dp_t7.exo". The command file then performs a 10M loop Random Resigster test on 144 registers in each FGPA on the card in slot 10 and 144 registers in each FGPA in slot 20. The registers are selected such that every address line is tested with the exception of A13. This is not tested because A13 corresponds to the energy lookup table and words in the table are 8-bits wide and the random register test only works with 16-bit words. The remote console will report back how many errors were found. 11. Press the button "3) DacToAdc" or run the command file "Step3_DacToAdcRatio.cmd" This tests that gain of the DAC to ADC is between 6.9 and 7.3. In doing so, the functionality of the DACs and ADCs and their connections to the PAL and the FPGAs are tested. The T7 firmware is loaded into the FPGAs and "Adf_InitCard.cmd" is run. The DACs are loaded with 50 and 3500 and the ADCs are read out. The value read out when the DACs were set to 50 is AdcValueDacLow and the value read out when the DACs were set to 3500 is AdcValueDacHigh. The ratio of AdcValueDacHigh / AdcValueDacLow is computed and reported. Values outside of 6.9-7.3 are reported as errors. A summary window with the DAC to ADC ratios will pop up after the test is finished. There should be no summary entries with "Error!" at the end. 12. Press the button "4) Find_DAC" or run the command file "Step4_FindDac.cmd" This tests the full scale of the DACs to ADCs output and determines the DAC value that corresponds to a value of 490 on the ADC for each channel. This also does a simple noise measurement on successive ADC reads. This loads firmware "dp_t7.exo" into the FPGAs in slot 10. During the test, the full DAC range is tested and it is confirmed that the lowest DAC output yields about half scale on the ADC and the highest DAC output yields zero on the ADC. The ratio of the DAC to ADC is computed from samples just below the highest and just above the lowest DAC ouput. The DAC value corresponding to and ADC output of 490 is interpolated and tested for. Each DAC value in the vicinity of the interpolated value is sampled many times and the standard deviation is computed. The DAC value that actually yields and ADC output closest to 490 is returned. A summary window will pop up showing the DAC values corresponding to an output of 490 and the standard deviation of many ADC reads at that DAC value. If a DAC value could not be found that yielded an ADC output of 490 then an error is reported. If the standard deviation is greater than 0.5 an error is reported. 13. Press "5) Frequency Response" or run the command file "Step5_FreqResp.cmd" This tests the frequency response of the ADF-2 card at three frequencies: 50KHz(below band), 1MHz(in band), 20MHz(above band). This loads each FPGA in slot 10 with the firmware "dp_t7.exo". This test samples each channel with sin wave inputs from Stefano's waveform generator at 50KHz (below band), 1MHz (inband), and 20MHz (above band) input into the channel being sampled. The channel number vs. magnitude is plotted for each frequency and displayed. The graphs should be flat. The 50KHz singal is know to have some structure and this is thought to be due to the test signal input circuit and not a property of the ADF-2 card. Acceptable values are: 120> @ 20MHz, 220> @ 50KHz, and 240< @ 1MHz. 14. Press "6) FFT Analysis" or run the command file "Step_6_FFT_Analysis.cmd" A 2MHz sin wave is input into each channel and read out through the ADCs. The sampled wave is analyzed with the program ffttool. Initially the "dp_t7.exo" firmware is loaded into the FPGAs. Then the command file "Adf_InitCard.cmd" is called to turn on the ADCs. 4096 samples are read from the channel and the average and standard deviation is computed for the sample. The data is passed to ffttool and is checked for DC value, frequency, harmonic distortion, bit patterns (eg. a bit always set low or two adjacent bits always the same value). This is repeated for all 32 channels on the ADF-2 card. A dialog box pops up after the test and indicates if there were errors. The file "C:/LICal_IIB/LogFiles/CommandFiles/FFT_Analysis/[SN#]/errors.log/ [SN]_[DATE]_[Trial]/errors.log gives details on the errors found. 15. Plug in the appropriate Channel Link cable into "Big Brother" and Press "7) Channel Link" or run the command file "Step7_ChannelLink.cmd" This command file performs much of the test described below. It loads the FPGAs on the ADF-2 card in slot 10 with the firmware "dp_t7.exo". The channel link is synced up by running "Adf_InitCard.cmd". The PRN seeds are loaded into the DP_FPGAs on the ADF-2 card and the sequence is started. Next "Big Brother" is set up to listen for the pattern. The GUI console will provide feedback if the pattern is found by "Big Brother". If the pattern is not found an error dialog box will pop up. If this happens rerun the script. 99% of the time is works the second time the script is run. After 10 minutes of running without errors a dialog box will pop up saying the test is complete and successfull. The test will continue to run until the power is turned off or the FPGAs are reconfigured. Press "7) Check Again" or run "Step7_ChannelLink_CheckAgain.cmd" to check the link again. The result with be displayed in the GUI console. This test needs to be performed on all 3 chanel link output channels on the ADF-2 card. After one chanels test is complete, unplug the chanel link cable from "Big Brother" and plug in the cable for the next chanel to be tested. Once the cable is plugged in press "7) Channel Link" or rerun "Step7_ChannelLink.cmd". This will "wack" the ADF-2 FPGA and "Big Brothers" FPGA and prepare them for a new test. -------------------------------------------------------------------------------------- Channel Link Output Test of the ADF-2 Cards --------------------------------------------- Original Version: 15-MAR-2005 Latest Version: 16-MAR-2005 The intent of the ADF-2 Channel Link Test is to verify that the all 3 Channel Link outputs on the ADF-2 card are functioning properly. This test uses the ADF-2 DP_T6 firmware to generate the test data on the ADF-2 card and it uses the Denis Calvet's Channel Link Test Receiver to receive this test data and verify its format and content. Details about Denis' Channel Link Test Receiver are covered in: www.pa.msu.edu/hep/d0/ftp/run2b/l1cal/hardware/channel_link_tester/ channel_link_tester.txt Section 14 of this document contains many of the details which describe how it is being used in ADF-2 production testing. Basic Description of the Steps in ADF-2 Channel Link Testing 1. Plug the cable from the ADF-2 Channel Link output that is going to be tested into the Channel Link Test Receiver. 2. Start the ADF-2 card sending out the Channel Link test data. 3. Start the Channel Link Test Receiver checking the data that its receiving from the ADF-2 card that is under test. 4. Look at the Channel Link Test Receiver Error Counters to see if there are any errors. 5. Let the system run for 10 minutes and check the Error Counters again to see if there are any errors. 6. Repeat this proceadure for all 3 Channel Link outputs from the ADF-2 card that is under test. Detailed Description of the Steps in the ADF-2 Channel Link Test 1. The ADF-2 card that is going to have its Channel Link outputs tested must be in slot #10 of the test crate. This ADF-2 card must have already had its BC PAL programmed and have passed the basic tests for VME I/O and for Configuring its Data Path FPGAs. 2. Plug the cable from the ADF-2 Channel Link output that is going to be tested into the Channel Link Test Receiver. You do not need to turn off the crate power or the Channel Link Test Receiver power while doing this. - There must be one row of Channel Link Test Receiver pins over the top of the cable connector. - The cable connector is oriented so that either the gold metal piece is at the top or else the white plastic piece is on the right hand side. 3. Start the ADF-2 card sending the test data by executing the command file named: Step 7 Stop Load Start PRN T6 Channel Link Test This command file does all the steps that are necessary to start the ADF-2 cards sending Channel Link test data. This includes Configuring the ADF-2 Data Path FPGAs. 4. Initialize the Channel Link Test Receiver and start it checking the data that its receiving from the ADF-2 card that is under test. - You work with the Channel Link Test Receiver from its own control program which is running in a separate window from the TRICS L1 Cal Trig control programs. - There are a number of steps that are required to initialize the Channel Link Test Receiver and instruct it to begin testing its input data. You do not need to re-type the command lines for these steps. The Channel Link Test Receiver control program retains previous commands in a buffer and you may access these via up-arrow and down-arrow. - The commands that are needed to initialize the Channel Link Test Receiver are the following: mode 1 trig_pattern 0x 4 AAA8 0000 trig_mask 0x 1B 0000 0000 lfsr 0x0000 0xFFFE 0x012E 0x0C26 0xA128 ... 0x0031 After executing these commands the "flashing LED" at the top of the Channel Link Test Receiver should still be OFF. - The command that is needed to start the Channel Link Test Receiver checking its input data is the following: arm_trigger After executing this command the "flashing LED" at the top of the Channel Link Test Receiver should start FLASHING at a rate of about 2 Hz. If it is flashing very slowly (sub Hz) or if it is off, get help. 5. After the test has run for 5 or 10 seconds check the results by typing the command "errors" to the Channel Link Test Receiver. This will cause it to print a list of 36 error counters in the Channel Link Tester control program window. These counters should all be Zero. 6. After about 10 minutes of running this test, check the error counters again. They should still all be Zero. 7. When you are finished testing this ADF-2 card Channel Link output type "reset" in the Channel Link Tester command window. It is then OK to move to the next Channel Link output or to switch ADF-2 cards. For switching ADF-2 cards you must turn off the ADF Crate power but the Channel Link Test Receiver may remain powered up for this change. -------------------------------------------------------------------------------------- System Level Tests ------------------ The remaining tests are performed on a crate full of cards. The crate address is set at the top of the command files with the variables "SlaveNum" and "MasterNum". "MasterNum" should always be 0 and "SlaveNum" should be 0 for the production test crate and 1 for the system test crate. The top of the file also defines an array of slots to test. If the crate is not fully populated comment out the beginning of a unpopulated slot lines with a "#" at the begining of a line. 16. Run "Crate_Test_Pal_Registers_Startup_Values.cmd" This is intended to be performed after the crate has been turned on. This test reads the three read/write registers in the PAL and checks that the values match the expected power up values. If the values in the registers do not match the correct value is written. A summary window pops up after the test. Errors will be indicated with lines ending in "ERROR!!!!". 17. Run "Crate_Test_Crate_Status_Lines.cmd" This tests that all ADF-2 cards in the test crate can drive and read the Crate_Status bus. A single card writes a value to the Crate_Status bus and all 20 cards test to see if they read back the same value on the bus. All 16 possilbe values for the 4-signal bus are tested for each card. After all values have been tested for a card, the card writes all zeros to the bus so that other cards can drive the bus. This is done because the bus is open collector. After the test is done a summary window pops up. The summary is organized by what card was writing to the bus. The errors will be reported as what card wrote the word and what card read what incorrect value. 18. Run "Crate_Random_Register_Test.cmd" This programs all the DP_FPGAs in the test crate with the firmware "dp_t2.exo". 8 registers at address 512 are added to the Random Register Test Range for each FPGA. A 12 billion loop Random Register Test is performed (4 successive 3 billion loop random register tests). The remote console will return how many errors were found during the test. 19. Run "Crate_Test_Pal_Registers_Startup_Values.cmd" This is the same test that was run in step 16. This checks if the PAL registers survived the I/O performed during the Random Register Test. ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ DC Connectivity Test: FPGA to PAL ADF-2 to SCLD (does it matter except for a couple of Maestro ADF-2's ?) ADF-2 to/from Backplane ? Tests with SCLD and Maestro ADF-2 Crate Control: Verify that the control signals are correctly passed from SCLD to the normal ADF-2 cards in the crate. Verify that a fully populated crate operates correctly. Are there any grounding or noise problems ? e.g. with the Channel Link output data. Multi-Crate Tests: Verify that 2 or more fully populated crate operate correctly. Are there any grounding or noise problems ? e.g. with the Channel Link output data.