ADF-2 Inventory Notes -------------------------- Original Rev. 19-JAN-2005 Most Recent Rev. 10-Aug-2005 The purpose of this file is to record for now various pieces of information that we will eventually need to put into the formal inventory system and trailer sheets for the ADF-2 cards. This informal file will be used for now while we are working with the initial 10 ADF-2 cards. We will need to have the formal inventory system setup for these cards by the time that we begin testing the series production of 90 cards. Date: 4-JAN-2005 Drive to ADCO and pickup the first 10 cards. Start the initial visual and Ohm meter inspection. Note that C905, C906, C907 appear to be missing from all cards. Date: 5:6-JAN-2005 Start testing on ADF-2 SN #1. SN #1 has a temporary front panel and temporary LED's. For now it also has a temporary 20 MHz rock. During this work flag wires were added for: Received_DS1, VME_Latch_Clk, Data_Buf_Enb, Data_Buf_Direction, DRV_DTACK, CCLK, RDWR_B, PROG_B_0, CS_B_0, INIT_B_0, Done_0, Busy_0. Date: 12-JAN-2005 Start work on ADF-2 SN #2. SN #2 has a final design front panel (for use with the substitute LED's) except that the panel has not been painted. SN #2 has the VCXO installed. Thus SN #2 is 100% final electrical design. Configure its BC_PAL. It appears to work OK. Date: 13-JAN-2005 Using SN #1 and the DP_T4 software deliver the first files with 4096 consecutive samples. One file with no input and one file with 80% full scale sin wave input. Date: 14-JAN-2005 Find that R129 is missing on both SN #1 and SN #2 (and we assume on the other 8 cards). First official photo of SN #2. Date: 18-JAN-2005 Working with SN #2 notice in the Ped_DAC "gain" test that Ch 15 HD looks wrong (Ped_DAC gain is about 9 instead of about 7.2). The problem is that the bit of value 128 is stuck High from this ADC. That is caused by an open solder connection on N723 pin 3. Re-solder that pin and now SN #2 looks OK (except for the known missing R129 problem). Made a gain scan of SN #2 Ch 0 EM. This is at 2 MHz. Stefano HP Generator TRICS TRICS Output Dev Average ---------- ------- --------- 2000 mV 273.49 507.48 1500 mV 205.03 507.49 1000 mV 136.67 507.49 1000 mV 136.64 507.51 1000 mV 136.65 507.43 500 mV 68.44 507.48 0 mV 0.5 507.53 Note that based on the "Average Value" the Ped_DAC must have been set right between 2 codes. Using the D.P T5 firmware and Denis Channel Link test receiver mezzanine card verify that all 35 data bits from all 3 Channel Link outputs on card SN #2 look OK. This data looks fine. This is running in DC_Balanced mode and each time after moving the cable I did a De-Skew operation. That is now part of the wakeup command file. Date: 19-JAN-2005 Working with SN #2 make a gain scan over frequency. Before starting this scan, move the Ped_DAC around to get things centered on one ADC output code. This work was done with card SN #2 Channel 0 EM. Its Ped_DAC was set to the value 22 decimal. The generator was set for 1800 mV. Stefano HP Generator TRICS TRICS Output Dev Average ADC Values in this Histogram ---------- ------- --------- ----------------------------- no output 0.05 506. 8@505 4086@506 2@507 2.00 Mhz 246.00 505.94 157 lowest 2.00 Mhz 246.00 506.03 158 lowest 1.00 Mhz 249.34 505.94 153 lowest 1.00 Mhz 249.32 505.91 153 lowest 0.50 Mhz 247.17 504.33 156 lowest 0.50 Mhz 247.17 504.40 156 lowest 0.25 Mhz 244.28 505.36 161 lowest 0.25 Mhz 243.71 504.27 161 lowest 0.10 Mhz 229.05 498.50 182 lowest 0.10 Mhz 229.16 502.61 182 lowest 4.00 Mhz 237.30 505.96 170 lowest 4.00 Mhz 237.28 506.00 170 lowest 2.00 Mhz 245.69 505.99 158 lowest 8.00 Mhz 207.23 506.02 212 lowest 8.00 Mhz 207.26 506.00 212 lowest 16.00 Mhz 134.18 505.92 316 lowest 16.00 Mhz 134.29 506.01 316 lowest 20.00 Mhz 105.60 505.93 356 lowest 20.00 Mhz 105.61 505.94 356 lowest 25.00 Mhz 80.75 506.02 391 lowest 25.00 Mhz 80.73 505.93 391 lowest 3.00 Mhz 242.05 506.00 163 lowest 3.00 Mhz 242.05 505.92 163 lowest 5.00 Mhz 231.43 506.01 178 lowest 5.00 Mhz 231.42 505.99 178 lowest 12.00 Mhz 169.86 505.92 265 lowest 12.00 Mhz 169.87 505.99 265 lowest 2.00 Mhz 245.73 505.93 158 lowest 2.00 Mhz 245.72 505.91 158 lowest no output 0.05 506.00 5@505 4084@506 7@507 0.05 Mhz 197.56 496.72 222 lowest 0.05 Mhz 199.44 512.97 222 lowest Date: 21-JAN-2005 Work on SN #3. Install a painted front panel on SN #3 with the standard type of substitute LED's. Install the VCXO. The BC PAL programs OK (with the card drawing its "normal" 3 Amps of 3.3 Volts until the BC PAL is programmed). Run the Ped DAC Gain test and notice that Ch 11 EM is funny. It showed a gain ration of 3.47 It became clear that a couple of Ch 11 EM ADC data lines are tied together (512 & 256). This was an easy to remove solder bridge between pins 7,8 of N553. After that fix it ran OK for the Ped DAC Gain test. Put a data file of 4096 raw ADC samples from Ch 11 EM, taken when the solder bridge was still on the card, on the web for Jorge to practice on with his "funny data tool". Finally receive the replacement parts for the missing: C905, C906, C907 (0.47 uFd 0805) and R129 (150 Ohm 0603). Install these on SN #2 and SN #3. These two cards are now 100% complete for what the first 10 cards will be. Hold off on adding these parts to SN #1 because I want to keep on the flag wires on it for now and it is hard to work on with flag wires. Run automatic gain scans across all 32 channels at 3 frequencies (50 kHz, 1 MHz and 20 MHz). Do this on SN #2 and SN #3. Date: 22-JAN-2005 Work on SN #4. Install a painted front panel on SN #4 with the standard type of substitute LED's. Install the VCXO. Install the 3 missing capacitors C905:C907 and the 1 missing resistor R129. The BC PAL programs OK (with the card drawing its "normal" 3 Amps of 3.3 Volts until the BC PAL is programmed). ADF-2 SN #4 looks OK on the PED_DAC_Gain test. On SN #3 find a remove a solder bridge on U353 between pins 16 and 17. This is what made SN #3 1,3 HD look funny in the gain scan yesterday. This bridge clamped the Ch 7 HD MSBit to Gnd. Date: 28-JAN-2005 ADF-2 SN #4 shipped to Paul for the review meeting at the end of next week. Date: 29-JAN-2005 Philippe collects the 1024 files from SN #3 for Jorge's cross talk study. Denis' Channel Link Tester running on SN #3 Chan Lnk Output #0 The parity is correct with the total number of 1's set even. Standard setup for BERT: mode 1 trig_pattern $ 4 AAA8 0000 trig_mask $ 1B 0000 0000 lfsr lanes 0:17 Denis standard seeds lanes 18:31 $0018, $0019, $0020, ... $0030, $0031 Date: 30-JAN-2005 Finish 26 hours of standard setup BERT on SN #3 Output #0 with zero errors. Move BERT to SN #3 Output #2. Date: 31-JAN-2005 Finish 19 hours of standard setup BERT on SN #3 Output #2 with zero errors. Move the overall setup to using timing and control that comes through the SCLD and a Maestro ADF-2. Now more standard setup BERT to SN #3 Output #2. Date: 1-FEB-2005 Finish 15 hours of standard setup BERT on SN #3 Output #2 with zero errors. This is with timing and control coming from SCLD. Do the Final Assembly steps on SN #5 and SN #6. Date: 4-FEB-2005 Initial tests on SN #5 and SN #6. Philippe runs the full suite of analog tests on SN #2 #3 #5 #6. Want to have a standard set of data for Jorge to work with and want to check the response as a function of channel number to verify roll-off cap placement. This also now includes tuning the zero energy response ("Zeresp") to a fixed value that minimizes the observed noise RMS. The ADC Zeresp chosen is 490 ADC counts (as 500 was not in the linear range of the DAC->ADC relationship for some channels). The crosstalk runs of these 4-Feb tests were not fully successful as buffered disk activity on the PC while writing the 2048 files caused occasional timeouts waiting for the reply from the C++ engine and prevented a correct capture of all results in the command logfile. There were also an operator procedural error which lost the tuned Find_DAC settings at Zeresp=490, as the Frequency Response command file was still overwriting the DACs with zeros. BC PAL firmware is from 31-JAN-05 with phase comp working. Date: 8-FEB-2005 Run the full suite of analog tests on SN #2 #3 #5 #6 (again). A copy of the test results is in c:\users\python\py_vme\ComFiles\TestResults\... including excel plots. Date: 10-15-FEB-2005 Channel Link Test on SN#2 in slot #8 with SN#? in slot #7 and SN#3 in slot #9, with the crate BX clock running off of SCLD with SN#1 Maestro in slot #20. All 4 cards are loaded with T6 and cycling through the pseudo random test pattern, while Denis' tester is watching the center output of slot #8. No error in 24 hours ~1pm 10-Feb to ~1pm 11-Feb (stopped for show&tell PRR) No error in 4 days ~1pm 11-Feb to ~1pm 15-Feb (stopped for BC PAL wake up LED test) The tester software claims it checked 21.09 E12 cycles which is close to 60.7 E6 * 3600 sec * 24 hours * 4 days With 36 bits transfered and checked, 5 days of testing corresponds to 9.4 E14 bits We can also compare this test to the 240 ADF-TAB links of the full system, which corresponds to 5 days * 24 hours / 240 = 30 minutes of beam time with no error. Date: 16-FEB-2005 Continued test for >20 hours from ~1pm 15-Feb to ~10am 16-Feb This is now > 1E15 bits transferred in this test configuration Date: 17-FEB-2005 Add C905, C906, C907, R129 and VCXO to SN #7, #8, #9 and #10. Date: 18-FEB-2005 Assemble front panels on SN #7, #8, #9, and #10. This includes soldering the LEDs to the circuit boards. Date: 18-FEB-2005 ADF-2 SN 2 was not tracking the SCLD BX Clock. It was found that on ADF-2 SN 2 the control input pin to it VCXO had never been soldered correctly. Solder this pin and now it runs just fine tracking the SCLD clock. Date: 21-FEB-2005 ADF-2 SN 2 ran the standard Channel Link Test setup for 24 hours with zero errors using the DP_T6_16ma_Fast firmware. It then ran for 17 hours with zero errors using the DP_T6_8ma_Fast firmware. This was using the center Channel Link output to feed data to Big Brother. Date: 21,22,25-FEB-2005 Perform DC tests on SN #7, #8, #9 and #10. This is testing the resistance between the nets GROUND, VCC_LOGIC, VDD_ANALOG, VCC_ANALOG, VEE_ANALOG, VDD_LOGIC, and VCCINT. SN #8 has a short between GROUND and VDD_LOGIC. This was fixed and the resistances for SN#8 were re-measured. SN #10 has a lower resistance between VCCINT and VDD_ANALOG, VDD_LOGIC and GROUND. COMMON PROBE +------------+--------+-------+--------+--------+--------+-------+--------+ |SN 7,8,9,10 | | VCC_ | VDD_ | VCC_ | VEE_ | VDD_ | | | | GROUND | LOGIC | ANALOG | ANALOG | ANALOG | LOGIC | VCCINT | +------------+--------+-------+--------+--------+--------+-------+--------+ CARD | | | | | | | | | 7 | GROUND |XXXXXXXX| 3.1K | 73.62 | 934 | 930 | 112 | 95 | 8 | |XXXXXXXX| 3.1K | 73.26 | 940 | 937 | 0.5 | 95 | 9 | |XXXXXXXX| 3.1K | 73.32 | 944 | 939 | 113 | 92 | 10 | |XXXXXXXX| 3.0K | 73.29 | 938 | 934 | 114 | 86 | | | | | | | | | | CARD +------------+--------+-------+--------+--------+--------+-------+--------+ | | |XXXXXXX| | | | | | 25-Feb 1 | |c 3.0K |XXXXXXX| | | | | | 22-Feb 7 | |c 3.0K |XXXXXXX| | | | | | 22-Feb 7 | VCC_LOGIC |c 3.1K |XXXXXXX| 3.1K | 4.0K | 4.0K | 4.2K | 3.2K | 22-Feb 8 | |c 3.0K |XXXXXXX| 3.1K | 4.0K | 4.0K | 4.0K | 3.2K | 24-Feb 8 | | 3.0K |XXXXXXX| | | | | | 22-Feb 9 | | 3.0K |XXXXXXX| 3.1K | 4.0K | 4.0K | 4.3K | 3.2K | 22-Feb 10 | | 3.0K |XXXXXXX| 3.1K | 4.0K | 4.0K | 4.3K | 3.2K | | | | | | | | | | +------------+--------+-------+--------+--------+--------+-------+--------+ | | | |XXXXXXXX| | | | | 1 | |c 73 |c 3.1K |XXXXXXXX| | | | | 7 | |a 73.65 |c 3.1K |XXXXXXXX| | | | | 7 | VDD_ANALOG |c 73 |c 3.2K |XXXXXXXX| 954 | 954 | 184 | 166 | 8 | | 73.52 | 3.1K |XXXXXXXX| 959 | 960 | 73.80| 167 | 8 | |c 72 |c 3.1K |XXXXXXXX| | | | | 9 | | 73.67 | 3.1K |XXXXXXXX| 960 | 961 | 186 | 165 | 10 | | 73.52 | 3.1K |XXXXXXXX| 956 | 957 | 188 | 159 | | | | | | | | | | CARD +------------+--------+-------+--------+--------+--------+-------+--------+ | | | | |XXXXXXXX| | | | 1 | |c 932 |c 4.0K |c 962 |XXXXXXXX| | | | 7 | |b 928 |c 4.0K |b 954 |XXXXXXXX| | | | 7 | VCC_ANALOG |c 927 |c 4.1K |c 955 |XXXXXXXX| 1.8K | 1.4K | 1.0K | 8 | | 930 | 4.0K | 959 |XXXXXXXX| 1.7K | 933 | 1.0K | 8 | |c 929 |c 4.0K |c 956 |XXXXXXXX| | | | 9 | | 936 | 4.0K | 961 |XXXXXXXX| 1.7K | 1.4K | 1.0K | 10 | | 932 | 4.0K | 957 |XXXXXXXX| 1.7K | 1.5K | 1.0K | | | | | | | | | | CARD +------------+--------+-------+--------+--------+--------+-------+--------+ | | | | | |XXXXXXXX| | | 1 | |c 933 |c 4.0K |c 962 |c 1.7K |XXXXXXXX| | | 7 | |b 929 |c 4.0K |b 955 |c 1.8K |XXXXXXXX| | | 7 | VEE_ANALOG |c 929 |c 4.1K |c 956 |c 1.7K |XXXXXXXX| 1.4K | 1.0K | 8 | | 932 | 4.0K | 959 | 1.7K |XXXXXXXX| 936 | 1.0K | 8 | |c 929 |c 4.0K |c 958 |c 1.7K |XXXXXXXX| | | 9 | | 934 | 4.0K | 962 | 1.7K |XXXXXXXX| 1.4K | 1.0K | 10 | | 928 | 4.0K | 957 | 1.7K |XXXXXXXX| 1.5K | 1.0K | | | | | | | | | | CARD +------------+--------+-------+--------+--------+--------+-------+--------+ | | | | | | |XXXXXXX| | 1 | |c 1.7K |c 4.7K |c 1.7K |c 2.6K |c 2.6K |XXXXXXX| | 7 | |c 2.2K |c 5.2K |c 2.2K |c 3.0K |c 3.0K |XXXXXXX| | 7 | VDD_LOGIC |c 1.9K |c 5.0K |c 1.9K |c 2.8K |c 2.8K |XXXXXXX| 1.9K | 8 | | 0.5 | 3.1K | 73.03 | 932 | 934 |XXXXXXX| 94 | 8 | |c 2.5K |c 5.6K |c 2.6K |c 3.4K |c 3.4K |XXXXXXX| | 9 | | 2.4K | 5.2K | 2.2K | 2.6K | 2.9K |XXXXXXX| 2.1K | 10 | | 1.8K | 5.4K | 2.3K | 3.1K | 2.9K |XXXXXXX| 84 | | | | | | | | | | CARD +------------+--------+-------+--------+--------+--------+-------+--------+ | | | | | | | |XXXXXXXX| 1 | |c 96 |c 3.1K |c 169 |c 1.0K |c 1.0K |b 673 |XXXXXXXX| 7 | |b 170 |c 3.2K |b 237 |b 1.0K |b 1.0K |b 681 |XXXXXXXX| 7 | VCCINT |c 150 |c 3.2K |c 223 |c 1.0K |c 1.0K |c 1.3K |XXXXXXXX| 8 | | 165 | 3.3K | 231 | 1.0K | 1.0K | 155 |XXXXXXXX| 8 | |c 182 |c 3.2K |c 253 |c 1.1K |c 1.1K |b 779 |XXXXXXXX| 9 | | 150 | 3.2K | 214 | 1.0K | 1.0K | 686 |XXXXXXXX| 10 | | 156 | 3.3K | 185 | 1.0K | 1.0K | 669 |XXXXXXXX| | | | | | | | | | +------------+--------+-------+--------+--------+--------+-------+--------+ All values are in Ohms Meter Range a - 200 Ohm b - 2K Ohm c - 20K Ohm d - 200K Ohm e - M Ohm The lower left half of the matrix represents the meter attached to the nets in one polarity and the upper right half of the matrix represents the meter attached in the opposite polarity. This tests if what is measured is resistive or a semiconductor. If the measurement is the same in both polarities then what is measured is resistive. If there is a difference in the measurements then what is measured is not resistive. GROUND, VCC_LOGIC, VDD_ANALOG, VCC_ANALOG and VEE_ANALOG all show a resistive response. VCCINT and VDD_LOGIC are polar and are not resistive. Cards SN#7-10 were initially checked with the lowest setting on the ohm meter that was not overload. To test if all the measurements could be done at the same setting on the ohm meter, one polarity of SN #7 was re-measured with the meter on the 20K Ohm setting. All the measurements were consistent with the measurements made in the initial polarity except for the measurement between VCCINT and VDD_LOGIC which is expected because the voltage/current relationship appears not to be linear for those two nets. This implies that VDD_LOGIC and VCCINT may have a path between them and the other nets that is not resistive but semiconducting. SN#8 had a short between VDD_LOGIC and Ground initially. It was remeasured after the short was fixed. DATE: 02-Mar-2005 Resistance checks for final circuit board check-in. This is step 4 (Ohm meter test) of the circuit board check-in described in http://www.pa.msu.edu/hep/d0/ftp/run2b/l1cal/hardware/adf_2/cards_and_crates/ adf_2_circuit_board_check_in_instructions.txt Boards 1 and 2 were checked by only Jason Biel. Boards 3-10 were checked by both Jason Biel (JDB) and Jorge Benitez (JAB). All values are in Ohms Meter Range a - 200 Ohm b - 2K Ohm c - 20K Ohm d - 200K Ohm e - M Ohm COMMON PROBE +------------+--------+-------+--------+--------+--------+-------+--------+ |SN 7,8,9,10 | | VCC_ | VDD_ | VCC_ | VEE_ | VDD_ | | | | GROUND | LOGIC | ANALOG | ANALOG | ANALOG | LOGIC | VCCINT | CARD +------------+--------+-------+--------+--------+--------+-------+--------+ | | |XXXXXXX| | | | | | JDB 1 | |c 3.1K |XXXXXXX| | | | | | JDB 2 | |C 3.2K |XXXXXXX| | | | | | JAB 3 | |c 3.1K |XXXXXXX| | | | | | JDB 3 | |c 3.1K |XXXXXXX| | | | | | JAB 4 | |c 3.1K |XXXXXXX| | | | | | JDB 4 | |c 3.1K |XXXXXXX| | | | | | JAB 5 | VCC_LOGIC |c 3.2K |XXXXXXX| | | | | | JDB 5 | |c 3.1K |XXXXXXX| | | | | | JAB 6 | |c 3.1K |XXXXXXX| | | | | | JDB 6 | |c 3.0K |XXXXXXX| | | | | | JAB 7 | |c 3.1K |XXXXXXX| | | | | | JDB 7 | |c 3.1K |XXXXXXX| | | | | | JAB 8 | |c 3.1K |XXXXXXX| | | | | | JDB 8 | |c 3.0K |XXXXXXX| | | | | | JAB 9 | |c 3.1K |XXXXXXX| | | | | | JDB 9 | |c 3.1K |XXXXXXX| | | | | | JAB 10 | |c 3.1K |XXXXXXX| | | | | | JDB 10 | |c 3.0K |XXXXXXX| | | | | | | | | | | | | | | +------------+--------+-------+--------+--------+--------+-------+--------+ | | | |XXXXXXXX| | | | | JDB 1 | |c 71 |c 3.0K |XXXXXXXX| | | | | JDB 2 | |c 75 |c 3.1K |XXXXXXXX| | | | | JAB 3 | |c 73 |c 3.2K |XXXXXXXX| | | | | JDB 3 | |c 72 |c 3.0K |XXXXXXXX| | | | | JAB 4 | |c 73 |c 3.2K |XXXXXXXX| | | | | JDB 4 | |c 73 |c 3.1K |XXXXXXXX| | | | | JAB 5 | VDD_ANALOG |c 72K |c 3.1K |XXXXXXXX| | | | | JDB 5 | |c 72 |c 3.1K |XXXXXXXX| | | | | JAB 6 | |c 73 |c 3.0K |XXXXXXXX| | | | | JDB 6 | |c 74 |c 3.1K |XXXXXXXX| | | | | JAB 7 | |c 77 |c 3.1K |XXXXXXXX| | | | | JDB 7 | |c 72 |c 3.1K |XXXXXXXX| | | | | JAB 8 | |c 73 |c 3.1K |XXXXXXXX| | | | | JDB 8 | |c 74 |c 3.1K |XXXXXXXX| | | | | JAB 9 | |c 73 |c 3.1K |XXXXXXXX| | | | | JDB 9 | |c 72 |c 3.1K |XXXXXXXX| | | | | JAB 10 | |c 73 |c 3.1K |XXXXXXXX| | | | | JDB 10 | |c 72 |c 3.1K |XXXXXXXX| | | | | | | | | | | | | | CARD +------------+--------+-------+--------+--------+--------+-------+--------+ | | | | |XXXXXXXX| | | | JDB 1 | |c 936 |c 4.0K |c 965 |XXXXXXXX| | | | JDB 2 | |c 944 |c 4.0K |c 965 |XXXXXXXX| | | | JAB 3 | |c 923 |c 4.0K |c 950 |XXXXXXXX| | | | JDB 3 | |c 926 |c 4.0K |c 954 |XXXXXXXX| | | | JAB 4 | |c 923 |c 4.0K |c 956 |XXXXXXXX| | | | JDB 4 | |c 928 |c 4.0K |c 954 |XXXXXXXX| | | | JAB 5 | VCC_ANALOG |c 926 |c 4.0K |c 953 |XXXXXXXX| | | | JDB 5 | |c 925 |c 4.0K |c 952 |XXXXXXXX| | | | JAB 6 | |c 924 |c 4.0K |c 954 |XXXXXXXX| | | | JDB 6 | |c 925 |c 4.0K |c 951 |XXXXXXXX| | | | JAB 7 | |c 927 |c 4.0K |c 952 |XXXXXXXX| | | | JDB 7 | |c 924 |c 4.0K |c 954 |XXXXXXXX| | | | JAB 8 | |c 925 |c 4.0K |c 956 |XXXXXXXX| | | | JDB 8 | |c 930 |c 4.0K |c 956 |XXXXXXXX| | | | JAB 9 | |c 931 |c 4.0K |c 958 |XXXXXXXX| | | | JDB 9 | |c 930 |c 4.0K |c 960 |XXXXXXXX| | | | JAB 10 | |c 926 |c 4.0K |c 956 |XXXXXXXX| | | | JDB 10 | |c 927 |c 3.9K |c 957 |XXXXXXXX| | | | | | | | | | | | | CARD +------------+--------+-------+--------+--------+--------+-------+--------+ | | | | | |XXXXXXXX| | | JDB 1 | |c 925 |c 3.9K |c 956 |c 1.7K |XXXXXXXX| | | JDB 2 | |c 912 |c 3.9K |c 945 |c 1.7K |XXXXXXXX| | | JAB 3 | |c 923 |c 4.0K |c 950 |c 1.7K |XXXXXXXX| | | JDB 3 | |c 928 |c 4.0K |c 954 |c 1.7K |XXXXXXXX| | | JAB 4 | |c 927 |c 4.0K |c 953 |c 1.7K |XXXXXXXX| | | JDB 4 | |c 931 |c 4.0K |c 955 |c 1.7K |XXXXXXXX| | | JAB 5 | VEE_ANALOG |c 925 |c 4.0K |c 954 |c 1.7K |XXXXXXXX| | | JDB 5 | |c 925 |c 4.0K |c 954 |c 1.7K |XXXXXXXX| | | JAB 6 | |c 924 |c 4.0K |c 952 |c 1.7K |XXXXXXXX| | | JDB 6 | |c 928 |c 4.0K |c 951 |c 1.7K |XXXXXXXX| | | JAB 7 | |c 926 |c 4.0K |c 951 |c 1.7K |XXXXXXXX| | | JDB 7 | |c 925 |c 4.0K |c 954 |c 1.7K |XXXXXXXX| | | JAB 8 | |c 927 |c 4.0K |c 956 |c 1.8K |XXXXXXXX| | | JDB 8 | |c 930 |c 4.0K |c 956 |c 1.7K |XXXXXXXX| | | JAB 9 | |c 930 |c 4.0K |c 959 |c 1.7K |XXXXXXXX| | | JDB 9 | |c 931 |c 4.0K |c 962 |c 1.7K |XXXXXXXX| | | JAB 10 | |c 929 |c 4.0K |c 955 |c 1.7K |XXXXXXXX| | | JDB 10 | |c 930 |c 3.9K |c 957 |c 1.7K |XXXXXXXX| | | | | | | | | | | | CARD +------------+--------+-------+--------+--------+--------+-------+--------+ | | | | | | |XXXXXXX| | JDB 1 | |c 2.0K |c 5.0K |c 2.0K |c 2.8K |c 2.8K |XXXXXXX| | JDB 2 | |c 2.0K |c 5.0K |c 2.1K |c 2.9K |c 2.9K |XXXXXXX| | JAB 3 | |c 2.5K |c 5.5K |c 2.5K |c 3.3K |c 3.4K |XXXXXXX| | JDB 3 | |c 2.3K |c 5.4K |c 2.3K |c 3.2K |c 3.2K |XXXXXXX| | JAB 4 | |c 2.5K |c 5.6K |c 2.6K |c 3.4K |c 3.4K |XXXXXXX| | JDB 4 | |c 2.4K |c 5.5K |c 2.5K |c 3.3K |c 3.3K |XXXXXXX| | JAB 5 | VDD_LOGIC |c 2.3K |c 5.3K |c 2.3K |c 3.2K |c 3.1K |XXXXXXX| | JDB 5 | |c 2.2K |c 5.3K |c 2.3K |c 3.1K |c 3.1K |XXXXXXX| | JAB 6 | |c 2.6K |c 5.5K |c 2.4K |c 3.3K |c 3.3K |XXXXXXX| | JDB 6 | |c 2.7K |c 5.7K |c 2.7K |c 3.5K |c 3.5K |XXXXXXX| | JAB 7 | |c 2.2K |c 5.2K |c 2.2K |c 3.0K |c 3.0K |XXXXXXX| | JDB 7 | |c 2.3K |c 5.3K |c 2.2K |c 3.0K |c 3.0K |XXXXXXX| | JAB 8 | |c 2.6K |c 5.6K |c 2.5K |c 3.3K |c 3.3K |XXXXXXX| | JDB 8 | |c 1.3K |c 5.4K |c 2.4K |c 3.2K |c 3.2K |XXXXXXX| | JAB 9 | |c 2.5K |c 5.5K |c 2.5K |c 3.3K |c 3.3K |XXXXXXX| | JDB 9 | |c 2.3K |c 5.3K |c 2.3K |c 3.1K |c 3.1K |XXXXXXX| | JAB 10 | |c 2.5K |c 5.5K |c 2.5K |c 3.3K |c 3.2K |XXXXXXX| | JDB 10 | |c 2.3K |c 5.3K |c 2.3K |c 3.2K |c 3.2K |XXXXXXX| | | | | | | | | | | CARD +------------+--------+-------+--------+--------+--------+-------+--------+ | | | | | | | |XXXXXXXX| JDB 1 | |c 105 |c 3.1K |c 180 |c 1.0K |c 1.0K |b 660 |XXXXXXXX| JDB 2 | |c 178 |c 3.2K |c 252 |c 1.0K |c 1.1K |b 723 |XXXXXXXX| JAB 3 | |c 175 |c 3.2K |c 246 |c 1.1K |c 1.1K |b 764 |XXXXXXXX| JDB 3 | |c 165 |c 3.2K |c 238 |c 1.0K |c 1.0K |b 765 |XXXXXXXX| JAB 4 | |c 170 |c 3.3K |c 242 |c 1.1K |c 1.1K |b 770 |XXXXXXXX| JDB 4 | |c 168 |c 3.2K |c 238 |c 1.0K |c 1.0K |b 757 |XXXXXXXX| JAB 5 | VCCINT |c 186 |c 3.3K |c 255 |c 1.1K |c 1.1K |b 753 |XXXXXXXX| JDB 5 | |c 179 |c 3.2K |c 251 |c 1.1K |c 1.1K |b 751 |XXXXXXXX| JAB 6 | |c 182 |c 3.3K |c 251 |c 1.1K |c 1.1K |b 760 |XXXXXXXX| JDB 6 | |c 178 |c 3.2K |c 244 |c 1.0K |c 1.1K |b 759 |XXXXXXXX| JAB 7 | |c 171 |c 3.2K |c 241 |c 1.1K |c 1.1K |b 719 |XXXXXXXX| JDB 7 | |c 177 |c 3.2K |c 243 |c 1.0K |c 1.0K |b 730 |XXXXXXXX| JAB 8 | |c 182 |c 3.2K |c 249 |c 1.1K |c 1.1K |b 760 |XXXXXXXX| JDB 8 | |c 174 |c 3.2K |c 240 |c 1.1K |c 1.1K |b 750 |XXXXXXXX| JAB 9 | |c 165 |c 3.2K |c 231 |c 1.1K |c 1.1K |b 735 |XXXXXXXX| JDB 9 | |c 150 |c 3.2K |c 224 |c 1.0K |c 1.0K |b 730 |XXXXXXXX| JAB 10 | |c 123 |c 3.2K |c 192 |c 1.0K |c 1.0K |b 701 |XXXXXXXX| JDB 10 | |c 118 |c 3.1K |c 190 |c 1.0K |c 1.0K |b 693 |XXXXXXXX| | | | | | | | | | +------------+--------+-------+--------+--------+--------+-------+--------+ Date: 02-Mar-2005 Power supply measurement with 2 cards (a non-maestro and a maestro). These are observations of the LED display on the power-supply for the Weiner crate after the power has been turned on. There is a vertical interconnect card in slot 1, a card under test in slot 8, and a maestro card in slot 20 (for SN1, a maestro card, in slot 8, a non-maestro card was in slot 20). S/N Power U5 +3v3 U1 +5v0 V A V A V A V A ------------------------------------------------------------------------------------- 1 35W 5.01V 0.9A 3.26V 1A 5.02V 1.1A 5.01V 5A 2 35W 5.01V 0.9A 3.28V 1A 5.02V 1.1A 5.02V 5A 3 35W 5.01V 0.9A 3.28V 1A 5.02V 1.0A 5.02V 5A 4 35W 5.01V 0.9A 3.27V 1A 5.02V 1.0A 5.02V 4A 5 35W 5.01V 0.9A 3.27V 1A 5.02V 1.1A 5.02V 4A 6 35W 5.01V 0.9A 3.28V 1A 5.02V 1.1A 5.02V 4A 7 35W 5.01V 0.9A 3.27V 1A 5.02V 1.0A 5.02V 5A 8 35W 5.01V 0.9A 3.28V 1A 5.02V 1.1A 5.02V 4A 9 35W 5.01V 0.9A 3.28V 1A 5.02V 1.1A 5.02V 4A 10 35W 5.01V 0.9A 3.28V 1A 5.02V 1.0A 5.02V 4A Date: 02-Mar-2005 PLL tracking measurements. These are observations of the MONITOR_PLL signal on the P4 connector with a voltmeter. S/N (Time since power on [min:sec], Voltage) ------------------------------------------------------------------------------------- 1 (2:00, 2.377V) (4:00, 2.380V) (13:00, 2.388V) 2 (4:00, 2.294V) (10:00, 2.291V) 3 (3:00, 2.301V) (12:00, 2.301V) 4 (2:00, 2.399V) 5 (3:00, 2.374V) (9:00, 2.379V) (14:00, 2.386V) 6 (9:00, 2.062V) 7 (2:00, 2.345V) (5:00, 2.354V) (11:00, 2.360V) 8 (2:00, 1.853V) (5:00, 1.854V) (11:00, 1.860V) 9 (2:00, 2.359V) (4:00, 2.361V) (11:00, 2.361V) 10 (2:00, 2.329V) (4:00, 2.335V) (12:00, 2.340V) Date: 02-Mar-2005 DC/DC converter measurements. These are observations of the outputs of the DC/DC converters on the ADF-2 card. These voltages were measured on the "+" terminal of C1323 and C1333 with the card plugged into the crate. These measurements were made with a multi-meter. These observations were made after the PAL was programmed. S/N VDD_LOGIC VCCINT DC AC DC AC ------------------------------------------------------------------------------------- 1 3.284V 0.001V 1.502V 0.000V 2 3.294V 0.000V 1.494V 0.000V 3 3.291V 0.000V 1.493V 0.000V 4 3.299V 0.000V 1.503V 0.000V 5 3.285V 0.000V 1.493V 0.000V 6 3.290V 0.000V 1.495V 0.000V 7 3.293V 0.000V 1.499V 0.000V 8 3.293V 0.000V 1.499V 0.000V 9 3.289V 0.000V 1.504V 0.000V 10 3.298V 0.000V 1.494V 0.000V Date: 09-Mar-2005 Received from ADCO 20 boards of species A. Date: 10-Mar-2005 Returned 20 boards of species A to ADCO to rework P3 connectors. Date: 11-Mar-2005 Received from ADCO 20 boards of species A with P3 connectors repressed into the cards. Date: 18-Mar-2005 Received 46 cards from ADCO. 26 Blue, 11 Yellow and 9 Green. ------------------------------------------------------------------------------- The following notes are about tests that have been done in the System Test Crate. 8:11-APR-2005 System Crate Tests DC-DC Converter Operation with RRT Run Random Register Test over all 20 cards in the System Test Crate. All 20 of these ADF-2 cards have had C1354 470 pFd installed on their BG_IN_1_B backplane signal. About 6 x 10**9 RRT loops were run over these 3 days with no shutdown of the DC-DC converters or loss of the Data Path FPGA configuration. There was one I/O error in all these loops which was corrected on the 2nd try. Note book #7 page 105. RRT runs at about: 50k loops per second, 3 meg loops per minute, 180 meg loops per hour. 12-APR-2005 System Crate Tests BX_X8_Clock Jitter with RRT With the digital scope watch the BX_X8_Clock picked up from connector P4 from the ADF-2 cards in slots 3 and 20. At the same time run Random Register Test on all 20 cards in the System Test Crate. This crate is under control of the SCLD using the standard setup of the SCLD connected to slot 11. With scope traces for both BX_X8_Clock signals being displayed set the scope for infinite persistence. Let it run over night and then compare the width of the scope trace that was used to trigger the scope to the width of the trace that comes from the other end of the crate. They look basically identical. The vertical edges of these traces look about 1.2 nsec wide. 13-APR-2005 System Crate Tests Channel Link Test with RRT In the System Test Crate run Random Register Test on all 20 cards except for slot #17. In slot #17 run the Channel Link Test. Run the Channel Link Test over night and Big Brother says zero errors. 26-Apr-2005 System Crate Tests 1) Run Find_Dac in a loaded crate Copy and modify Find_Dac.cmd into PlayCrate_Find_Dac.cmd This command file loads T4 in all slots #2-21 and runs Find_Dac on all channels of all cards. The logfile is \L1Cal_IIb\LogFiles\CommandFiles\PlayCrate_Find_Dac.log There does not seem to be any visible change in the noise, but this needs to be examined in more details: Make a table comparing the values recorded by FInd_DAC during production testing (one card in the crate at a time) and the values collected here (loaded crate). Use Excel to visualize the data. - The value picked by Find_DAC to produce 490 counts did not significantly change - The amount of noise in each tower did not significantly change - by overlapping the graphs of all cards, one can NOT see any systematic tendency for certain channels to have more or less noise than other channels. 2) Look for any added noise generated during VME IO Copy and modify PlayCrate_Find_Dac.cmd into PlayCrate_Capture_Adc.cmd This command file loads T6 in all slots #2-21 and runs Capture_Dac on all channels of all cards in the crate, collecting one 4k sample per channel. This creates 640 AdcCapture files. The maximum data is reported and recorded in the logfile. It does not seem to catch anything higher than one count above the average of 490. The GUI (python) command file requests the TCC (C++) part of the code to use T6 to capture ADC data with no actual threshold requirement. TCC sets up the T6 control register and immediately starts doing 4k VME reads to retrieve the content of the slice. It takes 4k*30ns=135us for T6 to fill the sample, thus TCC will have read some 135/5=27 VME read cycles from the same FPGA during that time. The logfile is \L1Cal_IIb\LogFiles\CommandFiles\PlayCrate_Find_Dac.log Using a search tool to tally the content of the files (e.g. TextPad) we can do a global histogram of all entries for all 20 cards * 32 channels * 4096 samples = 2,621,440 ADC samples Value Instances 489 18808 490 2587256 491 15374 492 2 ------- tot 2621440 This does not look quite symmetrical, but it still shows that no significant noise peak was captured. The two entries at 492 happened for SN#A13 TT_HD(2,1) and SN#A15 TT_HD(2,1). This is the same channel on two different cards. These are otherwise quite channels, and NOT intrinsically noisier channels. 3) Channel_Link tests Run the channel link tests while using VME_Access to hassle a register on the same card. The card connected to Big Brother in the system crate is in Slot #17, thus its base address for Master#0/Slave#1 is 0x11440000 - VME Access was told to repeatedly read VME address 0x11440410 for ~ 10 minutes. Big Brother did not detect any error. - VME Access was told to repeatedly write VME address 0x11440410 for ~ 10 minutes. Big Brother only detected errors in the expected byte lane #8 corresponding to this seed register. 8:26-April-2005 Testing done of cards for crate M104(A1-A16,B1-B4). 11:13-May-2005 After ECO#1 was installed, the cards for crate M109 (C14-C21 and D1-D12) were put in the system test crate in the order specified in http://www.pa.msu.edu/hep/d0/ftp/run2b/l1cal/hardware/adf_2/cards_and_crates/ adf_crate_card_layout.txt The set of cards were tested with the command file Play_RRT_FPGA_Configuration_Loss.cmd. This performed a 3 billion loop random register test on all 20 ADF-2 cards. There were no errors. 6 Billion addition loops of random register testing was passed with no errors. The PAL_LED_1 is off at power-up for all cards. 16:20-May-2005 After ECO#1 was installed, the cards for crate M106 (B5-B16 and C6-C13) were put in the system test crate in the order specified in http://www.pa.msu.edu/hep/d0/ftp/run2b/l1cal/hardware/adf_2/cards_and_crates/ adf_crate_card_layout.txt Slots 2-13 have their PAL_LED_1 on at power-up. The LEDs come on together, not on a per card basis as the card power comes up. Some PAL_LED_1 flicker before the VDD_LOGIC power is enabled. This implies that VDD_LOGIC is not zero before BG_IN_1_B is asserted. The value of the control bit in the PAL for the LED is asserted for these cards. This is not consistent with the power-on state specified for that control bit in the PAL firmware. The register bit CNTRL_PAL_LED_1 can be written to successfully and the PAL_LED_1 can be toggled on and off for all cards. The command file Play_Test_PAL_Registers_Startup_Values.cmd tests the three Read/Write registers in the PAL on all ADF-2 cards in the system test crate for the correct power up values. If an incorrect value is found, the correct value is written into the register. The set of cards were first tested with the command file Play_Test_PAL_Registers_Startup_Values.cmd to test for the correct power-up values in the PAL registers. If incorrect values are found they are corrected. A 1 billion loop random register test was run and passed without errors next. The Play_Test_PAL_Registers_Startup_Values.cmd was rerun and passed without errors. This proves that the PAL register values were not compromised with heavy I/O to all cards. The command file PLAY_Test_Crate_Status_Lines.cmd was run next. This tested if each card could drive all 4 crate status lines in all 16 possible combinations and be successfully read out through all other cards in the crate. This passed without errors. Play_RRT_FPGA_Configuration_Loss.cmd was run again and 9 billion loops were passed without errors. 23:25-May-2005 After ECO#1 was installed, the cards for crate M111 (D13-D32) were put in the system test crate in the order specified in http://www.pa.msu.edu/hep/d0/ftp/run2b/l1cal/hardware/adf_2/cards_and_crates/ adf_crate_card_layout.txt Slots 2-12 has their PAL_LED_1 on at power-up except slots 8 and 10 (D19 and D21) do not have their PAL_LED_1 on but their PAL_LED_1 do not function. The test Play_Test_PAL_Registers_Startup_Values.cmd was run and the register bit CNTRL_PAL_LED_1 was incorrect for slots A-B. A 1 million loop random register test was run and there were no errors. Play_Test_PAL_Registers_Startup_Values.cmd was rerun and there were no errors. PLAY_Test_Crate_Status_Lines.cmd was run and there were no errors. 9 billion loops of random register test were passed with no unexplained errors. There were errors but they occurred when the Production test crate was powered on or off or when the grey arm lamp by the soldering station was turned on or off. Turning on/off the Production test crate or grey arm lamp caused errors in the random register test 100% of the time. The vertical interconnect slave cards were swapped between the production test crate and the system test crate. The problem still occured almost entirely in the system test crate so the vertical interconnect cards are not the problem. The vertical interconnect cables were swapped between crates. The problem still occured almost entirely in the system test crate so the problem is not with the vertical interconnect cables or the port on the vertical insterconnect master. The Produciton test crate case is attached to the communications crate back plane with a wire. The System test crate case is attached to the production test crate case with a wire. The system test crate is resistively further from the communications crate than the production test crate so this may explain why the system test crate is more sensitive. 26:30-May-2005 After ECO#1 was installed, all available spare cards (A17-A21, B17-B21, C1, C2, C4, D33-D37) were put in the system test crate. C3 and C5 are at Fermi Lab so they are not tested at this time. D31 and D32 are in the system test crate in their place. The cards are placed in the system test crate in the following order: Slot Currently Number Installed ------ ------------ 2 A17 3 A18 4 A19 5 A20 6 A21 7 B17 8 B18 9 B19 10 B21 11 M C1 12 C2 13 C4 14 D33 15 D34 16 D35 17 D36 18 D37 19 D31 20 D32 21 B20 Slots 2-18 has their PAL_LED_1 on at power-up. The test Play_Test_PAL_Registers_Startup_Values.cmd was run and the register bit CNTRL_PAL_LED_1 was incorrect for slots 2-18. A 1 million loop random register test was run and there were no errors. Play_Test_PAL_Registers_Startup_Values.cmd was rerun and there were no errors. PLAY_Test_Crate_Status_Lines.cmd was run and there were no errors. 12 billion loops of random register test were passed with no errors. 01:03 Jun 2005 The PRODUCTION test crate is populated as follows: Slot Currently Number Installed ------ ------------ 2 EMPTY 3 EMPTY 4 EMPTY 5 EMPTY 6 A17 7 B18 8 EMPTY 9 A19 10 C4 11 A20 12 B17 13 B18 14 B19 15 B20 16 D33 17 D34 18 D35 19 D36 20 M C1 21 C2 A 12 Billion loop random register test was started on 1-Jun-2005 at 12pm. 9 Billion loops passed with no errors or warning. Test terminated at 2Pm on 3-Jun-2005. 20:24-June-2005 The ADF Transition card has been installed in slot 3 and the channel link has been briefly tested on all three channels. The cables need to be plugged in 180 degrees from how they plug into the backplane. A cable plugs into the bottom of the connector. Additional cables skip a row of pines between them. Communications to the SCLD were not successful at this time. They work without the ADF Transition card. The cable has been tried in each orientation (rotated 180 degrees). An extended test has been run on channel 0. The script "Crate_Channel_Link_and_Random_Register_Test.cmd" was run. The channel link test was performed on the maestro card in slot 3 with the ADF Transistion card attached to the back. 12 billion loops of random register test completed without errors. 1.5e13 Channel Link counts (words?) completed without error. 23-June Start Channel 2 test and concurrent random register test. 24-June 3 billion loops of random register test on all cards in the crate succeeded. 4.44e12 Channel Link counts completed without error. Start Channel 1 test and concurrent random register test. 28-June 3 Billion loop random register test completed without errors. 2.00e13 Channel Link counts completed without error. Start Channel 2 test and concurrent random registertest. 29-June 3 billion loops of random register test on all cards in the crate succeeded. 3.9e12 Channel Link counts completed without error. 30-June-2005 : 20-Jul-2005 45 Billion RRT loops completed without any errors. 1.02e14 counts of Channel Link test without errors.