cpldfit: version G.31a Xilinx Inc. Fitter Report Design Name: bcp Date: 9-25-2004, 3:25PM Device Used: XC95144XL-5-TQ144 Fitting Status: Successful **************************** Resource Summary **************************** Macrocells Product Terms Registers Pins Function Block Used Used Used Used Inputs Used 122/144 ( 85%) 313 /720 ( 43%) 84 /144 ( 58%) 117/117 (100%) 329/432 ( 76%) PIN RESOURCES: Signal Type Required Mapped | Pin Type Used Remaining ------------------------------------|--------------------------------------- Input : 57 57 | I/O : 109 0 Output : 50 50 | GCK/IO : 3 0 Bidirectional : 8 8 | GTS/IO : 4 0 GCK : 2 2 | GSR/IO : 1 0 GTS : 0 0 | GSR : 0 0 | ---- ---- Total 117 117 MACROCELL RESOURCES: Total Macrocells Available 144 Registered Macrocells 84 Non-registered Macrocell driving I/O 8 GLOBAL RESOURCES: Signal 'PAL_BX_CLOCK_in_stdl' mapped onto global clock net GCK1. Signal 'PAL_BX_X8_CLOCK_in_stdl' mapped onto global clock net GCK3. Global output enable net(s) unused. Global set/reset net(s) unused. POWER DATA: There are 122 macrocells in high performance mode (MCHP). There are 0 macrocells in low power mode (MCLP). There are a total of 122 macrocells used (MC). End of Resource Summary *************** Summary of Required Resources ****************** ** LOGIC ** Signal Total Signals Loc Pwr Slew Pin Pin Pin Reg Init Name Pt Used Mode Rate # Type Use State ADC_ENABLE_reg_stdl 3 14 FB1_12 STD SLOW 26 I/O O RESET BOARD_CONTROL_1_DATA_int_stdlv(3) 3 14 FB6_18 STD (b) (b) RESET BOARD_CONTROL_1_DATA_int_stdlv(4) 3 14 FB2_18 STD (b) (b) RESET BOARD_CONTROL_1_DATA_int_stdlv(5) 3 14 FB2_17 STD 15 I/O I RESET BOARD_CONTROL_1_DATA_int_stdlv(6) 3 14 FB6_17 STD 125 I/O I SET BOARD_CONTROL_2_DATA_int_stdlv(6) 3 14 FB6_15 STD 124 I/O I SET CNFG_CCLK_out_stdl 2 13 FB2_11 STD SLOW 9 I/O O RESET CNFG_CS_B_reg_stdlv(0) 3 14 FB2_13 STD SLOW 12 I/O O SET CNFG_CS_B_reg_stdlv(1) 3 14 FB2_5 STD SLOW 2 GTS/I/O O SET CNFG_PROG_B_REQ_reg_stdlv(0) 3 14 FB2_16 STD 14 I/O I SET CNFG_PROG_B_REQ_reg_stdlv(1) 3 14 FB2_15 STD 13 I/O I SET CNFG_PROG_B_out_stdlv(0) 2 6 FB2_14 STD SLOW 11 I/O O SET CNFG_PROG_B_out_stdlv(1) 2 6 FB2_1 STD SLOW 142 I/O O SET CNFG_RDWR_B_reg_stdl 3 14 FB2_12 STD SLOW 10 I/O O SET CNT_BIT_VAL_1_int_stdl 0 0 FB5_18 STD (b) (b) RESET CNT_BIT_VAL_2_int_stdl 1 1 FB5_17 STD 69 I/O I RESET CNT_BIT_VAL_4_inout_stdl 3 7 FB3_5 STD SLOW 33 I/O O RESET DAC_CHIP_SELECT_B_out_stdl 2 6 FB4_14 STD SLOW 136 I/O O SET DAC_SERIAL_DATA_CLOCK_out_stdl 2 13 FB4_10 STD SLOW 135 I/O O SET DATA_BUF_DIR_out_stdl 2 9 FB2_8 STD SLOW 5 GTS/I/O O SET DATA_BUF_ENB_B_out_stdl 2 8 FB5_2 STD SLOW 52 I/O O SET DATA_TO_FIRST_DAC_INPUT_out_stdl 2 12 FB4_12 STD SLOW 134 I/O O RESET DRV_CRATE_STATUS_reg_stdlv(0) 3 14 FB6_16 STD SLOW 117 I/O O RESET DRV_CRATE_STATUS_reg_stdlv(1) 3 14 FB6_11 STD SLOW 119 I/O O RESET DRV_CRATE_STATUS_reg_stdlv(2) 3 14 FB6_12 STD SLOW 120 I/O O RESET DRV_CRATE_STATUS_reg_stdlv(3) 3 14 FB6_14 STD SLOW 121 I/O O RESET DRV_CRATE_TO_SCLD_reg_stdlv(0) 3 14 FB1_10 STD SLOW 31 I/O O RESET DRV_CRATE_TO_SCLD_reg_stdlv(1) 3 14 FB1_16 STD SLOW 35 I/O O RESET DRV_DTACK_out_stdl 3 9 FB5_6 STD SLOW 54 I/O O RESET DRV_PAL_LED_out_stdlv(0) 2 18 FB6_9 STD SLOW 116 I/O O SET DRV_PAL_LED_out_stdlv(1) 2 5 FB4_5 STD SLOW 128 I/O O SET DS1_tmp_int_stdl 1 1 FB7_11 STD 82 I/O I RESET IDLE_STATE_int_stdl 6 12 FB8_18 STD (b) (b) SET IO_1_STATE_int_stdl 2 12 FB8_14 STD 102 I/O I RESET IO_2_STATE_int_stdl 4 13 FB8_15 STD 104 I/O I RESET LATCH_1_STATE_int_stdl 2 11 FB8_13 STD 103 I/O I RESET LATCH_2_STATE_int_stdl 2 11 FB8_11 STD 98 I/O I RESET LED_STRETCHER_CB16CE/Q(0) 3 19 FB6_13 STD (b) (b) RESET LED_STRETCHER_CB16CE/Q(1) 3 7 FB1_18 STD (b) (b) RESET LED_STRETCHER_CB16CE/Q(10) 2 8 FB1_9 STD 22 I/O I RESET LED_STRETCHER_CB16CE/Q(11) 2 7 FB1_8 STD 21 I/O I RESET LED_STRETCHER_CB16CE/Q(12) 2 6 FB1_7 STD (b) (b) RESET LED_STRETCHER_CB16CE/Q(13) 2 5 FB7_15 STD 87 I/O I RESET LED_STRETCHER_CB16CE/Q(2) 3 7 FB1_17 STD 30 GCK/I/O GCK/I RESET LED_STRETCHER_CB16CE/Q(3) 3 7 FB1_13 STD (b) (b) RESET LED_STRETCHER_CB16CE/Q(4) 3 7 FB1_11 STD 24 I/O I RESET LED_STRETCHER_CB16CE/Q(5) 3 7 FB7_18 STD (b) (b) RESET LED_STRETCHER_CB16CE/Q(6) 3 7 FB7_17 STD 88 I/O I RESET LED_STRETCHER_CB16CE/Q(7) 2 11 FB6_7 STD (b) (b) RESET LED_STRETCHER_CB16CE/Q(8) 2 10 FB2_10 STD 7 I/O I RESET LED_STRETCHER_CB16CE/Q(9) 2 9 FB1_6 STD 20 I/O I RESET LED_STRETCHER_CB16CE/Q__n0000(10)/LED_STRETCHER_CB16CE/Q__n0000(10)_D 2 11 FB1_5 STD 19 I/O I LED_STRETCHER_CB16CE/Q__n0000(11)/LED_STRETCHER_CB16CE/Q__n0000(11)_D 2 12 FB6_3 STD (b) (b) LED_STRETCHER_CB16CE/Q__n0000(12)/LED_STRETCHER_CB16CE/Q__n0000(12)_D 2 13 FB6_2 STD 106 I/O I LED_STRETCHER_CB16CE/Q__n0000(7)/LED_STRETCHER_CB16CE/Q__n0000(7)_D 2 8 FB4_11 STD 132 I/O I LED_STRETCHER_CB16CE/Q__n0000(8)/LED_STRETCHER_CB16CE/Q__n0000(8)_D 2 9 FB1_3 STD 17 I/O I LED_STRETCHER_CB16CE/Q__n0000(9)/LED_STRETCHER_CB16CE/Q__n0000(9)_D 2 10 FB1_2 STD 16 I/O I LED_STRETCHER_CE_int_stdl/LED_STRETCHER_CE_int_stdl_D2 2 15 FB6_1 STD (b) (b) LOOP_FILTER_REF_inout_stdl 1 4 FB3_1 STD SLOW 39 I/O O RESET N1861/N1861_D2 1 6 FB2_7 STD (b) (b) N1871/N1871_D2 1 6 FB2_6 STD 3 GTS/I/O I N1881/N1881_D2 1 6 FB2_4 STD 4 I/O I NEXT_STATE_QUIESCENT_B_int_stdl 1 1 FB4_9 STD 131 I/O I NEXT_STATE_QUIESCENT_int_stdl 6 11 FB8_17 STD 105 I/O I SET OCB_CHIP_SEL_B_int_stdlv(0) 1 1 FB4_8 STD 130 I/O I OCB_CHIP_SEL_B_int_stdlv(1) 1 1 FB4_7 STD (b) (b) OCB_CHIP_SEL_B_out_stdlv(0) 2 6 FB4_16 STD SLOW 139 I/O O SET OCB_CHIP_SEL_B_out_stdlv(1) 2 6 FB4_15 STD SLOW 138 I/O O SET OCB_CHIP_SEL_int_stdlv(0) 3 14 FB4_18 STD (b) (b) OCB_CHIP_SEL_int_stdlv(1) 3 14 FB4_13 STD 137 I/O I OCB_DATA_inout_stdlv(0) 8 16 FB8_16 STD SLOW 107 I/O I/O RESET OCB_DATA_inout_stdlv(1) 8 16 FB8_12 STD SLOW 100 I/O I/O RESET OCB_DATA_inout_stdlv(2) 7 15 FB8_3 STD SLOW 95 I/O I/O RESET OCB_DATA_inout_stdlv(3) 3 11 FB8_8 STD SLOW 94 I/O I/O RESET OCB_DATA_inout_stdlv(4) 3 11 FB7_12 STD SLOW 85 I/O I/O RESET OCB_DATA_inout_stdlv(5) 6 14 FB7_16 STD SLOW 83 I/O I/O RESET OCB_DATA_inout_stdlv(6) 5 13 FB7_7 STD SLOW 77 I/O I/O RESET OCB_DATA_inout_stdlv(7) 4 12 FB7_3 STD SLOW 75 I/O I/O RESET OCB_DIRECTION_out_stdl 5 10 FB2_9 STD SLOW 6 GTS/I/O O SET OCB_WRITE_STRB_B_inout_stdl 4 10 FB4_17 STD SLOW 140 I/O O SET PAL_ACCESS_inout_stdlv(0) 2 2 FB1_4 STD SLOW 25 I/O O PAL_ACCESS_inout_stdlv(1) 2 2 FB3_3 STD SLOW 41 I/O O RESET PAL_ACCESS_inout_stdlv(10) 5 11 FB5_9 STD SLOW 57 I/O O SET PAL_ACCESS_inout_stdlv(11) 2 2 FB5_11 STD SLOW 58 I/O O PAL_ACCESS_inout_stdlv(12) 2 2 FB6_5 STD SLOW 110 I/O O PAL_ACCESS_inout_stdlv(13) 2 3 FB6_4 STD SLOW 111 I/O O PAL_ACCESS_inout_stdlv(14) 2 6 FB6_6 STD SLOW 112 I/O O PAL_ACCESS_inout_stdlv(15) 4 15 FB6_8 STD SLOW 113 I/O O SET PAL_ACCESS_inout_stdlv(16) 4 15 FB6_10 STD SLOW 115 I/O O RESET PAL_ACCESS_inout_stdlv(2) 4 10 FB3_11 STD SLOW 43 I/O O RESET PAL_ACCESS_inout_stdlv(3) 9 16 FB3_4 STD SLOW 44 I/O O PAL_ACCESS_inout_stdlv(4) 3 7 FB3_12 STD SLOW 45 I/O O RESET PAL_ACCESS_inout_stdlv(5) 3 9 FB3_7 STD SLOW 46 I/O O SET PAL_ACCESS_inout_stdlv(6) 3 10 FB3_10 STD SLOW 48 I/O O SET PAL_ACCESS_inout_stdlv(7) 6 11 FB3_14 STD SLOW 49 I/O O SET PAL_ACCESS_inout_stdlv(8) 2 15 FB3_15 STD SLOW 50 I/O O PAL_ACCESS_inout_stdlv(9) 3 8 FB3_17 STD SLOW 51 I/O O RESET PAL_FIRST_X8_EDGE_out_stdl 2 7 FB3_6 STD SLOW 34 I/O O RESET PHASE_DET_OUT_out_stdl 2 2 FB3_9 STD SLOW 40 I/O O RCVD_BX_CLOCK_inout_stdl 1 4 FB3_2 STD SLOW 32 GCK/I/O O RESET SER_DC_BALANCE_reg_stdl 3 14 FB1_14 STD SLOW 27 I/O O RESET SER_DESKEW_B_reg_stdl 3 14 FB1_15 STD SLOW 28 I/O O SET SET_QUIESCENT_STATE_int_stdl 2 11 FB8_10 STD 101 I/O I RESET SYSRESET_TMP_1_int_stdl 1 1 FB8_9 STD 96 I/O I SET SYSRESET_TMP_2_int_stdl 1 1 FB8_7 STD (b) (b) SET SYSRESET_TMP_3_int_stdl 1 1 FB8_6 STD 93 I/O I SET VALID_CYCLE_B_int_stdl 1 1 FB4_6 STD 129 I/O I VME_LTCH_CLK_out_stdl 2 6 FB5_5 STD SLOW 53 I/O O RESET _n0104/_n0104_D2 1 6 FB7_10 STD 79 I/O I _n0105/_n0105_D2 1 6 FB7_9 STD 80 I/O I _n0106/_n0106_D2 1 6 FB7_8 STD 78 I/O I _n0107/_n0107_D2 1 6 FB7_6 STD 76 I/O I _n0108/_n0108_D2 1 6 FB7_5 STD 74 I/O I _n0109/_n0109_D2 1 6 FB2_3 STD (b) (b) _n0110/_n0110_D2 1 6 FB7_4 STD (b) (b) _n0111/_n0111_D2 1 6 FB7_2 STD 71 I/O I _n0112/_n0112_D2 1 6 FB7_1 STD (b) (b) _n0113/_n0113_D2 1 6 FB8_1 STD (b) (b) _n0114/_n0114_D2 1 6 FB1_1 STD 23 I/O I _n0115/_n0115_D2 1 6 FB2_2 STD 143 GSR/I/O I _n0142/_n0142_D 2 2 FB7_14 STD 86 I/O I _n0145/_n0145_D 2 2 FB7_13 STD 81 I/O I ** INPUTS ** Signal Loc Pin Pin Pin Name # Type Use CNFG_BUSY_in_stdlv(0) FB2_16 14 I/O I CNFG_BUSY_in_stdlv(1) FB2_4 4 I/O I CNFG_DONE_in_stdlv(0) FB2_17 15 I/O I CNFG_DONE_in_stdlv(1) FB2_10 7 I/O I CNFG_INIT_B_in_stdlv(0) FB2_15 13 I/O I CNFG_INIT_B_in_stdlv(1) FB2_6 3 GTS/I/O I CRATE_STATUS_B_in_stdlv(0) FB6_15 124 I/O I CRATE_STATUS_B_in_stdlv(1) FB6_17 125 I/O I CRATE_STATUS_B_in_stdlv(2) FB4_1 118 I/O I CRATE_STATUS_B_in_stdlv(3) FB4_2 126 I/O I FPGA_0_STATUS_in_stdlv(0) FB1_8 21 I/O I FPGA_0_STATUS_in_stdlv(1) FB1_9 22 I/O I FPGA_0_STATUS_in_stdlv(2) FB1_1 23 I/O I FPGA_0_STATUS_in_stdlv(3) FB1_11 24 I/O I FPGA_1_STATUS_in_stdlv(0) FB1_2 16 I/O I FPGA_1_STATUS_in_stdlv(1) FB1_3 17 I/O I FPGA_1_STATUS_in_stdlv(2) FB1_5 19 I/O I FPGA_1_STATUS_in_stdlv(3) FB1_6 20 I/O I LAST_DAC_OUTPUT_DATA_in_stdl FB4_13 137 I/O I LTCHD_AM_in_stdlv(0) FB5_10 68 I/O I LTCHD_AM_in_stdlv(1) FB5_7 66 I/O I LTCHD_AM_in_stdlv(2) FB5_15 64 I/O I LTCHD_AM_in_stdlv(3) FB5_14 61 I/O I LTCHD_AM_in_stdlv(4) FB5_3 59 I/O I LTCHD_AM_in_stdlv(5) FB5_13 70 I/O I LTCHD_IACK_B_in_stdl FB5_12 60 I/O I LTCHD_WRITE_B_in_stdl FB5_17 69 I/O I OCB_ADRS_in_stdlv(1) FB6_2 106 I/O I OCB_ADRS_in_stdlv(10) FB8_6 93 I/O I OCB_ADRS_in_stdlv(11) FB8_5 92 I/O I OCB_ADRS_in_stdlv(12) FB8_2 91 I/O I OCB_ADRS_in_stdlv(13) FB7_17 88 I/O I OCB_ADRS_in_stdlv(14) FB7_15 87 I/O I OCB_ADRS_in_stdlv(15) FB7_14 86 I/O I OCB_ADRS_in_stdlv(16) FB7_11 82 I/O I OCB_ADRS_in_stdlv(17) FB7_13 81 I/O I OCB_ADRS_in_stdlv(18) FB7_9 80 I/O I OCB_ADRS_in_stdlv(19) FB7_10 79 I/O I OCB_ADRS_in_stdlv(2) FB8_17 105 I/O I OCB_ADRS_in_stdlv(20) FB7_8 78 I/O I OCB_ADRS_in_stdlv(21) FB7_6 76 I/O I OCB_ADRS_in_stdlv(22) FB7_5 74 I/O I OCB_ADRS_in_stdlv(23) FB7_2 71 I/O I OCB_ADRS_in_stdlv(3) FB8_15 104 I/O I OCB_ADRS_in_stdlv(4) FB8_13 103 I/O I OCB_ADRS_in_stdlv(5) FB8_14 102 I/O I OCB_ADRS_in_stdlv(6) FB8_10 101 I/O I OCB_ADRS_in_stdlv(7) FB8_11 98 I/O I OCB_ADRS_in_stdlv(8) FB8_4 97 I/O I OCB_ADRS_in_stdlv(9) FB8_9 96 I/O I PAL_BX_CLOCK_in_stdl FB1_17 30 GCK/I/O GCK/I PAL_BX_X8_CLOCK_in_stdl FB3_8 38 GCK/I/O GCK RCVD_DS1_in_stdl FB5_8 56 I/O I VME_GEO_B_in_stdlv(0) FB4_6 129 I/O I VME_GEO_B_in_stdlv(1) FB4_8 130 I/O I VME_GEO_B_in_stdlv(2) FB4_9 131 I/O I VME_GEO_B_in_stdlv(3) FB4_11 132 I/O I VME_GEO_B_in_stdlv(4) FB4_3 133 I/O I VME_SYSRESET_B_in_stdl FB2_2 143 GSR/I/O I End of Resources *********************Function Block Resource Summary*********************** Function # of FB Inputs Signals Total O/IO IO Block Macrocells Used Used Pt Used Req Avail FB1 18 43 43 44 6/0 15 FB2 18 40 40 41 8/0 15 FB3 14 52 52 44 14/0 15 FB4 14 43 43 28 7/0 15 FB5 7 22 22 15 5/0 14 FB6 18 43 43 48 10/0 13 FB7 18 43 43 39 0/4 15 FB8 15 43 43 54 0/4 15 ---- ----- ----- ----- 122 313 50/8 117 *********************************** FB1 *********************************** Number of function block inputs used/remaining: 43/11 Number of signals used by logic mapping into function block: 43 Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin Name Pt Pt Pt Pt Mode # Type Use _n0114/_n0114_D2 1 0 0 4 FB1_1 STD 23 I/O I LED_STRETCHER_CB16CE/Q__n0000(9)/LED_STRETCHER_CB16CE/Q__n0000(9)_D 2 0 0 3 FB1_2 STD 16 I/O I LED_STRETCHER_CB16CE/Q__n0000(8)/LED_STRETCHER_CB16CE/Q__n0000(8)_D 2 0 0 3 FB1_3 STD 17 I/O I PAL_ACCESS_inout_stdlv(0) 2 0 0 3 FB1_4 STD 25 I/O O LED_STRETCHER_CB16CE/Q__n0000(10)/LED_STRETCHER_CB16CE/Q__n0000(10)_D 2 0 0 3 FB1_5 STD 19 I/O I LED_STRETCHER_CB16CE/Q(9) 2 0 0 3 FB1_6 STD 20 I/O I LED_STRETCHER_CB16CE/Q(12) 2 0 0 3 FB1_7 STD (b) (b) LED_STRETCHER_CB16CE/Q(11) 2 0 0 3 FB1_8 STD 21 I/O I LED_STRETCHER_CB16CE/Q(10) 2 0 0 3 FB1_9 STD 22 I/O I DRV_CRATE_TO_SCLD_reg_stdlv(0) 3 0 0 2 FB1_10 STD 31 I/O O LED_STRETCHER_CB16CE/Q(4) 3 0 0 2 FB1_11 STD 24 I/O I ADC_ENABLE_reg_stdl 3 0 0 2 FB1_12 STD 26 I/O O LED_STRETCHER_CB16CE/Q(3) 3 0 0 2 FB1_13 STD (b) (b) SER_DC_BALANCE_reg_stdl 3 0 0 2 FB1_14 STD 27 I/O O SER_DESKEW_B_reg_stdl 3 0 0 2 FB1_15 STD 28 I/O O DRV_CRATE_TO_SCLD_reg_stdlv(1) 3 0 0 2 FB1_16 STD 35 I/O O LED_STRETCHER_CB16CE/Q(2) 3 0 0 2 FB1_17 STD 30 GCK/I/O GCK/I LED_STRETCHER_CB16CE/Q(1) 3 0 0 2 FB1_18 STD (b) (b) Signals Used by Logic in Function Block 1: ADC_ENABLE_reg_stdl 16: LED_STRETCHER_CB16CE/Q(8) 30: OCB_DATA_inout_stdlv(4).PIN 2: BOARD_CONTROL_1_DATA_int_stdlv(6) 17: LED_STRETCHER_CB16CE/Q(9) 31: OCB_DATA_inout_stdlv(5).PIN 3: DRV_CRATE_TO_SCLD_reg_stdlv(0) 18: LED_STRETCHER_CB16CE/Q__n0000(10)/LED_STRETCHER_CB16CE/Q__n0000(10)_D 32: OCB_DATA_inout_stdlv(7).PIN 4: DRV_CRATE_TO_SCLD_reg_stdlv(1) 19: LED_STRETCHER_CB16CE/Q__n0000(11)/LED_STRETCHER_CB16CE/Q__n0000(11)_D 33: PAL_ACCESS_inout_stdlv(10) 5: LED_STRETCHER_CB16CE/Q(1) 20: LED_STRETCHER_CB16CE/Q__n0000(12)/LED_STRETCHER_CB16CE/Q__n0000(12)_D 34: PAL_ACCESS_inout_stdlv(13) 6: LED_STRETCHER_CB16CE/Q(10) 21: LED_STRETCHER_CB16CE/Q__n0000(9)/LED_STRETCHER_CB16CE/Q__n0000(9)_D 35: PAL_ACCESS_inout_stdlv(8) 7: LED_STRETCHER_CB16CE/Q(11) 22: LED_STRETCHER_CE_int_stdl/LED_STRETCHER_CE_int_stdl_D2 36: OCB_DATA_inout_stdlv(0).PIN 8: LED_STRETCHER_CB16CE/Q(12) 23: N1861/N1861_D2 37: PAL_BX_CLOCK_in_stdl 9: LED_STRETCHER_CB16CE/Q(13) 24: N1871/N1871_D2 38: SER_DC_BALANCE_reg_stdl 10: LED_STRETCHER_CB16CE/Q(2) 25: OCB_ADRS_in_stdlv(1) 39: SER_DESKEW_B_reg_stdl 11: LED_STRETCHER_CB16CE/Q(3) 26: OCB_ADRS_in_stdlv(2) 40: SYSRESET_TMP_1_int_stdl 12: LED_STRETCHER_CB16CE/Q(4) 27: OCB_ADRS_in_stdlv(3) 41: SYSRESET_TMP_2_int_stdl 13: LED_STRETCHER_CB16CE/Q(5) 28: OCB_ADRS_in_stdlv(4) 42: SYSRESET_TMP_3_int_stdl 14: LED_STRETCHER_CB16CE/Q(6) 29: OCB_DATA_inout_stdlv(1).PIN 43: VME_SYSRESET_B_in_stdl 15: LED_STRETCHER_CB16CE/Q(7) Signal 1 2 3 4 5 Signals FB Name 0----+----0----+----0----+----0----+----0----+----0 Used Inputs _n0114/_n0114_D2 ..X.....................XXXX......X............... 6 6 LED_STRETCHER_CB16CE/Q__n0000(9)/LED_STRETCHER_CB16CE/Q__n0000(9)_D .....XXXX..XXXXXX................................. 10 10 LED_STRETCHER_CB16CE/Q__n0000(8)/LED_STRETCHER_CB16CE/Q__n0000(8)_D .....XXXX...XXXXX................................. 9 9 PAL_ACCESS_inout_stdlv(0) .X..................................X............. 2 2 LED_STRETCHER_CB16CE/Q__n0000(10)/LED_STRETCHER_CB16CE/Q__n0000(10)_D .....XXXX.XXXXXXX................................. 11 11 LED_STRETCHER_CB16CE/Q(9) .....XXXX............X.................XXXX....... 9 9 LED_STRETCHER_CB16CE/Q(12) ........X............X.................XXXX....... 6 6 LED_STRETCHER_CB16CE/Q(11) .......XX............X.................XXXX....... 7 7 LED_STRETCHER_CB16CE/Q(10) ......XXX............X.................XXXX....... 8 8 DRV_CRATE_TO_SCLD_reg_stdlv(0) ..X....................XXXXX.X..XXX....XXXX....... 14 14 LED_STRETCHER_CB16CE/Q(4) ...........X........XX.................XXXX....... 7 7 ADC_ENABLE_reg_stdl X.....................X.XXXX...XXXX....XXXX....... 14 14 LED_STRETCHER_CB16CE/Q(3) ..........X......X...X.................XXXX....... 7 7 SER_DC_BALANCE_reg_stdl ......................X.XXXXX...XXX..X.XXXX....... 14 14 SER_DESKEW_B_reg_stdl ......................X.XXXX....XXXX..XXXXX....... 14 14 DRV_CRATE_TO_SCLD_reg_stdlv(1) ...X...................XXXXX..X.XXX....XXXX....... 14 14 LED_STRETCHER_CB16CE/Q(2) .........X........X..X.................XXXX....... 7 7 LED_STRETCHER_CB16CE/Q(1) ....X..............X.X.................XXXX....... 7 7 0----+----1----+----2----+----3----+----4----+----5 0 0 0 0 0 Legend: Total Pt - Total product terms used by the macrocell signal Imp Pt - Product terms imported from other macrocells Exp Pt - Product terms exported to other macrocells in direction shown Unused Pt - Unused local product terms remaining in macrocell Loc - Location where logic was mapped in device Pwr Mode - Macrocell power mode Pin Type/Use - I - Input GCK - Global Clock O - Output GTS - Global Output Enable (b) - Buried macrocell GSR - Global Set/Reset X(@) - Signal used as input (wire-AND input) to the macrocell logic. The number of Signals Used may exceed the number of FB Inputs Used due to wire-ANDing in the switch matrix. *********************************** FB2 *********************************** Number of function block inputs used/remaining: 40/14 Number of signals used by logic mapping into function block: 40 Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin Name Pt Pt Pt Pt Mode # Type Use CNFG_PROG_B_out_stdlv(1) 2 0 0 3 FB2_1 STD 142 I/O O _n0115/_n0115_D2 1 0 0 4 FB2_2 STD 143 GSR/I/O I _n0109/_n0109_D2 1 0 0 4 FB2_3 STD (b) (b) N1881/N1881_D2 1 0 0 4 FB2_4 STD 4 I/O I CNFG_CS_B_reg_stdlv(1) 3 0 0 2 FB2_5 STD 2 GTS/I/O O N1871/N1871_D2 1 0 0 4 FB2_6 STD 3 GTS/I/O I N1861/N1861_D2 1 0 0 4 FB2_7 STD (b) (b) DATA_BUF_DIR_out_stdl 2 0 0 3 FB2_8 STD 5 GTS/I/O O OCB_DIRECTION_out_stdl 5 0 0 0 FB2_9 STD 6 GTS/I/O O LED_STRETCHER_CB16CE/Q(8) 2 0 0 3 FB2_10 STD 7 I/O I CNFG_CCLK_out_stdl 2 0 0 3 FB2_11 STD 9 I/O O CNFG_RDWR_B_reg_stdl 3 0 0 2 FB2_12 STD 10 I/O O CNFG_CS_B_reg_stdlv(0) 3 0 0 2 FB2_13 STD 12 I/O O CNFG_PROG_B_out_stdlv(0) 2 0 0 3 FB2_14 STD 11 I/O O CNFG_PROG_B_REQ_reg_stdlv(1) 3 0 0 2 FB2_15 STD 13 I/O I CNFG_PROG_B_REQ_reg_stdlv(0) 3 0 0 2 FB2_16 STD 14 I/O I BOARD_CONTROL_1_DATA_int_stdlv(5) 3 0 0 2 FB2_17 STD 15 I/O I BOARD_CONTROL_1_DATA_int_stdlv(4) 3 0 0 2 FB2_18 STD (b) (b) Signals Used by Logic in Function Block 1: BOARD_CONTROL_1_DATA_int_stdlv(4) 15: LED_STRETCHER_CE_int_stdl/LED_STRETCHER_CE_int_stdl_D2 28: OCB_DATA_inout_stdlv(4).PIN 2: BOARD_CONTROL_1_DATA_int_stdlv(5) 16: LTCHD_WRITE_B_in_stdl 29: OCB_DATA_inout_stdlv(5).PIN 3: CNFG_CS_B_reg_stdlv(0) 17: N1861/N1861_D2 30: PAL_ACCESS_inout_stdlv(10) 4: CNFG_CS_B_reg_stdlv(1) 18: N1881/N1881_D2 31: PAL_ACCESS_inout_stdlv(13) 5: CNFG_PROG_B_REQ_reg_stdlv(0) 19: NEXT_STATE_QUIESCENT_B_int_stdl 32: PAL_ACCESS_inout_stdlv(3) 6: CNFG_PROG_B_REQ_reg_stdlv(1) 20: NEXT_STATE_QUIESCENT_int_stdl 33: PAL_ACCESS_inout_stdlv(8) 7: CNFG_RDWR_B_reg_stdl 21: OCB_ADRS_in_stdlv(1) 34: OCB_DATA_inout_stdlv(0).PIN 8: LATCH_1_STATE_int_stdl 22: OCB_ADRS_in_stdlv(2) 35: SET_QUIESCENT_STATE_int_stdl 9: LATCH_2_STATE_int_stdl 23: OCB_ADRS_in_stdlv(3) 36: SYSRESET_TMP_1_int_stdl 10: LED_STRETCHER_CB16CE/Q(10) 24: OCB_ADRS_in_stdlv(4) 37: SYSRESET_TMP_2_int_stdl 11: LED_STRETCHER_CB16CE/Q(11) 25: OCB_DATA_inout_stdlv(1).PIN 38: SYSRESET_TMP_3_int_stdl 12: LED_STRETCHER_CB16CE/Q(12) 26: OCB_DATA_inout_stdlv(2).PIN 39: VALID_CYCLE_B_int_stdl 13: LED_STRETCHER_CB16CE/Q(13) 27: OCB_DATA_inout_stdlv(3).PIN 40: VME_SYSRESET_B_in_stdl 14: LED_STRETCHER_CB16CE/Q(9) Signal 1 2 3 4 5 Signals FB Name 0----+----0----+----0----+----0----+----0----+----0 Used Inputs CNFG_PROG_B_out_stdlv(1) X....X.............................XXX.X.......... 6 6 _n0115/_n0115_D2 ......X.............XXXX........X................. 6 6 _n0109/_n0109_D2 ...X................XXXX........X................. 6 6 N1881/N1881_D2 ....................XXXX.....X..X................. 6 6 CNFG_CS_B_reg_stdlv(1) ...X.............X..XXXX..X..XX.X..XXX.X.......... 14 14 N1871/N1871_D2 ....................XXXX.....X..X................. 6 6 N1861/N1861_D2 ....................XXXX.....X..X................. 6 6 DATA_BUF_DIR_out_stdl .......X.......X...X..............XXXXXX.......... 9 9 OCB_DIRECTION_out_stdl .......XX......X...X...........X...XXXXX.......... 10 10 LED_STRETCHER_CB16CE/Q(8) .........XXXXXX....................XXX.X.......... 10 10 CNFG_CCLK_out_stdl X.......X......X..X.XXXX........X..XXX.X.......... 13 13 CNFG_RDWR_B_reg_stdl ......X..........X..XXXX...X.XX.X..XXX.X.......... 14 14 CNFG_CS_B_reg_stdlv(0) ..X..............X..XXXX.X...XX.X..XXX.X.......... 14 14 CNFG_PROG_B_out_stdlv(0) X...X..............................XXX.X.......... 6 6 CNFG_PROG_B_REQ_reg_stdlv(1) .....X...........X..XXXXX....XX.X..XXX.X.......... 14 14 CNFG_PROG_B_REQ_reg_stdlv(0) ....X............X..XXXX.....XX.XX.XXX.X.......... 14 14 BOARD_CONTROL_1_DATA_int_stdlv(5) .X..............X...XXXX....XXX.X..XXX.X.......... 14 14 BOARD_CONTROL_1_DATA_int_stdlv(4) X...............X...XXXX...X.XX.X..XXX.X.......... 14 14 0----+----1----+----2----+----3----+----4----+----5 0 0 0 0 0 Legend: Total Pt - Total product terms used by the macrocell signal Imp Pt - Product terms imported from other macrocells Exp Pt - Product terms exported to other macrocells in direction shown Unused Pt - Unused local product terms remaining in macrocell Loc - Location where logic was mapped in device Pwr Mode - Macrocell power mode Pin Type/Use - I - Input GCK - Global Clock O - Output GTS - Global Output Enable (b) - Buried macrocell GSR - Global Set/Reset X(@) - Signal used as input (wire-AND input) to the macrocell logic. The number of Signals Used may exceed the number of FB Inputs Used due to wire-ANDing in the switch matrix. *********************************** FB3 *********************************** Number of function block inputs used/remaining: 52/2 Number of signals used by logic mapping into function block: 52 Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin Name Pt Pt Pt Pt Mode # Type Use LOOP_FILTER_REF_inout_stdl 1 0 0 4 FB3_1 STD 39 I/O O RCVD_BX_CLOCK_inout_stdl 1 0 0 4 FB3_2 STD 32 GCK/I/O O PAL_ACCESS_inout_stdlv(1) 2 0 \/2 1 FB3_3 STD 41 I/O O PAL_ACCESS_inout_stdlv(3) 9 4<- 0 0 FB3_4 STD 44 I/O O CNT_BIT_VAL_4_inout_stdl 3 0 /\2 0 FB3_5 STD 33 I/O O PAL_FIRST_X8_EDGE_out_stdl 2 0 0 3 FB3_6 STD 34 I/O O PAL_ACCESS_inout_stdlv(5) 3 0 0 2 FB3_7 STD 46 I/O O (unused) 0 0 0 5 FB3_8 38 GCK/I/O GCK PHASE_DET_OUT_out_stdl 2 0 0 3 FB3_9 STD 40 I/O O PAL_ACCESS_inout_stdlv(6) 3 0 0 2 FB3_10 STD 48 I/O O PAL_ACCESS_inout_stdlv(2) 4 0 0 1 FB3_11 STD 43 I/O O PAL_ACCESS_inout_stdlv(4) 3 0 0 2 FB3_12 STD 45 I/O O (unused) 0 0 \/1 4 FB3_13 (b) (b) PAL_ACCESS_inout_stdlv(7) 6 1<- 0 0 FB3_14 STD 49 I/O O PAL_ACCESS_inout_stdlv(8) 2 0 0 3 FB3_15 STD 50 I/O O (unused) 0 0 0 5 FB3_16 (b) PAL_ACCESS_inout_stdlv(9) 3 0 0 2 FB3_17 STD 51 I/O O (unused) 0 0 0 5 FB3_18 (b) Signals Used by Logic in Function Block 1: BOARD_CONTROL_1_DATA_int_stdlv(6) 19: NEXT_STATE_QUIESCENT_B_int_stdl 36: OCB_ADRS_in_stdlv(8) 2: CNT_BIT_VAL_1_int_stdl 20: NEXT_STATE_QUIESCENT_int_stdl 37: OCB_ADRS_in_stdlv(9) 3: CNT_BIT_VAL_2_int_stdl 21: OCB_ADRS_in_stdlv(10) 38: PAL_ACCESS_inout_stdlv(1) 4: CNT_BIT_VAL_4_inout_stdl 22: OCB_ADRS_in_stdlv(11) 39: PAL_ACCESS_inout_stdlv(3) 5: DS1_tmp_int_stdl 23: OCB_ADRS_in_stdlv(12) 40: PAL_ACCESS_inout_stdlv(8) 6: IDLE_STATE_int_stdl 24: OCB_ADRS_in_stdlv(13) 41: RCVD_BX_CLOCK_inout_stdl 7: IO_1_STATE_int_stdl 25: OCB_ADRS_in_stdlv(14) 42: SET_QUIESCENT_STATE_int_stdl 8: IO_2_STATE_int_stdl 26: OCB_ADRS_in_stdlv(15) 43: SYSRESET_TMP_1_int_stdl 9: LATCH_1_STATE_int_stdl 27: OCB_ADRS_in_stdlv(16) 44: SYSRESET_TMP_2_int_stdl 10: LATCH_2_STATE_int_stdl 28: OCB_ADRS_in_stdlv(17) 45: SYSRESET_TMP_3_int_stdl 11: LOOP_FILTER_REF_inout_stdl 29: OCB_ADRS_in_stdlv(18) 46: VALID_CYCLE_B_int_stdl 12: LTCHD_AM_in_stdlv(0) 30: OCB_ADRS_in_stdlv(19) 47: VME_GEO_B_in_stdlv(0) 13: LTCHD_AM_in_stdlv(1) 31: OCB_ADRS_in_stdlv(20) 48: VME_GEO_B_in_stdlv(1) 14: LTCHD_AM_in_stdlv(3) 32: OCB_ADRS_in_stdlv(23) 49: VME_GEO_B_in_stdlv(2) 15: LTCHD_AM_in_stdlv(4) 33: OCB_ADRS_in_stdlv(5) 50: VME_SYSRESET_B_in_stdl 16: LTCHD_AM_in_stdlv(5) 34: OCB_ADRS_in_stdlv(6) 51: _n0142/_n0142_D 17: LTCHD_IACK_B_in_stdl 35: OCB_ADRS_in_stdlv(7) 52: _n0145/_n0145_D 18: LTCHD_WRITE_B_in_stdl Signal 1 2 3 4 5 6 Signals FB Name 0----+----0----+----0----+----0----+----0----+----0----+----0 Used Inputs LOOP_FILTER_REF_inout_stdl ..........................................XXX....X.......... 4 4 RCVD_BX_CLOCK_inout_stdl ..........................................XXX....X.......... 4 4 PAL_ACCESS_inout_stdlv(1) X...X....................................................... 2 2 PAL_ACCESS_inout_stdlv(3) X..........XXXXXX...........XXXX..............XXX.XX........ 16 16 CNT_BIT_VAL_4_inout_stdl .XXX......................................XXX....X.......... 7 7 PAL_FIRST_X8_EDGE_out_stdl .XXX......................................XXX....X.......... 7 7 PAL_ACCESS_inout_stdlv(5) X.......X..........X.....................XXXXX...X.......... 9 9 PHASE_DET_OUT_out_stdl ..........X.............................X................... 2 2 PAL_ACCESS_inout_stdlv(6) X.......X........X.X.....................XXXXX...X.......... 10 10 PAL_ACCESS_inout_stdlv(2) X.....XX..........X..................XX...XXX....X.......... 10 10 PAL_ACCESS_inout_stdlv(4) X....X...............................X....XXX....X.......... 7 7 PAL_ACCESS_inout_stdlv(7) X.......XX.......X.X..................X...XXXX...X.......... 11 11 PAL_ACCESS_inout_stdlv(8) X...................XXXXXXXX....XXXXX.X..................... 15 15 PAL_ACCESS_inout_stdlv(9) X................XX....................X..XXX....X.......... 8 8 0----+----1----+----2----+----3----+----4----+----5----+----6 0 0 0 0 0 0 Legend: Total Pt - Total product terms used by the macrocell signal Imp Pt - Product terms imported from other macrocells Exp Pt - Product terms exported to other macrocells in direction shown Unused Pt - Unused local product terms remaining in macrocell Loc - Location where logic was mapped in device Pwr Mode - Macrocell power mode Pin Type/Use - I - Input GCK - Global Clock O - Output GTS - Global Output Enable (b) - Buried macrocell GSR - Global Set/Reset X(@) - Signal used as input (wire-AND input) to the macrocell logic. The number of Signals Used may exceed the number of FB Inputs Used due to wire-ANDing in the switch matrix. *********************************** FB4 *********************************** Number of function block inputs used/remaining: 43/11 Number of signals used by logic mapping into function block: 43 Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin Name Pt Pt Pt Pt Mode # Type Use (unused) 0 0 0 5 FB4_1 118 I/O I (unused) 0 0 0 5 FB4_2 126 I/O I (unused) 0 0 0 5 FB4_3 133 I/O I (unused) 0 0 0 5 FB4_4 (b) DRV_PAL_LED_out_stdlv(1) 2 0 0 3 FB4_5 STD 128 I/O O VALID_CYCLE_B_int_stdl 1 0 0 4 FB4_6 STD 129 I/O I OCB_CHIP_SEL_B_int_stdlv(1) 1 0 0 4 FB4_7 STD (b) (b) OCB_CHIP_SEL_B_int_stdlv(0) 1 0 0 4 FB4_8 STD 130 I/O I NEXT_STATE_QUIESCENT_B_int_stdl 1 0 0 4 FB4_9 STD 131 I/O I DAC_SERIAL_DATA_CLOCK_out_stdl 2 0 0 3 FB4_10 STD 135 I/O O LED_STRETCHER_CB16CE/Q__n0000(7)/LED_STRETCHER_CB16CE/Q__n0000(7)_D 2 0 0 3 FB4_11 STD 132 I/O I DATA_TO_FIRST_DAC_INPUT_out_stdl 2 0 0 3 FB4_12 STD 134 I/O O OCB_CHIP_SEL_int_stdlv(1) 3 0 0 2 FB4_13 STD 137 I/O I DAC_CHIP_SELECT_B_out_stdl 2 0 0 3 FB4_14 STD 136 I/O O OCB_CHIP_SEL_B_out_stdlv(1) 2 0 0 3 FB4_15 STD 138 I/O O OCB_CHIP_SEL_B_out_stdlv(0) 2 0 0 3 FB4_16 STD 139 I/O O OCB_WRITE_STRB_B_inout_stdl 4 0 0 1 FB4_17 STD 140 I/O O OCB_CHIP_SEL_int_stdlv(0) 3 0 0 2 FB4_18 STD (b) (b) Signals Used by Logic in Function Block 1: BOARD_CONTROL_1_DATA_int_stdlv(3) 16: OCB_ADRS_in_stdlv(10) 30: OCB_ADRS_in_stdlv(7) 2: BOARD_CONTROL_1_DATA_int_stdlv(5) 17: OCB_ADRS_in_stdlv(11) 31: OCB_ADRS_in_stdlv(8) 3: BOARD_CONTROL_2_DATA_int_stdlv(6) 18: OCB_ADRS_in_stdlv(12) 32: OCB_ADRS_in_stdlv(9) 4: LATCH_2_STATE_int_stdl 19: OCB_ADRS_in_stdlv(13) 33: OCB_CHIP_SEL_B_int_stdlv(0) 5: LED_STRETCHER_CB16CE/Q(10) 20: OCB_ADRS_in_stdlv(14) 34: OCB_CHIP_SEL_B_int_stdlv(1) 6: LED_STRETCHER_CB16CE/Q(11) 21: OCB_ADRS_in_stdlv(15) 35: OCB_CHIP_SEL_int_stdlv(0) 7: LED_STRETCHER_CB16CE/Q(12) 22: OCB_ADRS_in_stdlv(16) 36: OCB_CHIP_SEL_int_stdlv(1) 8: LED_STRETCHER_CB16CE/Q(13) 23: OCB_ADRS_in_stdlv(17) 37: PAL_ACCESS_inout_stdlv(3) 9: LED_STRETCHER_CB16CE/Q(6) 24: OCB_ADRS_in_stdlv(1) 38: PAL_ACCESS_inout_stdlv(8) 10: LED_STRETCHER_CB16CE/Q(7) 25: OCB_ADRS_in_stdlv(2) 39: OCB_DATA_inout_stdlv(0).PIN 11: LED_STRETCHER_CB16CE/Q(8) 26: OCB_ADRS_in_stdlv(3) 40: SYSRESET_TMP_1_int_stdl 12: LED_STRETCHER_CB16CE/Q(9) 27: OCB_ADRS_in_stdlv(4) 41: SYSRESET_TMP_2_int_stdl 13: LTCHD_WRITE_B_in_stdl 28: OCB_ADRS_in_stdlv(5) 42: SYSRESET_TMP_3_int_stdl 14: NEXT_STATE_QUIESCENT_B_int_stdl 29: OCB_ADRS_in_stdlv(6) 43: VME_SYSRESET_B_in_stdl 15: NEXT_STATE_QUIESCENT_int_stdl Signal 1 2 3 4 5 Signals FB Name 0----+----0----+----0----+----0----+----0----+----0 Used Inputs DRV_PAL_LED_out_stdlv(1) X......................................XXXX....... 5 5 VALID_CYCLE_B_int_stdl ....................................X............. 1 1 OCB_CHIP_SEL_B_int_stdlv(1) ...................................X.............. 1 1 OCB_CHIP_SEL_B_int_stdlv(0) ..................................X............... 1 1 NEXT_STATE_QUIESCENT_B_int_stdl ..............X................................... 1 1 DAC_SERIAL_DATA_CLOCK_out_stdl .X.X........X.X........XXXX..........X.XXXX....... 13 13 LED_STRETCHER_CB16CE/Q__n0000(7)/LED_STRETCHER_CB16CE/Q__n0000(7)_D ....XXXXXXXX...................................... 8 8 DATA_TO_FIRST_DAC_INPUT_out_stdl .X...........X.........XXXX..........XXXXXX....... 12 12 OCB_CHIP_SEL_int_stdlv(1) ...............XXXXXXXX....XXXXX....X............. 14 14 DAC_CHIP_SELECT_B_out_stdl .XX....................................XXXX....... 6 6 OCB_CHIP_SEL_B_out_stdlv(1) ..............X..................X.....XXXX....... 6 6 OCB_CHIP_SEL_B_out_stdlv(0) ..............X.................X......XXXX....... 6 6 OCB_WRITE_STRB_B_inout_stdl ...X........X.X...................XX.X.XXXX....... 10 10 OCB_CHIP_SEL_int_stdlv(0) ...............XXXXXXXX....XXXXX....X............. 14 14 0----+----1----+----2----+----3----+----4----+----5 0 0 0 0 0 Legend: Total Pt - Total product terms used by the macrocell signal Imp Pt - Product terms imported from other macrocells Exp Pt - Product terms exported to other macrocells in direction shown Unused Pt - Unused local product terms remaining in macrocell Loc - Location where logic was mapped in device Pwr Mode - Macrocell power mode Pin Type/Use - I - Input GCK - Global Clock O - Output GTS - Global Output Enable (b) - Buried macrocell GSR - Global Set/Reset X(@) - Signal used as input (wire-AND input) to the macrocell logic. The number of Signals Used may exceed the number of FB Inputs Used due to wire-ANDing in the switch matrix. *********************************** FB5 *********************************** Number of function block inputs used/remaining: 22/32 Number of signals used by logic mapping into function block: 22 Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin Name Pt Pt Pt Pt Mode # Type Use (unused) 0 0 0 5 FB5_1 (b) DATA_BUF_ENB_B_out_stdl 2 0 0 3 FB5_2 STD 52 I/O O (unused) 0 0 0 5 FB5_3 59 I/O I (unused) 0 0 0 5 FB5_4 (b) VME_LTCH_CLK_out_stdl 2 0 0 3 FB5_5 STD 53 I/O O DRV_DTACK_out_stdl 3 0 0 2 FB5_6 STD 54 I/O O (unused) 0 0 0 5 FB5_7 66 I/O I (unused) 0 0 0 5 FB5_8 56 I/O I PAL_ACCESS_inout_stdlv(10) 5 0 0 0 FB5_9 STD 57 I/O O (unused) 0 0 0 5 FB5_10 68 I/O I PAL_ACCESS_inout_stdlv(11) 2 0 0 3 FB5_11 STD 58 I/O O (unused) 0 0 0 5 FB5_12 60 I/O I (unused) 0 0 0 5 FB5_13 70 I/O I (unused) 0 0 0 5 FB5_14 61 I/O I (unused) 0 0 0 5 FB5_15 64 I/O I (unused) 0 0 0 5 FB5_16 (b) CNT_BIT_VAL_2_int_stdl 1 0 0 4 FB5_17 STD 69 I/O I CNT_BIT_VAL_1_int_stdl 0 0 0 5 FB5_18 STD (b) (b) Signals Used by Logic in Function Block 1: BOARD_CONTROL_1_DATA_int_stdlv(6) 9: NEXT_STATE_QUIESCENT_B_int_stdl 16: OCB_DATA_inout_stdlv(0).PIN 2: CNT_BIT_VAL_1_int_stdl 10: NEXT_STATE_QUIESCENT_int_stdl 17: SET_QUIESCENT_STATE_int_stdl 3: IDLE_STATE_int_stdl 11: OCB_CHIP_SEL_int_stdlv(0) 18: SYSRESET_TMP_1_int_stdl 4: IO_1_STATE_int_stdl 12: OCB_CHIP_SEL_int_stdlv(1) 19: SYSRESET_TMP_2_int_stdl 5: IO_2_STATE_int_stdl 13: PAL_ACCESS_inout_stdlv(1) 20: SYSRESET_TMP_3_int_stdl 6: LATCH_1_STATE_int_stdl 14: PAL_ACCESS_inout_stdlv(3) 21: VALID_CYCLE_B_int_stdl 7: LATCH_2_STATE_int_stdl 15: PAL_ACCESS_inout_stdlv(8) 22: VME_SYSRESET_B_in_stdl 8: LTCHD_WRITE_B_in_stdl Signal 1 2 3 4 Signals FB Name 0----+----0----+----0----+----0----+----0 Used Inputs DATA_BUF_ENB_B_out_stdl .....X...X......XXXXXX.................. 8 8 VME_LTCH_CLK_out_stdl ..X.........X....XXX.X.................. 6 6 DRV_DTACK_out_stdl ...XX...X...XX...XXX.X.................. 9 9 PAL_ACCESS_inout_stdlv(10) X.....XX.XXX..X..XXX.X.................. 11 11 PAL_ACCESS_inout_stdlv(11) X..............X........................ 2 2 CNT_BIT_VAL_2_int_stdl .X...................................... 1 1 CNT_BIT_VAL_1_int_stdl ........................................ 0 0 0----+----1----+----2----+----3----+----4 0 0 0 0 Legend: Total Pt - Total product terms used by the macrocell signal Imp Pt - Product terms imported from other macrocells Exp Pt - Product terms exported to other macrocells in direction shown Unused Pt - Unused local product terms remaining in macrocell Loc - Location where logic was mapped in device Pwr Mode - Macrocell power mode Pin Type/Use - I - Input GCK - Global Clock O - Output GTS - Global Output Enable (b) - Buried macrocell GSR - Global Set/Reset X(@) - Signal used as input (wire-AND input) to the macrocell logic. The number of Signals Used may exceed the number of FB Inputs Used due to wire-ANDing in the switch matrix. *********************************** FB6 *********************************** Number of function block inputs used/remaining: 43/11 Number of signals used by logic mapping into function block: 43 Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin Name Pt Pt Pt Pt Mode # Type Use LED_STRETCHER_CE_int_stdl/LED_STRETCHER_CE_int_stdl_D2 2 0 0 3 FB6_1 STD (b) (b) LED_STRETCHER_CB16CE/Q__n0000(12)/LED_STRETCHER_CB16CE/Q__n0000(12)_D 2 0 0 3 FB6_2 STD 106 I/O I LED_STRETCHER_CB16CE/Q__n0000(11)/LED_STRETCHER_CB16CE/Q__n0000(11)_D 2 0 0 3 FB6_3 STD (b) (b) PAL_ACCESS_inout_stdlv(13) 2 0 0 3 FB6_4 STD 111 I/O O PAL_ACCESS_inout_stdlv(12) 2 0 0 3 FB6_5 STD 110 I/O O PAL_ACCESS_inout_stdlv(14) 2 0 0 3 FB6_6 STD 112 I/O O LED_STRETCHER_CB16CE/Q(7) 2 0 0 3 FB6_7 STD (b) (b) PAL_ACCESS_inout_stdlv(15) 4 0 0 1 FB6_8 STD 113 I/O O DRV_PAL_LED_out_stdlv(0) 2 0 0 3 FB6_9 STD 116 I/O O PAL_ACCESS_inout_stdlv(16) 4 0 0 1 FB6_10 STD 115 I/O O DRV_CRATE_STATUS_reg_stdlv(1) 3 0 0 2 FB6_11 STD 119 I/O O DRV_CRATE_STATUS_reg_stdlv(2) 3 0 0 2 FB6_12 STD 120 I/O O LED_STRETCHER_CB16CE/Q(0) 3 0 0 2 FB6_13 STD (b) (b) DRV_CRATE_STATUS_reg_stdlv(3) 3 0 0 2 FB6_14 STD 121 I/O O BOARD_CONTROL_2_DATA_int_stdlv(6) 3 0 0 2 FB6_15 STD 124 I/O I DRV_CRATE_STATUS_reg_stdlv(0) 3 0 0 2 FB6_16 STD 117 I/O O BOARD_CONTROL_1_DATA_int_stdlv(6) 3 0 0 2 FB6_17 STD 125 I/O I BOARD_CONTROL_1_DATA_int_stdlv(3) 3 0 0 2 FB6_18 STD (b) (b) Signals Used by Logic in Function Block 1: BOARD_CONTROL_1_DATA_int_stdlv(3) 16: LED_STRETCHER_CB16CE/Q(5) 30: OCB_DATA_inout_stdlv(2).PIN 2: BOARD_CONTROL_1_DATA_int_stdlv(6) 17: LED_STRETCHER_CB16CE/Q(6) 31: OCB_DATA_inout_stdlv(3).PIN 3: BOARD_CONTROL_2_DATA_int_stdlv(6) 18: LED_STRETCHER_CB16CE/Q(7) 32: OCB_DATA_inout_stdlv(6).PIN 4: DRV_CRATE_STATUS_reg_stdlv(1) 19: LED_STRETCHER_CB16CE/Q(8) 33: PAL_ACCESS_inout_stdlv(10) 5: DRV_CRATE_STATUS_reg_stdlv(2) 20: LED_STRETCHER_CB16CE/Q(9) 34: PAL_ACCESS_inout_stdlv(13) 6: DRV_CRATE_STATUS_reg_stdlv(3) 21: LED_STRETCHER_CE_int_stdl/LED_STRETCHER_CE_int_stdl_D2 35: PAL_ACCESS_inout_stdlv(16) 7: LED_STRETCHER_CB16CE/Q(0) 22: LTCHD_WRITE_B_in_stdl 36: PAL_ACCESS_inout_stdlv(3) 8: LED_STRETCHER_CB16CE/Q(1) 23: N1861/N1861_D2 37: PAL_ACCESS_inout_stdlv(8) 9: LED_STRETCHER_CB16CE/Q(10) 24: N1871/N1871_D2 38: OCB_DATA_inout_stdlv(0).PIN 10: LED_STRETCHER_CB16CE/Q(11) 25: OCB_ADRS_in_stdlv(1) 39: SER_DESKEW_B_reg_stdl 11: LED_STRETCHER_CB16CE/Q(12) 26: OCB_ADRS_in_stdlv(2) 40: SYSRESET_TMP_1_int_stdl 12: LED_STRETCHER_CB16CE/Q(13) 27: OCB_ADRS_in_stdlv(3) 41: SYSRESET_TMP_2_int_stdl 13: LED_STRETCHER_CB16CE/Q(2) 28: OCB_ADRS_in_stdlv(4) 42: SYSRESET_TMP_3_int_stdl 14: LED_STRETCHER_CB16CE/Q(3) 29: OCB_DATA_inout_stdlv(1).PIN 43: VME_SYSRESET_B_in_stdl 15: LED_STRETCHER_CB16CE/Q(4) Signal 1 2 3 4 5 Signals FB Name 0----+----0----+----0----+----0----+----0----+----0 Used Inputs LED_STRETCHER_CE_int_stdl/LED_STRETCHER_CE_int_stdl_D2 ......XXXXXXXXXXXXXX...............X.............. 15 15 LED_STRETCHER_CB16CE/Q__n0000(12)/LED_STRETCHER_CB16CE/Q__n0000(12)_D .......XXXXXXXXXXXXX.............................. 13 13 LED_STRETCHER_CB16CE/Q__n0000(11)/LED_STRETCHER_CB16CE/Q__n0000(11)_D ........XXXXXXXXXXXX.............................. 12 12 PAL_ACCESS_inout_stdlv(13) .X...................X..............X............. 3 3 PAL_ACCESS_inout_stdlv(12) .X......................X......................... 2 2 PAL_ACCESS_inout_stdlv(14) .X......................XXXX........X............. 6 6 LED_STRETCHER_CB16CE/Q(7) ........XXXX......XXX..................XXXX....... 11 11 PAL_ACCESS_inout_stdlv(15) .X....................X.XXXX....XX..XXXXXXX....... 15 15 DRV_PAL_LED_out_stdlv(0) ......XXXXXXXXXXXXXX...................XXXX....... 18 18 PAL_ACCESS_inout_stdlv(16) .X.....................XXXXX....XXX.XX.XXXX....... 15 15 DRV_CRATE_STATUS_reg_stdlv(1) ...X...................XXXXXX...XX..X..XXXX....... 14 14 DRV_CRATE_STATUS_reg_stdlv(2) ....X..................XXXXX.X..XX..X..XXXX....... 14 14 LED_STRETCHER_CB16CE/Q(0) ......XXXXXXXXXXXXXX...............X...XXXX....... 19 19 DRV_CRATE_STATUS_reg_stdlv(3) .....X.................XXXXX..X.XX..X..XXXX....... 14 14 BOARD_CONTROL_2_DATA_int_stdlv(6) ..X....................XXXXX...XXX..X..XXXX....... 14 14 DRV_CRATE_STATUS_reg_stdlv(0) .......................XXXXX....XXX.XX.XXXX....... 14 14 BOARD_CONTROL_1_DATA_int_stdlv(6) .X....................X.XXXX...XXX..X..XXXX....... 14 14 BOARD_CONTROL_1_DATA_int_stdlv(3) X.....................X.XXXX..X.XX..X..XXXX....... 14 14 0----+----1----+----2----+----3----+----4----+----5 0 0 0 0 0 Legend: Total Pt - Total product terms used by the macrocell signal Imp Pt - Product terms imported from other macrocells Exp Pt - Product terms exported to other macrocells in direction shown Unused Pt - Unused local product terms remaining in macrocell Loc - Location where logic was mapped in device Pwr Mode - Macrocell power mode Pin Type/Use - I - Input GCK - Global Clock O - Output GTS - Global Output Enable (b) - Buried macrocell GSR - Global Set/Reset X(@) - Signal used as input (wire-AND input) to the macrocell logic. The number of Signals Used may exceed the number of FB Inputs Used due to wire-ANDing in the switch matrix. *********************************** FB7 *********************************** Number of function block inputs used/remaining: 43/11 Number of signals used by logic mapping into function block: 43 Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin Name Pt Pt Pt Pt Mode # Type Use _n0112/_n0112_D2 1 0 0 4 FB7_1 STD (b) (b) _n0111/_n0111_D2 1 0 0 4 FB7_2 STD 71 I/O I OCB_DATA_inout_stdlv(7) 4 0 0 1 FB7_3 STD 75 I/O I/O _n0110/_n0110_D2 1 0 0 4 FB7_4 STD (b) (b) _n0108/_n0108_D2 1 0 0 4 FB7_5 STD 74 I/O I _n0107/_n0107_D2 1 0 0 4 FB7_6 STD 76 I/O I OCB_DATA_inout_stdlv(6) 5 0 0 0 FB7_7 STD 77 I/O I/O _n0106/_n0106_D2 1 0 0 4 FB7_8 STD 78 I/O I _n0105/_n0105_D2 1 0 0 4 FB7_9 STD 80 I/O I _n0104/_n0104_D2 1 0 0 4 FB7_10 STD 79 I/O I DS1_tmp_int_stdl 1 0 0 4 FB7_11 STD 82 I/O I OCB_DATA_inout_stdlv(4) 3 0 0 2 FB7_12 STD 85 I/O I/O _n0145/_n0145_D 2 0 0 3 FB7_13 STD 81 I/O I _n0142/_n0142_D 2 0 0 3 FB7_14 STD 86 I/O I LED_STRETCHER_CB16CE/Q(13) 2 0 \/1 2 FB7_15 STD 87 I/O I OCB_DATA_inout_stdlv(5) 6 1<- 0 0 FB7_16 STD 83 I/O I/O LED_STRETCHER_CB16CE/Q(6) 3 0 0 2 FB7_17 STD 88 I/O I LED_STRETCHER_CB16CE/Q(5) 3 0 0 2 FB7_18 STD (b) (b) Signals Used by Logic in Function Block 1: ADC_ENABLE_reg_stdl 16: FPGA_1_STATUS_in_stdlv(3) 30: PAL_ACCESS_inout_stdlv(9) 2: BOARD_CONTROL_1_DATA_int_stdlv(3) 17: LAST_DAC_OUTPUT_DATA_in_stdl 31: RCVD_DS1_in_stdl 3: BOARD_CONTROL_1_DATA_int_stdlv(5) 18: LED_STRETCHER_CB16CE/Q(5) 32: SYSRESET_TMP_1_int_stdl 4: BOARD_CONTROL_1_DATA_int_stdlv(6) 19: LED_STRETCHER_CB16CE/Q(6) 33: SYSRESET_TMP_2_int_stdl 5: BOARD_CONTROL_2_DATA_int_stdlv(6) 20: LED_STRETCHER_CB16CE/Q__n0000(7)/LED_STRETCHER_CB16CE/Q__n0000(7)_D 34: SYSRESET_TMP_3_int_stdl 6: CNFG_BUSY_in_stdlv(1) 21: LED_STRETCHER_CB16CE/Q__n0000(8)/LED_STRETCHER_CB16CE/Q__n0000(8)_D 35: VME_GEO_B_in_stdlv(3) 7: CNFG_DONE_in_stdlv(0) 22: LED_STRETCHER_CE_int_stdl/LED_STRETCHER_CE_int_stdl_D2 36: VME_GEO_B_in_stdlv(4) 8: CNFG_DONE_in_stdlv(1) 23: OCB_ADRS_in_stdlv(1) 37: VME_SYSRESET_B_in_stdl 9: CRATE_STATUS_B_in_stdlv(3) 24: OCB_ADRS_in_stdlv(21) 38: _n0110/_n0110_D2 10: DRV_CRATE_STATUS_reg_stdlv(3) 25: OCB_ADRS_in_stdlv(22) 39: _n0111/_n0111_D2 11: DRV_CRATE_TO_SCLD_reg_stdlv(1) 26: OCB_ADRS_in_stdlv(2) 40: _n0112/_n0112_D2 12: FPGA_0_STATUS_in_stdlv(3) 27: OCB_ADRS_in_stdlv(3) 41: _n0113/_n0113_D2 13: FPGA_1_STATUS_in_stdlv(0) 28: OCB_ADRS_in_stdlv(4) 42: _n0114/_n0114_D2 14: FPGA_1_STATUS_in_stdlv(1) 29: PAL_ACCESS_inout_stdlv(8) 43: _n0115/_n0115_D2 15: FPGA_1_STATUS_in_stdlv(2) Signal 1 2 3 4 5 Signals FB Name 0----+----0----+----0----+----0----+----0----+----0 Used Inputs _n0112/_n0112_D2 ......X...............X..XXXX..................... 6 6 _n0111/_n0111_D2 ................X.....X..XXXX..................... 6 6 OCB_DATA_inout_stdlv(7) X..............X......X..XXXXX.XXX..X............. 12 12 _n0110/_n0110_D2 ............X.........X..XXXX..................... 6 6 _n0108/_n0108_D2 .........X............X..XXXX..................... 6 6 _n0107/_n0107_D2 .X....................X..XXXX..................... 6 6 OCB_DATA_inout_stdlv(6) ...XX.........X.......X..XXXXX.XXX..X............. 13 13 _n0106/_n0106_D2 .....X................X..XXXX..................... 6 6 _n0105/_n0105_D2 ........X.............X..XXXX..................... 6 6 _n0104/_n0104_D2 ...........X..........X..XXXX..................... 6 6 DS1_tmp_int_stdl ..............................X................... 1 1 OCB_DATA_inout_stdlv(4) .............................X.XXX..XXXXXXX....... 11 11 _n0145/_n0145_D ........................X..........X.............. 2 2 _n0142/_n0142_D .......................X..........X............... 2 2 LED_STRETCHER_CB16CE/Q(13) .....................X.........XXX..X............. 5 5 OCB_DATA_inout_stdlv(5) ..X....X..X..X........X..XXXXX.XXX..X............. 14 14 LED_STRETCHER_CB16CE/Q(6) ..................XX.X.........XXX..X............. 7 7 LED_STRETCHER_CB16CE/Q(5) .................X..XX.........XXX..X............. 7 7 0----+----1----+----2----+----3----+----4----+----5 0 0 0 0 0 Legend: Total Pt - Total product terms used by the macrocell signal Imp Pt - Product terms imported from other macrocells Exp Pt - Product terms exported to other macrocells in direction shown Unused Pt - Unused local product terms remaining in macrocell Loc - Location where logic was mapped in device Pwr Mode - Macrocell power mode Pin Type/Use - I - Input GCK - Global Clock O - Output GTS - Global Output Enable (b) - Buried macrocell GSR - Global Set/Reset X(@) - Signal used as input (wire-AND input) to the macrocell logic. The number of Signals Used may exceed the number of FB Inputs Used due to wire-ANDing in the switch matrix. *********************************** FB8 *********************************** Number of function block inputs used/remaining: 43/11 Number of signals used by logic mapping into function block: 43 Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin Name Pt Pt Pt Pt Mode # Type Use _n0113/_n0113_D2 1 0 /\2 2 FB8_1 STD (b) (b) (unused) 0 0 \/1 4 FB8_2 91 I/O I OCB_DATA_inout_stdlv(2) 7 2<- 0 0 FB8_3 STD 95 I/O I/O (unused) 0 0 /\1 4 FB8_4 97 I/O I (unused) 0 0 0 5 FB8_5 92 I/O I SYSRESET_TMP_3_int_stdl 1 0 0 4 FB8_6 STD 93 I/O I SYSRESET_TMP_2_int_stdl 1 0 0 4 FB8_7 STD (b) (b) OCB_DATA_inout_stdlv(3) 3 0 0 2 FB8_8 STD 94 I/O I/O SYSRESET_TMP_1_int_stdl 1 0 0 4 FB8_9 STD 96 I/O I SET_QUIESCENT_STATE_int_stdl 2 0 0 3 FB8_10 STD 101 I/O I LATCH_2_STATE_int_stdl 2 0 \/2 1 FB8_11 STD 98 I/O I OCB_DATA_inout_stdlv(1) 8 3<- 0 0 FB8_12 STD 100 I/O I/O LATCH_1_STATE_int_stdl 2 0 /\1 2 FB8_13 STD 103 I/O I IO_1_STATE_int_stdl 2 0 \/2 1 FB8_14 STD 102 I/O I IO_2_STATE_int_stdl 4 2<- \/3 0 FB8_15 STD 104 I/O I OCB_DATA_inout_stdlv(0) 8 3<- 0 0 FB8_16 STD 107 I/O I/O NEXT_STATE_QUIESCENT_int_stdl 6 1<- 0 0 FB8_17 STD 105 I/O I IDLE_STATE_int_stdl 6 2<- /\1 0 FB8_18 STD (b) (b) Signals Used by Logic in Function Block 1: BOARD_CONTROL_1_DATA_int_stdlv(4) 16: IDLE_STATE_int_stdl 30: SER_DC_BALANCE_reg_stdl 2: CNFG_BUSY_in_stdlv(0) 17: IO_1_STATE_int_stdl 31: SER_DESKEW_B_reg_stdl 3: CNFG_CS_B_reg_stdlv(0) 18: IO_2_STATE_int_stdl 32: SET_QUIESCENT_STATE_int_stdl 4: CNFG_INIT_B_in_stdlv(0) 19: LATCH_1_STATE_int_stdl 33: SYSRESET_TMP_1_int_stdl 5: CNFG_INIT_B_in_stdlv(1) 20: LATCH_2_STATE_int_stdl 34: SYSRESET_TMP_2_int_stdl 6: CNFG_PROG_B_REQ_reg_stdlv(0) 21: OCB_ADRS_in_stdlv(1) 35: SYSRESET_TMP_3_int_stdl 7: CNFG_PROG_B_REQ_reg_stdlv(1) 22: OCB_ADRS_in_stdlv(2) 36: VALID_CYCLE_B_int_stdl 8: CRATE_STATUS_B_in_stdlv(0) 23: OCB_ADRS_in_stdlv(3) 37: VME_SYSRESET_B_in_stdl 9: CRATE_STATUS_B_in_stdlv(1) 24: OCB_ADRS_in_stdlv(4) 38: _n0104/_n0104_D2 10: CRATE_STATUS_B_in_stdlv(2) 25: PAL_ACCESS_inout_stdlv(1) 39: _n0105/_n0105_D2 11: DRV_CRATE_STATUS_reg_stdlv(1) 26: PAL_ACCESS_inout_stdlv(16) 40: _n0106/_n0106_D2 12: DRV_CRATE_STATUS_reg_stdlv(2) 27: PAL_ACCESS_inout_stdlv(3) 41: _n0107/_n0107_D2 13: FPGA_0_STATUS_in_stdlv(0) 28: PAL_ACCESS_inout_stdlv(8) 42: _n0108/_n0108_D2 14: FPGA_0_STATUS_in_stdlv(1) 29: PAL_ACCESS_inout_stdlv(9) 43: _n0109/_n0109_D2 15: FPGA_0_STATUS_in_stdlv(2) Signal 1 2 3 4 5 Signals FB Name 0----+----0----+----0----+----0----+----0----+----0 Used Inputs _n0113/_n0113_D2 X...................XXXX...X...................... 6 6 OCB_DATA_inout_stdlv(2) .XX......X.X..X.....XXXX...XX...XXX.X............. 15 15 SYSRESET_TMP_3_int_stdl .................................X................ 1 1 SYSRESET_TMP_2_int_stdl ................................X................. 1 1 OCB_DATA_inout_stdlv(3) ............................X...XXX.XXXXXXX....... 11 11 SYSRESET_TMP_1_int_stdl ....................................X............. 1 1 SET_QUIESCENT_STATE_int_stdl ...............XXXXX....X......XXXX.X............. 11 11 LATCH_2_STATE_int_stdl ...............XXXXX....X......XXXX.X............. 11 11 OCB_DATA_inout_stdlv(1) ....X.X.X.X..X......XXXX...XXX..XXX.X............. 16 16 LATCH_1_STATE_int_stdl ...............XXXXX....X......XXXX.X............. 11 11 IO_1_STATE_int_stdl ...............XXXXX....X.X....XXXX.X............. 12 12 IO_2_STATE_int_stdl ...............XXXXX....X.X....XXXXXX............. 13 13 OCB_DATA_inout_stdlv(0) ...X.X.X....X.......XXXX.X.XX.X.XXX.X............. 16 16 NEXT_STATE_QUIESCENT_int_stdl ...............X.X.X....X.X....XXXXXX............. 11 11 IDLE_STATE_int_stdl ...............XXXXX....X......XXXXXX............. 12 12 0----+----1----+----2----+----3----+----4----+----5 0 0 0 0 0 Legend: Total Pt - Total product terms used by the macrocell signal Imp Pt - Product terms imported from other macrocells Exp Pt - Product terms exported to other macrocells in direction shown Unused Pt - Unused local product terms remaining in macrocell Loc - Location where logic was mapped in device Pwr Mode - Macrocell power mode Pin Type/Use - I - Input GCK - Global Clock O - Output GTS - Global Output Enable (b) - Buried macrocell GSR - Global Set/Reset X(@) - Signal used as input (wire-AND input) to the macrocell logic. The number of Signals Used may exceed the number of FB Inputs Used due to wire-ANDing in the switch matrix. ;;-----------------------------------------------------------------;; ; Implemented Equations. FDCPE_ADC_ENABLE_reg_stdl: FDCPE port map (ADC_ENABLE_reg_stdl,ADC_ENABLE_reg_stdl_D,PAL_BX_CLOCK_in_stdl,ADC_ENABLE_reg_stdl_CLR,'0'); ADC_ENABLE_reg_stdl_D <= ((ADC_ENABLE_reg_stdl AND NOT N1861/N1861_D2) OR (PAL_ACCESS_inout_stdlv(8) AND NOT PAL_ACCESS_inout_stdlv(10) AND PAL_ACCESS_inout_stdlv(13) AND NOT OCB_ADRS_in_stdlv(1) AND NOT OCB_ADRS_in_stdlv(4) AND NOT OCB_ADRS_in_stdlv(2) AND OCB_DATA_inout_stdlv(7).PIN AND NOT OCB_ADRS_in_stdlv(3))); ADC_ENABLE_reg_stdl_CLR <= (NOT VME_SYSRESET_B_in_stdl AND NOT SYSRESET_TMP_1_int_stdl AND NOT SYSRESET_TMP_2_int_stdl AND NOT SYSRESET_TMP_3_int_stdl); FDCPE_BOARD_CONTROL_1_DATA_int_stdlv3: FDCPE port map (BOARD_CONTROL_1_DATA_int_stdlv(3),BOARD_CONTROL_1_DATA_int_stdlv_D(3),PAL_BX_CLOCK_in_stdl,'0',BOARD_CONTROL_1_DATA_int_stdlv_PRE(3)); BOARD_CONTROL_1_DATA_int_stdlv_D(3) <= ((BOARD_CONTROL_1_DATA_int_stdlv(3) AND NOT N1861/N1861_D2) OR (PAL_ACCESS_inout_stdlv(8) AND NOT PAL_ACCESS_inout_stdlv(10) AND PAL_ACCESS_inout_stdlv(13) AND NOT OCB_ADRS_in_stdlv(1) AND NOT OCB_ADRS_in_stdlv(4) AND NOT OCB_ADRS_in_stdlv(2) AND OCB_DATA_inout_stdlv(3).PIN AND NOT OCB_ADRS_in_stdlv(3))); BOARD_CONTROL_1_DATA_int_stdlv_PRE(3) <= (NOT VME_SYSRESET_B_in_stdl AND NOT SYSRESET_TMP_1_int_stdl AND NOT SYSRESET_TMP_2_int_stdl AND NOT SYSRESET_TMP_3_int_stdl); FDCPE_BOARD_CONTROL_1_DATA_int_stdlv4: FDCPE port map (BOARD_CONTROL_1_DATA_int_stdlv(4),BOARD_CONTROL_1_DATA_int_stdlv_D(4),PAL_BX_CLOCK_in_stdl,BOARD_CONTROL_1_DATA_int_stdlv_CLR(4),'0'); BOARD_CONTROL_1_DATA_int_stdlv_D(4) <= ((BOARD_CONTROL_1_DATA_int_stdlv(4) AND NOT N1861/N1861_D2) OR (PAL_ACCESS_inout_stdlv(8) AND NOT PAL_ACCESS_inout_stdlv(10) AND PAL_ACCESS_inout_stdlv(13) AND NOT OCB_ADRS_in_stdlv(1) AND NOT OCB_ADRS_in_stdlv(4) AND NOT OCB_ADRS_in_stdlv(2) AND OCB_DATA_inout_stdlv(4).PIN AND NOT OCB_ADRS_in_stdlv(3))); BOARD_CONTROL_1_DATA_int_stdlv_CLR(4) <= (NOT VME_SYSRESET_B_in_stdl AND NOT SYSRESET_TMP_1_int_stdl AND NOT SYSRESET_TMP_2_int_stdl AND NOT SYSRESET_TMP_3_int_stdl); FDCPE_BOARD_CONTROL_1_DATA_int_stdlv5: FDCPE port map (BOARD_CONTROL_1_DATA_int_stdlv(5),BOARD_CONTROL_1_DATA_int_stdlv_D(5),PAL_BX_CLOCK_in_stdl,BOARD_CONTROL_1_DATA_int_stdlv_CLR(5),'0'); BOARD_CONTROL_1_DATA_int_stdlv_D(5) <= ((BOARD_CONTROL_1_DATA_int_stdlv(5) AND NOT N1861/N1861_D2) OR (PAL_ACCESS_inout_stdlv(8) AND NOT PAL_ACCESS_inout_stdlv(10) AND PAL_ACCESS_inout_stdlv(13) AND NOT OCB_ADRS_in_stdlv(1) AND NOT OCB_ADRS_in_stdlv(4) AND NOT OCB_ADRS_in_stdlv(2) AND OCB_DATA_inout_stdlv(5).PIN AND NOT OCB_ADRS_in_stdlv(3))); BOARD_CONTROL_1_DATA_int_stdlv_CLR(5) <= (NOT VME_SYSRESET_B_in_stdl AND NOT SYSRESET_TMP_1_int_stdl AND NOT SYSRESET_TMP_2_int_stdl AND NOT SYSRESET_TMP_3_int_stdl); FDCPE_BOARD_CONTROL_1_DATA_int_stdlv6: FDCPE port map (BOARD_CONTROL_1_DATA_int_stdlv(6),BOARD_CONTROL_1_DATA_int_stdlv_D(6),PAL_BX_CLOCK_in_stdl,BOARD_CONTROL_1_DATA_int_stdlv_CLR(6),'0'); BOARD_CONTROL_1_DATA_int_stdlv_D(6) <= ((BOARD_CONTROL_1_DATA_int_stdlv(6) AND NOT N1861/N1861_D2) OR (PAL_ACCESS_inout_stdlv(8) AND NOT PAL_ACCESS_inout_stdlv(10) AND PAL_ACCESS_inout_stdlv(13) AND NOT OCB_ADRS_in_stdlv(1) AND NOT OCB_ADRS_in_stdlv(4) AND NOT OCB_ADRS_in_stdlv(2) AND OCB_DATA_inout_stdlv(6).PIN AND NOT OCB_ADRS_in_stdlv(3))); BOARD_CONTROL_1_DATA_int_stdlv_CLR(6) <= (NOT VME_SYSRESET_B_in_stdl AND NOT SYSRESET_TMP_1_int_stdl AND NOT SYSRESET_TMP_2_int_stdl AND NOT SYSRESET_TMP_3_int_stdl); FDCPE_BOARD_CONTROL_2_DATA_int_stdlv6: FDCPE port map (BOARD_CONTROL_2_DATA_int_stdlv(6),BOARD_CONTROL_2_DATA_int_stdlv_D(6),PAL_BX_CLOCK_in_stdl,'0',BOARD_CONTROL_2_DATA_int_stdlv_PRE(6)); BOARD_CONTROL_2_DATA_int_stdlv_D(6) <= ((BOARD_CONTROL_2_DATA_int_stdlv(6) AND NOT N1871/N1871_D2) OR (PAL_ACCESS_inout_stdlv(8) AND NOT PAL_ACCESS_inout_stdlv(10) AND PAL_ACCESS_inout_stdlv(13) AND OCB_ADRS_in_stdlv(1) AND NOT OCB_ADRS_in_stdlv(4) AND NOT OCB_ADRS_in_stdlv(2) AND OCB_DATA_inout_stdlv(6).PIN AND NOT OCB_ADRS_in_stdlv(3))); BOARD_CONTROL_2_DATA_int_stdlv_PRE(6) <= (NOT VME_SYSRESET_B_in_stdl AND NOT SYSRESET_TMP_1_int_stdl AND NOT SYSRESET_TMP_2_int_stdl AND NOT SYSRESET_TMP_3_int_stdl); FDCPE_CNFG_CCLK_out_stdl: FDCPE port map (CNFG_CCLK_out_stdl,CNFG_CCLK_out_stdl_D,PAL_BX_CLOCK_in_stdl,CNFG_CCLK_out_stdl_CLR,'0'); CNFG_CCLK_out_stdl_D <= (NOT LTCHD_WRITE_B_in_stdl AND PAL_ACCESS_inout_stdlv(8) AND LATCH_2_STATE_int_stdl AND BOARD_CONTROL_1_DATA_int_stdlv(4) AND NOT OCB_ADRS_in_stdlv(1) AND NOT OCB_ADRS_in_stdlv(4) AND OCB_ADRS_in_stdlv(2) AND OCB_ADRS_in_stdlv(3) AND NEXT_STATE_QUIESCENT_B_int_stdl); CNFG_CCLK_out_stdl_CLR <= (NOT VME_SYSRESET_B_in_stdl AND NOT SYSRESET_TMP_1_int_stdl AND NOT SYSRESET_TMP_2_int_stdl AND NOT SYSRESET_TMP_3_int_stdl); FDCPE_CNFG_CS_B_reg_stdlv0: FDCPE port map (CNFG_CS_B_reg_stdlv(0),CNFG_CS_B_reg_stdlv_D(0),PAL_BX_CLOCK_in_stdl,'0',CNFG_CS_B_reg_stdlv_PRE(0)); CNFG_CS_B_reg_stdlv_D(0) <= ((CNFG_CS_B_reg_stdlv(0) AND NOT N1881/N1881_D2) OR (PAL_ACCESS_inout_stdlv(8) AND NOT PAL_ACCESS_inout_stdlv(10) AND PAL_ACCESS_inout_stdlv(13) AND OCB_ADRS_in_stdlv(1) AND NOT OCB_ADRS_in_stdlv(4) AND NOT OCB_ADRS_in_stdlv(2) AND OCB_ADRS_in_stdlv(3) AND OCB_DATA_inout_stdlv(2).PIN)); CNFG_CS_B_reg_stdlv_PRE(0) <= (NOT VME_SYSRESET_B_in_stdl AND NOT SYSRESET_TMP_1_int_stdl AND NOT SYSRESET_TMP_2_int_stdl AND NOT SYSRESET_TMP_3_int_stdl); FDCPE_CNFG_CS_B_reg_stdlv1: FDCPE port map (CNFG_CS_B_reg_stdlv(1),CNFG_CS_B_reg_stdlv_D(1),PAL_BX_CLOCK_in_stdl,'0',CNFG_CS_B_reg_stdlv_PRE(1)); CNFG_CS_B_reg_stdlv_D(1) <= ((CNFG_CS_B_reg_stdlv(1) AND NOT N1881/N1881_D2) OR (PAL_ACCESS_inout_stdlv(8) AND NOT PAL_ACCESS_inout_stdlv(10) AND PAL_ACCESS_inout_stdlv(13) AND OCB_ADRS_in_stdlv(1) AND NOT OCB_ADRS_in_stdlv(4) AND NOT OCB_ADRS_in_stdlv(2) AND OCB_DATA_inout_stdlv(3).PIN AND OCB_ADRS_in_stdlv(3))); CNFG_CS_B_reg_stdlv_PRE(1) <= (NOT VME_SYSRESET_B_in_stdl AND NOT SYSRESET_TMP_1_int_stdl AND NOT SYSRESET_TMP_2_int_stdl AND NOT SYSRESET_TMP_3_int_stdl); FDCPE_CNFG_PROG_B_REQ_reg_stdlv0: FDCPE port map (CNFG_PROG_B_REQ_reg_stdlv(0),CNFG_PROG_B_REQ_reg_stdlv_D(0),PAL_BX_CLOCK_in_stdl,'0',CNFG_PROG_B_REQ_reg_stdlv_PRE(0)); CNFG_PROG_B_REQ_reg_stdlv_D(0) <= ((CNFG_PROG_B_REQ_reg_stdlv(0) AND NOT N1881/N1881_D2) OR (PAL_ACCESS_inout_stdlv(8) AND NOT PAL_ACCESS_inout_stdlv(10) AND PAL_ACCESS_inout_stdlv(13) AND OCB_ADRS_in_stdlv(1) AND NOT OCB_ADRS_in_stdlv(4) AND NOT OCB_ADRS_in_stdlv(2) AND OCB_DATA_inout_stdlv(0).PIN AND OCB_ADRS_in_stdlv(3))); CNFG_PROG_B_REQ_reg_stdlv_PRE(0) <= (NOT VME_SYSRESET_B_in_stdl AND NOT SYSRESET_TMP_1_int_stdl AND NOT SYSRESET_TMP_2_int_stdl AND NOT SYSRESET_TMP_3_int_stdl); FDCPE_CNFG_PROG_B_REQ_reg_stdlv1: FDCPE port map (CNFG_PROG_B_REQ_reg_stdlv(1),CNFG_PROG_B_REQ_reg_stdlv_D(1),PAL_BX_CLOCK_in_stdl,'0',CNFG_PROG_B_REQ_reg_stdlv_PRE(1)); CNFG_PROG_B_REQ_reg_stdlv_D(1) <= ((CNFG_PROG_B_REQ_reg_stdlv(1) AND NOT N1881/N1881_D2) OR (PAL_ACCESS_inout_stdlv(8) AND NOT PAL_ACCESS_inout_stdlv(10) AND PAL_ACCESS_inout_stdlv(13) AND OCB_ADRS_in_stdlv(1) AND NOT OCB_ADRS_in_stdlv(4) AND NOT OCB_ADRS_in_stdlv(2) AND OCB_DATA_inout_stdlv(1).PIN AND OCB_ADRS_in_stdlv(3))); CNFG_PROG_B_REQ_reg_stdlv_PRE(1) <= (NOT VME_SYSRESET_B_in_stdl AND NOT SYSRESET_TMP_1_int_stdl AND NOT SYSRESET_TMP_2_int_stdl AND NOT SYSRESET_TMP_3_int_stdl); FDCPE_CNFG_PROG_B_out_stdlv0: FDCPE port map (CNFG_PROG_B_out_stdlv(0),CNFG_PROG_B_out_stdlv_D(0),PAL_BX_CLOCK_in_stdl,'0',CNFG_PROG_B_out_stdlv_PRE(0)); CNFG_PROG_B_out_stdlv_D(0) <= (BOARD_CONTROL_1_DATA_int_stdlv(4) AND NOT CNFG_PROG_B_REQ_reg_stdlv(0)); CNFG_PROG_B_out_stdlv_PRE(0) <= (NOT VME_SYSRESET_B_in_stdl AND NOT SYSRESET_TMP_1_int_stdl AND NOT SYSRESET_TMP_2_int_stdl AND NOT SYSRESET_TMP_3_int_stdl); FDCPE_CNFG_PROG_B_out_stdlv1: FDCPE port map (CNFG_PROG_B_out_stdlv(1),CNFG_PROG_B_out_stdlv_D(1),PAL_BX_CLOCK_in_stdl,'0',CNFG_PROG_B_out_stdlv_PRE(1)); CNFG_PROG_B_out_stdlv_D(1) <= (BOARD_CONTROL_1_DATA_int_stdlv(4) AND NOT CNFG_PROG_B_REQ_reg_stdlv(1)); CNFG_PROG_B_out_stdlv_PRE(1) <= (NOT VME_SYSRESET_B_in_stdl AND NOT SYSRESET_TMP_1_int_stdl AND NOT SYSRESET_TMP_2_int_stdl AND NOT SYSRESET_TMP_3_int_stdl); FDCPE_CNFG_RDWR_B_reg_stdl: FDCPE port map (CNFG_RDWR_B_reg_stdl,CNFG_RDWR_B_reg_stdl_D,PAL_BX_CLOCK_in_stdl,'0',CNFG_RDWR_B_reg_stdl_PRE); CNFG_RDWR_B_reg_stdl_D <= ((CNFG_RDWR_B_reg_stdl AND NOT N1881/N1881_D2) OR (PAL_ACCESS_inout_stdlv(8) AND NOT PAL_ACCESS_inout_stdlv(10) AND PAL_ACCESS_inout_stdlv(13) AND OCB_ADRS_in_stdlv(1) AND NOT OCB_ADRS_in_stdlv(4) AND NOT OCB_ADRS_in_stdlv(2) AND OCB_DATA_inout_stdlv(4).PIN AND OCB_ADRS_in_stdlv(3))); CNFG_RDWR_B_reg_stdl_PRE <= (NOT VME_SYSRESET_B_in_stdl AND NOT SYSRESET_TMP_1_int_stdl AND NOT SYSRESET_TMP_2_int_stdl AND NOT SYSRESET_TMP_3_int_stdl); FTCPE_CNT_BIT_VAL_1_int_stdl: FTCPE port map (CNT_BIT_VAL_1_int_stdl,'1',PAL_BX_X8_CLOCK_in_stdl,'0','0'); FTCPE_CNT_BIT_VAL_2_int_stdl: FTCPE port map (CNT_BIT_VAL_2_int_stdl,CNT_BIT_VAL_1_int_stdl,PAL_BX_X8_CLOCK_in_stdl,'0','0'); FTCPE_CNT_BIT_VAL_4_inout_stdl: FTCPE port map (CNT_BIT_VAL_4_inout_stdl,CNT_BIT_VAL_4_inout_stdl_T,PAL_BX_X8_CLOCK_in_stdl,CNT_BIT_VAL_4_inout_stdl_CLR,'0'); CNT_BIT_VAL_4_inout_stdl_T <= ((NOT CNT_BIT_VAL_1_int_stdl AND NOT CNT_BIT_VAL_2_int_stdl) OR (CNT_BIT_VAL_4_inout_stdl AND CNT_BIT_VAL_1_int_stdl AND CNT_BIT_VAL_2_int_stdl)); CNT_BIT_VAL_4_inout_stdl_CLR <= (NOT VME_SYSRESET_B_in_stdl AND NOT SYSRESET_TMP_1_int_stdl AND NOT SYSRESET_TMP_2_int_stdl AND NOT SYSRESET_TMP_3_int_stdl); FDCPE_DAC_CHIP_SELECT_B_out_stdl: FDCPE port map (DAC_CHIP_SELECT_B_out_stdl,DAC_CHIP_SELECT_B_out_stdl_D,PAL_BX_CLOCK_in_stdl,'0',DAC_CHIP_SELECT_B_out_stdl_PRE); DAC_CHIP_SELECT_B_out_stdl_D <= (BOARD_CONTROL_1_DATA_int_stdlv(5) AND NOT BOARD_CONTROL_2_DATA_int_stdlv(6)); DAC_CHIP_SELECT_B_out_stdl_PRE <= (NOT VME_SYSRESET_B_in_stdl AND NOT SYSRESET_TMP_1_int_stdl AND NOT SYSRESET_TMP_2_int_stdl AND NOT SYSRESET_TMP_3_int_stdl); FDCPE_DAC_SERIAL_DATA_CLOCK_out_stdl: FDCPE port map (DAC_SERIAL_DATA_CLOCK_out_stdl,DAC_SERIAL_DATA_CLOCK_out_stdl_D,PAL_BX_CLOCK_in_stdl,'0',DAC_SERIAL_DATA_CLOCK_out_stdl_PRE); DAC_SERIAL_DATA_CLOCK_out_stdl_D <= (NOT LTCHD_WRITE_B_in_stdl AND PAL_ACCESS_inout_stdlv(8) AND LATCH_2_STATE_int_stdl AND NOT NEXT_STATE_QUIESCENT_int_stdl AND BOARD_CONTROL_1_DATA_int_stdlv(5) AND NOT OCB_ADRS_in_stdlv(1) AND NOT OCB_ADRS_in_stdlv(4) AND NOT OCB_ADRS_in_stdlv(2) AND OCB_ADRS_in_stdlv(3)); DAC_SERIAL_DATA_CLOCK_out_stdl_PRE <= (NOT VME_SYSRESET_B_in_stdl AND NOT SYSRESET_TMP_1_int_stdl AND NOT SYSRESET_TMP_2_int_stdl AND NOT SYSRESET_TMP_3_int_stdl); FDCPE_PAL_ACCESS_inout_stdlv6: FDCPE port map (PAL_ACCESS_inout_stdlv_I(6),PAL_ACCESS_inout_stdlv(6),PAL_BX_CLOCK_in_stdl,'0',PAL_ACCESS_inout_stdlv_PRE(6)); PAL_ACCESS_inout_stdlv(6) <= (NOT LTCHD_WRITE_B_in_stdl AND NOT LATCH_1_STATE_int_stdl AND NOT NEXT_STATE_QUIESCENT_int_stdl AND NOT SET_QUIESCENT_STATE_int_stdl AND NOT VALID_CYCLE_B_int_stdl); PAL_ACCESS_inout_stdlv_PRE(6) <= (NOT VME_SYSRESET_B_in_stdl AND NOT SYSRESET_TMP_1_int_stdl AND NOT SYSRESET_TMP_2_int_stdl AND NOT SYSRESET_TMP_3_int_stdl); PAL_ACCESS_inout_stdlv(6) <= PAL_ACCESS_inout_stdlv_I(6) when PAL_ACCESS_inout_stdlv_OE(6) = '1' else 'Z'; PAL_ACCESS_inout_stdlv_OE(6) <= BOARD_CONTROL_1_DATA_int_stdlv(6); FDCPE_DATA_BUF_DIR_out_stdl: FDCPE port map (DATA_BUF_DIR_out_stdl,DATA_BUF_DIR_out_stdl_D,PAL_BX_CLOCK_in_stdl,'0',DATA_BUF_DIR_out_stdl_PRE); DATA_BUF_DIR_out_stdl_D <= (NOT LTCHD_WRITE_B_in_stdl AND NOT LATCH_1_STATE_int_stdl AND NOT NEXT_STATE_QUIESCENT_int_stdl AND NOT SET_QUIESCENT_STATE_int_stdl AND NOT VALID_CYCLE_B_int_stdl); DATA_BUF_DIR_out_stdl_PRE <= (NOT VME_SYSRESET_B_in_stdl AND NOT SYSRESET_TMP_1_int_stdl AND NOT SYSRESET_TMP_2_int_stdl AND NOT SYSRESET_TMP_3_int_stdl); FDCPE_PAL_ACCESS_inout_stdlv5: FDCPE port map (PAL_ACCESS_inout_stdlv_I(5),PAL_ACCESS_inout_stdlv(5),PAL_BX_CLOCK_in_stdl,'0',PAL_ACCESS_inout_stdlv_PRE(5)); PAL_ACCESS_inout_stdlv(5) <= (NOT LATCH_1_STATE_int_stdl AND NOT NEXT_STATE_QUIESCENT_int_stdl AND NOT SET_QUIESCENT_STATE_int_stdl AND NOT VALID_CYCLE_B_int_stdl); PAL_ACCESS_inout_stdlv_PRE(5) <= (NOT VME_SYSRESET_B_in_stdl AND NOT SYSRESET_TMP_1_int_stdl AND NOT SYSRESET_TMP_2_int_stdl AND NOT SYSRESET_TMP_3_int_stdl); PAL_ACCESS_inout_stdlv(5) <= PAL_ACCESS_inout_stdlv_I(5) when PAL_ACCESS_inout_stdlv_OE(5) = '1' else 'Z'; PAL_ACCESS_inout_stdlv_OE(5) <= BOARD_CONTROL_1_DATA_int_stdlv(6); FDCPE_DATA_BUF_ENB_B_out_stdl: FDCPE port map (DATA_BUF_ENB_B_out_stdl,DATA_BUF_ENB_B_out_stdl_D,PAL_BX_CLOCK_in_stdl,'0',DATA_BUF_ENB_B_out_stdl_PRE); DATA_BUF_ENB_B_out_stdl_D <= (NOT LATCH_1_STATE_int_stdl AND NOT NEXT_STATE_QUIESCENT_int_stdl AND NOT SET_QUIESCENT_STATE_int_stdl AND NOT VALID_CYCLE_B_int_stdl); DATA_BUF_ENB_B_out_stdl_PRE <= (NOT VME_SYSRESET_B_in_stdl AND NOT SYSRESET_TMP_1_int_stdl AND NOT SYSRESET_TMP_2_int_stdl AND NOT SYSRESET_TMP_3_int_stdl); FDCPE_DATA_TO_FIRST_DAC_INPUT_out_stdl: FDCPE port map (DATA_TO_FIRST_DAC_INPUT_out_stdl,DATA_TO_FIRST_DAC_INPUT_out_stdl_D,PAL_BX_CLOCK_in_stdl,DATA_TO_FIRST_DAC_INPUT_out_stdl_CLR,'0'); DATA_TO_FIRST_DAC_INPUT_out_stdl_D <= (PAL_ACCESS_inout_stdlv(8) AND BOARD_CONTROL_1_DATA_int_stdlv(5) AND NOT OCB_ADRS_in_stdlv(1) AND NOT OCB_ADRS_in_stdlv(4) AND NOT OCB_ADRS_in_stdlv(2) AND OCB_DATA_inout_stdlv(0).PIN AND OCB_ADRS_in_stdlv(3) AND NEXT_STATE_QUIESCENT_B_int_stdl); DATA_TO_FIRST_DAC_INPUT_out_stdl_CLR <= (NOT VME_SYSRESET_B_in_stdl AND NOT SYSRESET_TMP_1_int_stdl AND NOT SYSRESET_TMP_2_int_stdl AND NOT SYSRESET_TMP_3_int_stdl); FDCPE_PAL_ACCESS_inout_stdlv16: FDCPE port map (PAL_ACCESS_inout_stdlv_I(16),PAL_ACCESS_inout_stdlv(16),PAL_BX_CLOCK_in_stdl,PAL_ACCESS_inout_stdlv_CLR(16),'0'); PAL_ACCESS_inout_stdlv(16) <= ((PAL_ACCESS_inout_stdlv(16) AND NOT N1871/N1871_D2) OR (PAL_ACCESS_inout_stdlv(8) AND NOT PAL_ACCESS_inout_stdlv(10) AND PAL_ACCESS_inout_stdlv(13) AND OCB_ADRS_in_stdlv(1) AND NOT OCB_ADRS_in_stdlv(4) AND NOT OCB_ADRS_in_stdlv(2) AND OCB_DATA_inout_stdlv(0).PIN AND NOT OCB_ADRS_in_stdlv(3))); PAL_ACCESS_inout_stdlv_CLR(16) <= (NOT VME_SYSRESET_B_in_stdl AND NOT SYSRESET_TMP_1_int_stdl AND NOT SYSRESET_TMP_2_int_stdl AND NOT SYSRESET_TMP_3_int_stdl); PAL_ACCESS_inout_stdlv(16) <= PAL_ACCESS_inout_stdlv_I(16) when PAL_ACCESS_inout_stdlv_OE(16) = '1' else 'Z'; PAL_ACCESS_inout_stdlv_OE(16) <= BOARD_CONTROL_1_DATA_int_stdlv(6); FDCPE_DRV_CRATE_STATUS_reg_stdlv0: FDCPE port map (DRV_CRATE_STATUS_reg_stdlv(0),DRV_CRATE_STATUS_reg_stdlv_D(0),PAL_BX_CLOCK_in_stdl,DRV_CRATE_STATUS_reg_stdlv_CLR(0),'0'); DRV_CRATE_STATUS_reg_stdlv_D(0) <= ((PAL_ACCESS_inout_stdlv(16) AND NOT N1871/N1871_D2) OR (PAL_ACCESS_inout_stdlv(8) AND NOT PAL_ACCESS_inout_stdlv(10) AND PAL_ACCESS_inout_stdlv(13) AND OCB_ADRS_in_stdlv(1) AND NOT OCB_ADRS_in_stdlv(4) AND NOT OCB_ADRS_in_stdlv(2) AND OCB_DATA_inout_stdlv(0).PIN AND NOT OCB_ADRS_in_stdlv(3))); DRV_CRATE_STATUS_reg_stdlv_CLR(0) <= (NOT VME_SYSRESET_B_in_stdl AND NOT SYSRESET_TMP_1_int_stdl AND NOT SYSRESET_TMP_2_int_stdl AND NOT SYSRESET_TMP_3_int_stdl); FDCPE_DRV_CRATE_STATUS_reg_stdlv1: FDCPE port map (DRV_CRATE_STATUS_reg_stdlv(1),DRV_CRATE_STATUS_reg_stdlv_D(1),PAL_BX_CLOCK_in_stdl,DRV_CRATE_STATUS_reg_stdlv_CLR(1),'0'); DRV_CRATE_STATUS_reg_stdlv_D(1) <= ((DRV_CRATE_STATUS_reg_stdlv(1) AND NOT N1871/N1871_D2) OR (PAL_ACCESS_inout_stdlv(8) AND NOT PAL_ACCESS_inout_stdlv(10) AND PAL_ACCESS_inout_stdlv(13) AND OCB_ADRS_in_stdlv(1) AND NOT OCB_ADRS_in_stdlv(4) AND NOT OCB_ADRS_in_stdlv(2) AND OCB_DATA_inout_stdlv(1).PIN AND NOT OCB_ADRS_in_stdlv(3))); DRV_CRATE_STATUS_reg_stdlv_CLR(1) <= (NOT VME_SYSRESET_B_in_stdl AND NOT SYSRESET_TMP_1_int_stdl AND NOT SYSRESET_TMP_2_int_stdl AND NOT SYSRESET_TMP_3_int_stdl); FDCPE_DRV_CRATE_STATUS_reg_stdlv2: FDCPE port map (DRV_CRATE_STATUS_reg_stdlv(2),DRV_CRATE_STATUS_reg_stdlv_D(2),PAL_BX_CLOCK_in_stdl,DRV_CRATE_STATUS_reg_stdlv_CLR(2),'0'); DRV_CRATE_STATUS_reg_stdlv_D(2) <= ((DRV_CRATE_STATUS_reg_stdlv(2) AND NOT N1871/N1871_D2) OR (PAL_ACCESS_inout_stdlv(8) AND NOT PAL_ACCESS_inout_stdlv(10) AND PAL_ACCESS_inout_stdlv(13) AND OCB_ADRS_in_stdlv(1) AND NOT OCB_ADRS_in_stdlv(4) AND NOT OCB_ADRS_in_stdlv(2) AND NOT OCB_ADRS_in_stdlv(3) AND OCB_DATA_inout_stdlv(2).PIN)); DRV_CRATE_STATUS_reg_stdlv_CLR(2) <= (NOT VME_SYSRESET_B_in_stdl AND NOT SYSRESET_TMP_1_int_stdl AND NOT SYSRESET_TMP_2_int_stdl AND NOT SYSRESET_TMP_3_int_stdl); FDCPE_DRV_CRATE_STATUS_reg_stdlv3: FDCPE port map (DRV_CRATE_STATUS_reg_stdlv(3),DRV_CRATE_STATUS_reg_stdlv_D(3),PAL_BX_CLOCK_in_stdl,DRV_CRATE_STATUS_reg_stdlv_CLR(3),'0'); DRV_CRATE_STATUS_reg_stdlv_D(3) <= ((DRV_CRATE_STATUS_reg_stdlv(3) AND NOT N1871/N1871_D2) OR (PAL_ACCESS_inout_stdlv(8) AND NOT PAL_ACCESS_inout_stdlv(10) AND PAL_ACCESS_inout_stdlv(13) AND OCB_ADRS_in_stdlv(1) AND NOT OCB_ADRS_in_stdlv(4) AND NOT OCB_ADRS_in_stdlv(2) AND OCB_DATA_inout_stdlv(3).PIN AND NOT OCB_ADRS_in_stdlv(3))); DRV_CRATE_STATUS_reg_stdlv_CLR(3) <= (NOT VME_SYSRESET_B_in_stdl AND NOT SYSRESET_TMP_1_int_stdl AND NOT SYSRESET_TMP_2_int_stdl AND NOT SYSRESET_TMP_3_int_stdl); FDCPE_DRV_CRATE_TO_SCLD_reg_stdlv0: FDCPE port map (DRV_CRATE_TO_SCLD_reg_stdlv(0),DRV_CRATE_TO_SCLD_reg_stdlv_D(0),PAL_BX_CLOCK_in_stdl,DRV_CRATE_TO_SCLD_reg_stdlv_CLR(0),'0'); DRV_CRATE_TO_SCLD_reg_stdlv_D(0) <= ((DRV_CRATE_TO_SCLD_reg_stdlv(0) AND NOT N1871/N1871_D2) OR (PAL_ACCESS_inout_stdlv(8) AND NOT PAL_ACCESS_inout_stdlv(10) AND PAL_ACCESS_inout_stdlv(13) AND OCB_ADRS_in_stdlv(1) AND NOT OCB_ADRS_in_stdlv(4) AND NOT OCB_ADRS_in_stdlv(2) AND OCB_DATA_inout_stdlv(4).PIN AND NOT OCB_ADRS_in_stdlv(3))); DRV_CRATE_TO_SCLD_reg_stdlv_CLR(0) <= (NOT VME_SYSRESET_B_in_stdl AND NOT SYSRESET_TMP_1_int_stdl AND NOT SYSRESET_TMP_2_int_stdl AND NOT SYSRESET_TMP_3_int_stdl); FDCPE_DRV_CRATE_TO_SCLD_reg_stdlv1: FDCPE port map (DRV_CRATE_TO_SCLD_reg_stdlv(1),DRV_CRATE_TO_SCLD_reg_stdlv_D(1),PAL_BX_CLOCK_in_stdl,DRV_CRATE_TO_SCLD_reg_stdlv_CLR(1),'0'); DRV_CRATE_TO_SCLD_reg_stdlv_D(1) <= ((DRV_CRATE_TO_SCLD_reg_stdlv(1) AND NOT N1871/N1871_D2) OR (PAL_ACCESS_inout_stdlv(8) AND NOT PAL_ACCESS_inout_stdlv(10) AND PAL_ACCESS_inout_stdlv(13) AND OCB_ADRS_in_stdlv(1) AND NOT OCB_ADRS_in_stdlv(4) AND NOT OCB_ADRS_in_stdlv(2) AND OCB_DATA_inout_stdlv(5).PIN AND NOT OCB_ADRS_in_stdlv(3))); DRV_CRATE_TO_SCLD_reg_stdlv_CLR(1) <= (NOT VME_SYSRESET_B_in_stdl AND NOT SYSRESET_TMP_1_int_stdl AND NOT SYSRESET_TMP_2_int_stdl AND NOT SYSRESET_TMP_3_int_stdl); FDCPE_PAL_ACCESS_inout_stdlv2: FDCPE port map (PAL_ACCESS_inout_stdlv_I(2),PAL_ACCESS_inout_stdlv(2),PAL_BX_CLOCK_in_stdl,PAL_ACCESS_inout_stdlv_CLR(2),'0'); PAL_ACCESS_inout_stdlv(2) <= ((IO_1_STATE_int_stdl AND NEXT_STATE_QUIESCENT_B_int_stdl) OR (PAL_ACCESS_inout_stdlv(3) AND PAL_ACCESS_inout_stdlv(1) AND IO_2_STATE_int_stdl AND NEXT_STATE_QUIESCENT_B_int_stdl)); PAL_ACCESS_inout_stdlv_CLR(2) <= (NOT VME_SYSRESET_B_in_stdl AND NOT SYSRESET_TMP_1_int_stdl AND NOT SYSRESET_TMP_2_int_stdl AND NOT SYSRESET_TMP_3_int_stdl); PAL_ACCESS_inout_stdlv(2) <= PAL_ACCESS_inout_stdlv_I(2) when PAL_ACCESS_inout_stdlv_OE(2) = '1' else 'Z'; PAL_ACCESS_inout_stdlv_OE(2) <= BOARD_CONTROL_1_DATA_int_stdlv(6); FDCPE_DRV_DTACK_out_stdl: FDCPE port map (DRV_DTACK_out_stdl,DRV_DTACK_out_stdl_D,PAL_BX_CLOCK_in_stdl,DRV_DTACK_out_stdl_CLR,'0'); DRV_DTACK_out_stdl_D <= ((IO_1_STATE_int_stdl AND NEXT_STATE_QUIESCENT_B_int_stdl) OR (PAL_ACCESS_inout_stdlv(3) AND PAL_ACCESS_inout_stdlv(1) AND IO_2_STATE_int_stdl AND NEXT_STATE_QUIESCENT_B_int_stdl)); DRV_DTACK_out_stdl_CLR <= (NOT VME_SYSRESET_B_in_stdl AND NOT SYSRESET_TMP_1_int_stdl AND NOT SYSRESET_TMP_2_int_stdl AND NOT SYSRESET_TMP_3_int_stdl); FDCPE_DRV_PAL_LED_out_stdlv0: FDCPE port map (DRV_PAL_LED_out_stdlv(0),DRV_PAL_LED_out_stdlv_D(0),PAL_BX_CLOCK_in_stdl,'0',DRV_PAL_LED_out_stdlv_PRE(0)); DRV_PAL_LED_out_stdlv_D(0) <= (LED_STRETCHER_CB16CE/Q(13) AND LED_STRETCHER_CB16CE/Q(1) AND LED_STRETCHER_CB16CE/Q(10) AND LED_STRETCHER_CB16CE/Q(11) AND LED_STRETCHER_CB16CE/Q(12) AND LED_STRETCHER_CB16CE/Q(2) AND LED_STRETCHER_CB16CE/Q(3) AND LED_STRETCHER_CB16CE/Q(4) AND LED_STRETCHER_CB16CE/Q(5) AND LED_STRETCHER_CB16CE/Q(6) AND LED_STRETCHER_CB16CE/Q(7) AND LED_STRETCHER_CB16CE/Q(8) AND LED_STRETCHER_CB16CE/Q(9) AND LED_STRETCHER_CB16CE/Q(0)); DRV_PAL_LED_out_stdlv_PRE(0) <= (NOT VME_SYSRESET_B_in_stdl AND NOT SYSRESET_TMP_1_int_stdl AND NOT SYSRESET_TMP_2_int_stdl AND NOT SYSRESET_TMP_3_int_stdl); FDCPE_DRV_PAL_LED_out_stdlv1: FDCPE port map (DRV_PAL_LED_out_stdlv(1),NOT BOARD_CONTROL_1_DATA_int_stdlv(3),PAL_BX_CLOCK_in_stdl,'0',DRV_PAL_LED_out_stdlv_PRE(1)); DRV_PAL_LED_out_stdlv_PRE(1) <= (NOT VME_SYSRESET_B_in_stdl AND NOT SYSRESET_TMP_1_int_stdl AND NOT SYSRESET_TMP_2_int_stdl AND NOT SYSRESET_TMP_3_int_stdl); FDCPE_DS1_tmp_int_stdl: FDCPE port map (DS1_tmp_int_stdl,RCVD_DS1_in_stdl,PAL_BX_CLOCK_in_stdl,'0','0'); FDCPE_IDLE_STATE_int_stdl: FDCPE port map (IDLE_STATE_int_stdl,IDLE_STATE_int_stdl_D,PAL_BX_CLOCK_in_stdl,'0',IDLE_STATE_int_stdl_PRE); IDLE_STATE_int_stdl_D <= ((_n0113/_n0113_D2.EXP) OR (NOT LATCH_2_STATE_int_stdl AND IO_2_STATE_int_stdl AND NOT IO_1_STATE_int_stdl AND NOT LATCH_1_STATE_int_stdl AND NOT SET_QUIESCENT_STATE_int_stdl AND NOT IDLE_STATE_int_stdl) OR (PAL_ACCESS_inout_stdlv(1) AND NOT LATCH_2_STATE_int_stdl AND NOT IO_2_STATE_int_stdl AND NOT IO_1_STATE_int_stdl AND LATCH_1_STATE_int_stdl AND NOT SET_QUIESCENT_STATE_int_stdl AND NOT IDLE_STATE_int_stdl) OR (PAL_ACCESS_inout_stdlv(1) AND NOT LATCH_2_STATE_int_stdl AND NOT IO_2_STATE_int_stdl AND NOT IO_1_STATE_int_stdl AND NOT LATCH_1_STATE_int_stdl AND NOT SET_QUIESCENT_STATE_int_stdl AND IDLE_STATE_int_stdl)); IDLE_STATE_int_stdl_PRE <= (NOT VME_SYSRESET_B_in_stdl AND NOT SYSRESET_TMP_1_int_stdl AND NOT SYSRESET_TMP_2_int_stdl AND NOT SYSRESET_TMP_3_int_stdl); FDCPE_IO_1_STATE_int_stdl: FDCPE port map (IO_1_STATE_int_stdl,IO_1_STATE_int_stdl_D,PAL_BX_CLOCK_in_stdl,IO_1_STATE_int_stdl_CLR,'0'); IO_1_STATE_int_stdl_D <= (PAL_ACCESS_inout_stdlv(3) AND PAL_ACCESS_inout_stdlv(1) AND LATCH_2_STATE_int_stdl AND NOT IO_2_STATE_int_stdl AND NOT IO_1_STATE_int_stdl AND NOT LATCH_1_STATE_int_stdl AND NOT SET_QUIESCENT_STATE_int_stdl AND NOT IDLE_STATE_int_stdl); IO_1_STATE_int_stdl_CLR <= (NOT VME_SYSRESET_B_in_stdl AND NOT SYSRESET_TMP_1_int_stdl AND NOT SYSRESET_TMP_2_int_stdl AND NOT SYSRESET_TMP_3_int_stdl); FDCPE_IO_2_STATE_int_stdl: FDCPE port map (IO_2_STATE_int_stdl,IO_2_STATE_int_stdl_D,PAL_BX_CLOCK_in_stdl,IO_2_STATE_int_stdl_CLR,'0'); IO_2_STATE_int_stdl_D <= ((IO_1_STATE_int_stdl.EXP) OR (PAL_ACCESS_inout_stdlv(1) AND NOT LATCH_2_STATE_int_stdl AND IO_2_STATE_int_stdl AND NOT IO_1_STATE_int_stdl AND NOT LATCH_1_STATE_int_stdl AND NOT SET_QUIESCENT_STATE_int_stdl AND NOT IDLE_STATE_int_stdl)); IO_2_STATE_int_stdl_CLR <= (NOT VME_SYSRESET_B_in_stdl AND NOT SYSRESET_TMP_1_int_stdl AND NOT SYSRESET_TMP_2_int_stdl AND NOT SYSRESET_TMP_3_int_stdl); FDCPE_LATCH_1_STATE_int_stdl: FDCPE port map (LATCH_1_STATE_int_stdl,LATCH_1_STATE_int_stdl_D,PAL_BX_CLOCK_in_stdl,LATCH_1_STATE_int_stdl_CLR,'0'); LATCH_1_STATE_int_stdl_D <= (PAL_ACCESS_inout_stdlv(1) AND NOT LATCH_2_STATE_int_stdl AND NOT IO_2_STATE_int_stdl AND NOT IO_1_STATE_int_stdl AND NOT LATCH_1_STATE_int_stdl AND NOT SET_QUIESCENT_STATE_int_stdl AND IDLE_STATE_int_stdl); LATCH_1_STATE_int_stdl_CLR <= (NOT VME_SYSRESET_B_in_stdl AND NOT SYSRESET_TMP_1_int_stdl AND NOT SYSRESET_TMP_2_int_stdl AND NOT SYSRESET_TMP_3_int_stdl); FDCPE_LATCH_2_STATE_int_stdl: FDCPE port map (LATCH_2_STATE_int_stdl,LATCH_2_STATE_int_stdl_D,PAL_BX_CLOCK_in_stdl,LATCH_2_STATE_int_stdl_CLR,'0'); LATCH_2_STATE_int_stdl_D <= (PAL_ACCESS_inout_stdlv(1) AND NOT LATCH_2_STATE_int_stdl AND NOT IO_2_STATE_int_stdl AND NOT IO_1_STATE_int_stdl AND LATCH_1_STATE_int_stdl AND NOT SET_QUIESCENT_STATE_int_stdl AND NOT IDLE_STATE_int_stdl); LATCH_2_STATE_int_stdl_CLR <= (NOT VME_SYSRESET_B_in_stdl AND NOT SYSRESET_TMP_1_int_stdl AND NOT SYSRESET_TMP_2_int_stdl AND NOT SYSRESET_TMP_3_int_stdl); FTCPE_LED_STRETCHER_CB16CE/Q0: FTCPE port map (LED_STRETCHER_CB16CE/Q(0),LED_STRETCHER_CB16CE/Q_T(0),PAL_BX_CLOCK_in_stdl,LED_STRETCHER_CB16CE/Q_CLR(0),'0'); LED_STRETCHER_CB16CE/Q_T(0) <= ((LED_STRETCHER_CB16CE/Q(13) AND LED_STRETCHER_CB16CE/Q(1) AND LED_STRETCHER_CB16CE/Q(10) AND LED_STRETCHER_CB16CE/Q(11) AND LED_STRETCHER_CB16CE/Q(12) AND LED_STRETCHER_CB16CE/Q(2) AND LED_STRETCHER_CB16CE/Q(3) AND LED_STRETCHER_CB16CE/Q(4) AND LED_STRETCHER_CB16CE/Q(5) AND LED_STRETCHER_CB16CE/Q(6) AND LED_STRETCHER_CB16CE/Q(7) AND LED_STRETCHER_CB16CE/Q(8) AND LED_STRETCHER_CB16CE/Q(9) AND LED_STRETCHER_CB16CE/Q(0)) OR (LED_STRETCHER_CB16CE/Q(13) AND LED_STRETCHER_CB16CE/Q(1) AND LED_STRETCHER_CB16CE/Q(10) AND LED_STRETCHER_CB16CE/Q(11) AND LED_STRETCHER_CB16CE/Q(12) AND LED_STRETCHER_CB16CE/Q(2) AND LED_STRETCHER_CB16CE/Q(3) AND LED_STRETCHER_CB16CE/Q(4) AND LED_STRETCHER_CB16CE/Q(5) AND LED_STRETCHER_CB16CE/Q(6) AND LED_STRETCHER_CB16CE/Q(7) AND LED_STRETCHER_CB16CE/Q(8) AND LED_STRETCHER_CB16CE/Q(9) AND PAL_ACCESS_inout_stdlv(3))); LED_STRETCHER_CB16CE/Q_CLR(0) <= (NOT VME_SYSRESET_B_in_stdl AND NOT SYSRESET_TMP_1_int_stdl AND NOT SYSRESET_TMP_2_int_stdl AND NOT SYSRESET_TMP_3_int_stdl); FDCPE_LED_STRETCHER_CB16CE/Q1: FDCPE port map (LED_STRETCHER_CB16CE/Q(1),LED_STRETCHER_CB16CE/Q_D(1),PAL_BX_CLOCK_in_stdl,LED_STRETCHER_CB16CE/Q_CLR(1),'0'); LED_STRETCHER_CB16CE/Q_D(1) <= ((LED_STRETCHER_CB16CE/Q(1) AND NOT LED_STRETCHER_CE_int_stdl/LED_STRETCHER_CE_int_stdl_D2) OR ( LED_STRETCHER_CE_int_stdl/LED_STRETCHER_CE_int_stdl_D2 AND LED_STRETCHER_CB16CE/Q__n0000(12)/LED_STRETCHER_CB16CE/Q__n0000(12)_D)); LED_STRETCHER_CB16CE/Q_CLR(1) <= (NOT VME_SYSRESET_B_in_stdl AND NOT SYSRESET_TMP_1_int_stdl AND NOT SYSRESET_TMP_2_int_stdl AND NOT SYSRESET_TMP_3_int_stdl); FTCPE_LED_STRETCHER_CB16CE/Q10: FTCPE port map (LED_STRETCHER_CB16CE/Q(10),LED_STRETCHER_CB16CE/Q_T(10),PAL_BX_CLOCK_in_stdl,LED_STRETCHER_CB16CE/Q_CLR(10),'0'); LED_STRETCHER_CB16CE/Q_T(10) <= (LED_STRETCHER_CB16CE/Q(13) AND LED_STRETCHER_CB16CE/Q(11) AND LED_STRETCHER_CB16CE/Q(12) AND LED_STRETCHER_CE_int_stdl/LED_STRETCHER_CE_int_stdl_D2); LED_STRETCHER_CB16CE/Q_CLR(10) <= (NOT VME_SYSRESET_B_in_stdl AND NOT SYSRESET_TMP_1_int_stdl AND NOT SYSRESET_TMP_2_int_stdl AND NOT SYSRESET_TMP_3_int_stdl); FTCPE_LED_STRETCHER_CB16CE/Q11: FTCPE port map (LED_STRETCHER_CB16CE/Q(11),LED_STRETCHER_CB16CE/Q_T(11),PAL_BX_CLOCK_in_stdl,LED_STRETCHER_CB16CE/Q_CLR(11),'0'); LED_STRETCHER_CB16CE/Q_T(11) <= (LED_STRETCHER_CB16CE/Q(13) AND LED_STRETCHER_CB16CE/Q(12) AND LED_STRETCHER_CE_int_stdl/LED_STRETCHER_CE_int_stdl_D2); LED_STRETCHER_CB16CE/Q_CLR(11) <= (NOT VME_SYSRESET_B_in_stdl AND NOT SYSRESET_TMP_1_int_stdl AND NOT SYSRESET_TMP_2_int_stdl AND NOT SYSRESET_TMP_3_int_stdl); FTCPE_LED_STRETCHER_CB16CE/Q12: FTCPE port map (LED_STRETCHER_CB16CE/Q(12),LED_STRETCHER_CB16CE/Q_T(12),PAL_BX_CLOCK_in_stdl,LED_STRETCHER_CB16CE/Q_CLR(12),'0'); LED_STRETCHER_CB16CE/Q_T(12) <= (LED_STRETCHER_CB16CE/Q(13) AND LED_STRETCHER_CE_int_stdl/LED_STRETCHER_CE_int_stdl_D2); LED_STRETCHER_CB16CE/Q_CLR(12) <= (NOT VME_SYSRESET_B_in_stdl AND NOT SYSRESET_TMP_1_int_stdl AND NOT SYSRESET_TMP_2_int_stdl AND NOT SYSRESET_TMP_3_int_stdl); FTCPE_LED_STRETCHER_CB16CE/Q13: FTCPE port map (LED_STRETCHER_CB16CE/Q(13),LED_STRETCHER_CE_int_stdl/LED_STRETCHER_CE_int_stdl_D2,PAL_BX_CLOCK_in_stdl,LED_STRETCHER_CB16CE/Q_CLR(13),'0'); LED_STRETCHER_CB16CE/Q_CLR(13) <= (NOT VME_SYSRESET_B_in_stdl AND NOT SYSRESET_TMP_1_int_stdl AND NOT SYSRESET_TMP_2_int_stdl AND NOT SYSRESET_TMP_3_int_stdl); FDCPE_LED_STRETCHER_CB16CE/Q2: FDCPE port map (LED_STRETCHER_CB16CE/Q(2),LED_STRETCHER_CB16CE/Q_D(2),PAL_BX_CLOCK_in_stdl,LED_STRETCHER_CB16CE/Q_CLR(2),'0'); LED_STRETCHER_CB16CE/Q_D(2) <= ((LED_STRETCHER_CB16CE/Q(2) AND NOT LED_STRETCHER_CE_int_stdl/LED_STRETCHER_CE_int_stdl_D2) OR ( LED_STRETCHER_CE_int_stdl/LED_STRETCHER_CE_int_stdl_D2 AND LED_STRETCHER_CB16CE/Q__n0000(11)/LED_STRETCHER_CB16CE/Q__n0000(11)_D)); LED_STRETCHER_CB16CE/Q_CLR(2) <= (NOT VME_SYSRESET_B_in_stdl AND NOT SYSRESET_TMP_1_int_stdl AND NOT SYSRESET_TMP_2_int_stdl AND NOT SYSRESET_TMP_3_int_stdl); FDCPE_LED_STRETCHER_CB16CE/Q3: FDCPE port map (LED_STRETCHER_CB16CE/Q(3),LED_STRETCHER_CB16CE/Q_D(3),PAL_BX_CLOCK_in_stdl,LED_STRETCHER_CB16CE/Q_CLR(3),'0'); LED_STRETCHER_CB16CE/Q_D(3) <= ((LED_STRETCHER_CB16CE/Q(3) AND NOT LED_STRETCHER_CE_int_stdl/LED_STRETCHER_CE_int_stdl_D2) OR ( LED_STRETCHER_CE_int_stdl/LED_STRETCHER_CE_int_stdl_D2 AND LED_STRETCHER_CB16CE/Q__n0000(10)/LED_STRETCHER_CB16CE/Q__n0000(10)_D)); LED_STRETCHER_CB16CE/Q_CLR(3) <= (NOT VME_SYSRESET_B_in_stdl AND NOT SYSRESET_TMP_1_int_stdl AND NOT SYSRESET_TMP_2_int_stdl AND NOT SYSRESET_TMP_3_int_stdl); FDCPE_LED_STRETCHER_CB16CE/Q4: FDCPE port map (LED_STRETCHER_CB16CE/Q(4),LED_STRETCHER_CB16CE/Q_D(4),PAL_BX_CLOCK_in_stdl,LED_STRETCHER_CB16CE/Q_CLR(4),'0'); LED_STRETCHER_CB16CE/Q_D(4) <= ((LED_STRETCHER_CB16CE/Q(4) AND NOT LED_STRETCHER_CE_int_stdl/LED_STRETCHER_CE_int_stdl_D2) OR ( LED_STRETCHER_CE_int_stdl/LED_STRETCHER_CE_int_stdl_D2 AND LED_STRETCHER_CB16CE/Q__n0000(9)/LED_STRETCHER_CB16CE/Q__n0000(9)_D)); LED_STRETCHER_CB16CE/Q_CLR(4) <= (NOT VME_SYSRESET_B_in_stdl AND NOT SYSRESET_TMP_1_int_stdl AND NOT SYSRESET_TMP_2_int_stdl AND NOT SYSRESET_TMP_3_int_stdl); FDCPE_LED_STRETCHER_CB16CE/Q5: FDCPE port map (LED_STRETCHER_CB16CE/Q(5),LED_STRETCHER_CB16CE/Q_D(5),PAL_BX_CLOCK_in_stdl,LED_STRETCHER_CB16CE/Q_CLR(5),'0'); LED_STRETCHER_CB16CE/Q_D(5) <= ((LED_STRETCHER_CB16CE/Q(5) AND NOT LED_STRETCHER_CE_int_stdl/LED_STRETCHER_CE_int_stdl_D2) OR ( LED_STRETCHER_CE_int_stdl/LED_STRETCHER_CE_int_stdl_D2 AND LED_STRETCHER_CB16CE/Q__n0000(8)/LED_STRETCHER_CB16CE/Q__n0000(8)_D)); LED_STRETCHER_CB16CE/Q_CLR(5) <= (NOT VME_SYSRESET_B_in_stdl AND NOT SYSRESET_TMP_1_int_stdl AND NOT SYSRESET_TMP_2_int_stdl AND NOT SYSRESET_TMP_3_int_stdl); FDCPE_LED_STRETCHER_CB16CE/Q6: FDCPE port map (LED_STRETCHER_CB16CE/Q(6),LED_STRETCHER_CB16CE/Q_D(6),PAL_BX_CLOCK_in_stdl,LED_STRETCHER_CB16CE/Q_CLR(6),'0'); LED_STRETCHER_CB16CE/Q_D(6) <= ((LED_STRETCHER_CB16CE/Q(6) AND NOT LED_STRETCHER_CE_int_stdl/LED_STRETCHER_CE_int_stdl_D2) OR ( LED_STRETCHER_CE_int_stdl/LED_STRETCHER_CE_int_stdl_D2 AND LED_STRETCHER_CB16CE/Q__n0000(7)/LED_STRETCHER_CB16CE/Q__n0000(7)_D)); LED_STRETCHER_CB16CE/Q_CLR(6) <= (NOT VME_SYSRESET_B_in_stdl AND NOT SYSRESET_TMP_1_int_stdl AND NOT SYSRESET_TMP_2_int_stdl AND NOT SYSRESET_TMP_3_int_stdl); FTCPE_LED_STRETCHER_CB16CE/Q7: FTCPE port map (LED_STRETCHER_CB16CE/Q(7),LED_STRETCHER_CB16CE/Q_T(7),PAL_BX_CLOCK_in_stdl,LED_STRETCHER_CB16CE/Q_CLR(7),'0'); LED_STRETCHER_CB16CE/Q_T(7) <= (LED_STRETCHER_CB16CE/Q(13) AND LED_STRETCHER_CB16CE/Q(10) AND LED_STRETCHER_CB16CE/Q(11) AND LED_STRETCHER_CB16CE/Q(12) AND LED_STRETCHER_CB16CE/Q(8) AND LED_STRETCHER_CB16CE/Q(9) AND LED_STRETCHER_CE_int_stdl/LED_STRETCHER_CE_int_stdl_D2); LED_STRETCHER_CB16CE/Q_CLR(7) <= (NOT VME_SYSRESET_B_in_stdl AND NOT SYSRESET_TMP_1_int_stdl AND NOT SYSRESET_TMP_2_int_stdl AND NOT SYSRESET_TMP_3_int_stdl); FTCPE_LED_STRETCHER_CB16CE/Q8: FTCPE port map (LED_STRETCHER_CB16CE/Q(8),LED_STRETCHER_CB16CE/Q_T(8),PAL_BX_CLOCK_in_stdl,LED_STRETCHER_CB16CE/Q_CLR(8),'0'); LED_STRETCHER_CB16CE/Q_T(8) <= (LED_STRETCHER_CB16CE/Q(13) AND LED_STRETCHER_CB16CE/Q(10) AND LED_STRETCHER_CB16CE/Q(11) AND LED_STRETCHER_CB16CE/Q(12) AND LED_STRETCHER_CB16CE/Q(9) AND LED_STRETCHER_CE_int_stdl/LED_STRETCHER_CE_int_stdl_D2); LED_STRETCHER_CB16CE/Q_CLR(8) <= (NOT VME_SYSRESET_B_in_stdl AND NOT SYSRESET_TMP_1_int_stdl AND NOT SYSRESET_TMP_2_int_stdl AND NOT SYSRESET_TMP_3_int_stdl); FTCPE_LED_STRETCHER_CB16CE/Q9: FTCPE port map (LED_STRETCHER_CB16CE/Q(9),LED_STRETCHER_CB16CE/Q_T(9),PAL_BX_CLOCK_in_stdl,LED_STRETCHER_CB16CE/Q_CLR(9),'0'); LED_STRETCHER_CB16CE/Q_T(9) <= (LED_STRETCHER_CB16CE/Q(13) AND LED_STRETCHER_CB16CE/Q(10) AND LED_STRETCHER_CB16CE/Q(11) AND LED_STRETCHER_CB16CE/Q(12) AND LED_STRETCHER_CE_int_stdl/LED_STRETCHER_CE_int_stdl_D2); LED_STRETCHER_CB16CE/Q_CLR(9) <= (NOT VME_SYSRESET_B_in_stdl AND NOT SYSRESET_TMP_1_int_stdl AND NOT SYSRESET_TMP_2_int_stdl AND NOT SYSRESET_TMP_3_int_stdl); LED_STRETCHER_CB16CE/Q__n0000(10)/LED_STRETCHER_CB16CE/Q__n0000(10)_D <= LED_STRETCHER_CB16CE/Q(3) XOR LED_STRETCHER_CB16CE/Q__n0000(10)/LED_STRETCHER_CB16CE/Q__n0000(10)_D <= (LED_STRETCHER_CB16CE/Q(13) AND LED_STRETCHER_CB16CE/Q(10) AND LED_STRETCHER_CB16CE/Q(11) AND LED_STRETCHER_CB16CE/Q(12) AND LED_STRETCHER_CB16CE/Q(4) AND LED_STRETCHER_CB16CE/Q(5) AND LED_STRETCHER_CB16CE/Q(6) AND LED_STRETCHER_CB16CE/Q(7) AND LED_STRETCHER_CB16CE/Q(8) AND LED_STRETCHER_CB16CE/Q(9)); LED_STRETCHER_CB16CE/Q__n0000(11)/LED_STRETCHER_CB16CE/Q__n0000(11)_D <= LED_STRETCHER_CB16CE/Q(2) XOR LED_STRETCHER_CB16CE/Q__n0000(11)/LED_STRETCHER_CB16CE/Q__n0000(11)_D <= (LED_STRETCHER_CB16CE/Q(13) AND LED_STRETCHER_CB16CE/Q(10) AND LED_STRETCHER_CB16CE/Q(11) AND LED_STRETCHER_CB16CE/Q(12) AND LED_STRETCHER_CB16CE/Q(3) AND LED_STRETCHER_CB16CE/Q(4) AND LED_STRETCHER_CB16CE/Q(5) AND LED_STRETCHER_CB16CE/Q(6) AND LED_STRETCHER_CB16CE/Q(7) AND LED_STRETCHER_CB16CE/Q(8) AND LED_STRETCHER_CB16CE/Q(9)); LED_STRETCHER_CB16CE/Q__n0000(12)/LED_STRETCHER_CB16CE/Q__n0000(12)_D <= LED_STRETCHER_CB16CE/Q(1) XOR LED_STRETCHER_CB16CE/Q__n0000(12)/LED_STRETCHER_CB16CE/Q__n0000(12)_D <= (LED_STRETCHER_CB16CE/Q(13) AND LED_STRETCHER_CB16CE/Q(10) AND LED_STRETCHER_CB16CE/Q(11) AND LED_STRETCHER_CB16CE/Q(12) AND LED_STRETCHER_CB16CE/Q(2) AND LED_STRETCHER_CB16CE/Q(3) AND LED_STRETCHER_CB16CE/Q(4) AND LED_STRETCHER_CB16CE/Q(5) AND LED_STRETCHER_CB16CE/Q(6) AND LED_STRETCHER_CB16CE/Q(7) AND LED_STRETCHER_CB16CE/Q(8) AND LED_STRETCHER_CB16CE/Q(9)); LED_STRETCHER_CB16CE/Q__n0000(7)/LED_STRETCHER_CB16CE/Q__n0000(7)_D <= LED_STRETCHER_CB16CE/Q(6) XOR LED_STRETCHER_CB16CE/Q__n0000(7)/LED_STRETCHER_CB16CE/Q__n0000(7)_D <= (LED_STRETCHER_CB16CE/Q(13) AND LED_STRETCHER_CB16CE/Q(10) AND LED_STRETCHER_CB16CE/Q(11) AND LED_STRETCHER_CB16CE/Q(12) AND LED_STRETCHER_CB16CE/Q(7) AND LED_STRETCHER_CB16CE/Q(8) AND LED_STRETCHER_CB16CE/Q(9)); LED_STRETCHER_CB16CE/Q__n0000(8)/LED_STRETCHER_CB16CE/Q__n0000(8)_D <= LED_STRETCHER_CB16CE/Q(5) XOR LED_STRETCHER_CB16CE/Q__n0000(8)/LED_STRETCHER_CB16CE/Q__n0000(8)_D <= (LED_STRETCHER_CB16CE/Q(13) AND LED_STRETCHER_CB16CE/Q(10) AND LED_STRETCHER_CB16CE/Q(11) AND LED_STRETCHER_CB16CE/Q(12) AND LED_STRETCHER_CB16CE/Q(6) AND LED_STRETCHER_CB16CE/Q(7) AND LED_STRETCHER_CB16CE/Q(8) AND LED_STRETCHER_CB16CE/Q(9)); LED_STRETCHER_CB16CE/Q__n0000(9)/LED_STRETCHER_CB16CE/Q__n0000(9)_D <= LED_STRETCHER_CB16CE/Q(4) XOR LED_STRETCHER_CB16CE/Q__n0000(9)/LED_STRETCHER_CB16CE/Q__n0000(9)_D <= (LED_STRETCHER_CB16CE/Q(13) AND LED_STRETCHER_CB16CE/Q(10) AND LED_STRETCHER_CB16CE/Q(11) AND LED_STRETCHER_CB16CE/Q(12) AND LED_STRETCHER_CB16CE/Q(5) AND LED_STRETCHER_CB16CE/Q(6) AND LED_STRETCHER_CB16CE/Q(7) AND LED_STRETCHER_CB16CE/Q(8) AND LED_STRETCHER_CB16CE/Q(9)); LED_STRETCHER_CE_int_stdl/LED_STRETCHER_CE_int_stdl_D2 <= ((PAL_ACCESS_inout_stdlv(3)) OR (LED_STRETCHER_CB16CE/Q(13) AND LED_STRETCHER_CB16CE/Q(1) AND LED_STRETCHER_CB16CE/Q(10) AND LED_STRETCHER_CB16CE/Q(11) AND LED_STRETCHER_CB16CE/Q(12) AND LED_STRETCHER_CB16CE/Q(2) AND LED_STRETCHER_CB16CE/Q(3) AND LED_STRETCHER_CB16CE/Q(4) AND LED_STRETCHER_CB16CE/Q(5) AND LED_STRETCHER_CB16CE/Q(6) AND LED_STRETCHER_CB16CE/Q(7) AND LED_STRETCHER_CB16CE/Q(8) AND LED_STRETCHER_CB16CE/Q(9) AND LED_STRETCHER_CB16CE/Q(0))); FTCPE_LOOP_FILTER_REF_inout_stdl: FTCPE port map (LOOP_FILTER_REF_inout_stdl,'1',PAL_BX_CLOCK_in_stdl,LOOP_FILTER_REF_inout_stdl_CLR,'0'); LOOP_FILTER_REF_inout_stdl_CLR <= (NOT VME_SYSRESET_B_in_stdl AND NOT SYSRESET_TMP_1_int_stdl AND NOT SYSRESET_TMP_2_int_stdl AND NOT SYSRESET_TMP_3_int_stdl); N1861/N1861_D2 <= (PAL_ACCESS_inout_stdlv(8) AND NOT PAL_ACCESS_inout_stdlv(10) AND NOT OCB_ADRS_in_stdlv(1) AND NOT OCB_ADRS_in_stdlv(4) AND NOT OCB_ADRS_in_stdlv(2) AND NOT OCB_ADRS_in_stdlv(3)); N1871/N1871_D2 <= (PAL_ACCESS_inout_stdlv(8) AND NOT PAL_ACCESS_inout_stdlv(10) AND OCB_ADRS_in_stdlv(1) AND NOT OCB_ADRS_in_stdlv(4) AND NOT OCB_ADRS_in_stdlv(2) AND NOT OCB_ADRS_in_stdlv(3)); N1881/N1881_D2 <= (PAL_ACCESS_inout_stdlv(8) AND NOT PAL_ACCESS_inout_stdlv(10) AND OCB_ADRS_in_stdlv(1) AND NOT OCB_ADRS_in_stdlv(4) AND NOT OCB_ADRS_in_stdlv(2) AND OCB_ADRS_in_stdlv(3)); NEXT_STATE_QUIESCENT_B_int_stdl <= NOT NEXT_STATE_QUIESCENT_int_stdl; FDCPE_NEXT_STATE_QUIESCENT_int_stdl: FDCPE port map (NEXT_STATE_QUIESCENT_int_stdl,NEXT_STATE_QUIESCENT_int_stdl_D,PAL_BX_CLOCK_in_stdl,'0',NEXT_STATE_QUIESCENT_int_stdl_PRE); NEXT_STATE_QUIESCENT_int_stdl_D <= ((IDLE_STATE_int_stdl.EXP) OR (PAL_ACCESS_inout_stdlv(1) AND NOT SET_QUIESCENT_STATE_int_stdl AND NOT VALID_CYCLE_B_int_stdl) OR (NOT PAL_ACCESS_inout_stdlv(3) AND NOT SET_QUIESCENT_STATE_int_stdl AND NOT IDLE_STATE_int_stdl AND NOT VALID_CYCLE_B_int_stdl) OR (PAL_ACCESS_inout_stdlv(1) AND NOT LATCH_2_STATE_int_stdl AND NOT IO_2_STATE_int_stdl AND NOT SET_QUIESCENT_STATE_int_stdl) OR (NOT LATCH_2_STATE_int_stdl AND NOT IO_2_STATE_int_stdl AND NOT SET_QUIESCENT_STATE_int_stdl AND NOT IDLE_STATE_int_stdl)); NEXT_STATE_QUIESCENT_int_stdl_PRE <= (NOT VME_SYSRESET_B_in_stdl AND NOT SYSRESET_TMP_1_int_stdl AND NOT SYSRESET_TMP_2_int_stdl AND NOT SYSRESET_TMP_3_int_stdl); PAL_ACCESS_inout_stdlv_I(12) <= OCB_ADRS_in_stdlv(1); PAL_ACCESS_inout_stdlv(12) <= PAL_ACCESS_inout_stdlv_I(12) when PAL_ACCESS_inout_stdlv_OE(12) = '1' else 'Z'; PAL_ACCESS_inout_stdlv_OE(12) <= BOARD_CONTROL_1_DATA_int_stdlv(6); OCB_CHIP_SEL_B_int_stdlv(0) <= NOT OCB_CHIP_SEL_int_stdlv(0); OCB_CHIP_SEL_B_int_stdlv(1) <= NOT OCB_CHIP_SEL_int_stdlv(1); FDCPE_OCB_CHIP_SEL_B_out_stdlv0: FDCPE port map (OCB_CHIP_SEL_B_out_stdlv(0),OCB_CHIP_SEL_B_out_stdlv_D(0),PAL_BX_CLOCK_in_stdl,'0',OCB_CHIP_SEL_B_out_stdlv_PRE(0)); OCB_CHIP_SEL_B_out_stdlv_D(0) <= (NOT NEXT_STATE_QUIESCENT_int_stdl AND NOT OCB_CHIP_SEL_B_int_stdlv(0)); OCB_CHIP_SEL_B_out_stdlv_PRE(0) <= (NOT VME_SYSRESET_B_in_stdl AND NOT SYSRESET_TMP_1_int_stdl AND NOT SYSRESET_TMP_2_int_stdl AND NOT SYSRESET_TMP_3_int_stdl); FDCPE_OCB_CHIP_SEL_B_out_stdlv1: FDCPE port map (OCB_CHIP_SEL_B_out_stdlv(1),OCB_CHIP_SEL_B_out_stdlv_D(1),PAL_BX_CLOCK_in_stdl,'0',OCB_CHIP_SEL_B_out_stdlv_PRE(1)); OCB_CHIP_SEL_B_out_stdlv_D(1) <= (NOT NEXT_STATE_QUIESCENT_int_stdl AND NOT OCB_CHIP_SEL_B_int_stdlv(1)); OCB_CHIP_SEL_B_out_stdlv_PRE(1) <= (NOT VME_SYSRESET_B_in_stdl AND NOT SYSRESET_TMP_1_int_stdl AND NOT SYSRESET_TMP_2_int_stdl AND NOT SYSRESET_TMP_3_int_stdl); OCB_CHIP_SEL_int_stdlv(0) <= NOT (((NOT PAL_ACCESS_inout_stdlv(3)) OR (OCB_ADRS_in_stdlv(17)) OR (NOT OCB_ADRS_in_stdlv(15) AND NOT OCB_ADRS_in_stdlv(14) AND NOT OCB_ADRS_in_stdlv(13) AND NOT OCB_ADRS_in_stdlv(6) AND NOT OCB_ADRS_in_stdlv(5) AND NOT OCB_ADRS_in_stdlv(10) AND NOT OCB_ADRS_in_stdlv(9) AND NOT OCB_ADRS_in_stdlv(16) AND NOT OCB_ADRS_in_stdlv(12) AND NOT OCB_ADRS_in_stdlv(8) AND NOT OCB_ADRS_in_stdlv(7) AND NOT OCB_ADRS_in_stdlv(11)))); OCB_CHIP_SEL_int_stdlv(1) <= NOT (((NOT PAL_ACCESS_inout_stdlv(3)) OR (NOT OCB_ADRS_in_stdlv(17)) OR (NOT OCB_ADRS_in_stdlv(15) AND NOT OCB_ADRS_in_stdlv(14) AND NOT OCB_ADRS_in_stdlv(13) AND NOT OCB_ADRS_in_stdlv(6) AND NOT OCB_ADRS_in_stdlv(5) AND NOT OCB_ADRS_in_stdlv(10) AND NOT OCB_ADRS_in_stdlv(9) AND NOT OCB_ADRS_in_stdlv(16) AND NOT OCB_ADRS_in_stdlv(12) AND NOT OCB_ADRS_in_stdlv(8) AND NOT OCB_ADRS_in_stdlv(7) AND NOT OCB_ADRS_in_stdlv(11)))); PAL_ACCESS_inout_stdlv_I(8) <= (PAL_ACCESS_inout_stdlv(3) AND NOT OCB_ADRS_in_stdlv(17) AND NOT OCB_ADRS_in_stdlv(15) AND NOT OCB_ADRS_in_stdlv(14) AND NOT OCB_ADRS_in_stdlv(13) AND NOT OCB_ADRS_in_stdlv(6) AND NOT OCB_ADRS_in_stdlv(5) AND NOT OCB_ADRS_in_stdlv(10) AND NOT OCB_ADRS_in_stdlv(9) AND NOT OCB_ADRS_in_stdlv(16) AND NOT OCB_ADRS_in_stdlv(12) AND NOT OCB_ADRS_in_stdlv(8) AND NOT OCB_ADRS_in_stdlv(7) AND NOT OCB_ADRS_in_stdlv(11)); PAL_ACCESS_inout_stdlv(8) <= PAL_ACCESS_inout_stdlv_I(8) when PAL_ACCESS_inout_stdlv_OE(8) = '1' else 'Z'; PAL_ACCESS_inout_stdlv_OE(8) <= BOARD_CONTROL_1_DATA_int_stdlv(6); FDCPE_PAL_ACCESS_inout_stdlv7: FDCPE port map (PAL_ACCESS_inout_stdlv_I(7),PAL_ACCESS_inout_stdlv(7),PAL_BX_CLOCK_in_stdl,'0',PAL_ACCESS_inout_stdlv_PRE(7)); PAL_ACCESS_inout_stdlv(7) <= ((EXP10_.EXP) OR (NOT LTCHD_WRITE_B_in_stdl AND NOT LATCH_2_STATE_int_stdl AND NOT LATCH_1_STATE_int_stdl AND NOT NEXT_STATE_QUIESCENT_int_stdl) OR (NOT PAL_ACCESS_inout_stdlv(3) AND NOT LATCH_2_STATE_int_stdl AND NOT LATCH_1_STATE_int_stdl AND NOT NEXT_STATE_QUIESCENT_int_stdl) OR (NOT PAL_ACCESS_inout_stdlv(3) AND NOT LATCH_1_STATE_int_stdl AND NOT NEXT_STATE_QUIESCENT_int_stdl AND NOT VALID_CYCLE_B_int_stdl)); PAL_ACCESS_inout_stdlv_PRE(7) <= (NOT VME_SYSRESET_B_in_stdl AND NOT SYSRESET_TMP_1_int_stdl AND NOT SYSRESET_TMP_2_int_stdl AND NOT SYSRESET_TMP_3_int_stdl); PAL_ACCESS_inout_stdlv(7) <= PAL_ACCESS_inout_stdlv_I(7) when PAL_ACCESS_inout_stdlv_OE(7) = '1' else 'Z'; PAL_ACCESS_inout_stdlv_OE(7) <= BOARD_CONTROL_1_DATA_int_stdlv(6); FDCPE_OCB_DIRECTION_out_stdl: FDCPE port map (OCB_DIRECTION_out_stdl,OCB_DIRECTION_out_stdl_D,PAL_BX_CLOCK_in_stdl,'0',OCB_DIRECTION_out_stdl_PRE); OCB_DIRECTION_out_stdl_D <= ((NOT LTCHD_WRITE_B_in_stdl AND NOT LATCH_2_STATE_int_stdl AND NOT LATCH_1_STATE_int_stdl AND NOT NEXT_STATE_QUIESCENT_int_stdl) OR (NOT LTCHD_WRITE_B_in_stdl AND NOT LATCH_1_STATE_int_stdl AND NOT NEXT_STATE_QUIESCENT_int_stdl AND NOT VALID_CYCLE_B_int_stdl) OR (NOT PAL_ACCESS_inout_stdlv(3) AND NOT LATCH_2_STATE_int_stdl AND NOT LATCH_1_STATE_int_stdl AND NOT NEXT_STATE_QUIESCENT_int_stdl) OR (NOT PAL_ACCESS_inout_stdlv(3) AND NOT LATCH_1_STATE_int_stdl AND NOT NEXT_STATE_QUIESCENT_int_stdl AND NOT VALID_CYCLE_B_int_stdl)); OCB_DIRECTION_out_stdl_PRE <= (NOT VME_SYSRESET_B_in_stdl AND NOT SYSRESET_TMP_1_int_stdl AND NOT SYSRESET_TMP_2_int_stdl AND NOT SYSRESET_TMP_3_int_stdl); FDCPE_PAL_ACCESS_inout_stdlv10: FDCPE port map (PAL_ACCESS_inout_stdlv_I(10),PAL_ACCESS_inout_stdlv(10),PAL_BX_CLOCK_in_stdl,'0',PAL_ACCESS_inout_stdlv_PRE(10)); PAL_ACCESS_inout_stdlv(10) <= ((NOT LTCHD_WRITE_B_in_stdl AND PAL_ACCESS_inout_stdlv(8) AND LATCH_2_STATE_int_stdl AND NOT NEXT_STATE_QUIESCENT_int_stdl) OR (NOT LTCHD_WRITE_B_in_stdl AND LATCH_2_STATE_int_stdl AND NOT NEXT_STATE_QUIESCENT_int_stdl AND OCB_CHIP_SEL_int_stdlv(1)) OR (NOT LTCHD_WRITE_B_in_stdl AND LATCH_2_STATE_int_stdl AND NOT NEXT_STATE_QUIESCENT_int_stdl AND OCB_CHIP_SEL_int_stdlv(0))); PAL_ACCESS_inout_stdlv_PRE(10) <= (NOT VME_SYSRESET_B_in_stdl AND NOT SYSRESET_TMP_1_int_stdl AND NOT SYSRESET_TMP_2_int_stdl AND NOT SYSRESET_TMP_3_int_stdl); PAL_ACCESS_inout_stdlv(10) <= PAL_ACCESS_inout_stdlv_I(10) when PAL_ACCESS_inout_stdlv_OE(10) = '1' else 'Z'; PAL_ACCESS_inout_stdlv_OE(10) <= BOARD_CONTROL_1_DATA_int_stdlv(6); FDCPE_OCB_WRITE_STRB_B_inout_stdl: FDCPE port map (OCB_WRITE_STRB_B_inout_stdl,OCB_WRITE_STRB_B_inout_stdl_D,PAL_BX_CLOCK_in_stdl,'0',OCB_WRITE_STRB_B_inout_stdl_PRE); OCB_WRITE_STRB_B_inout_stdl_D <= ((NOT LTCHD_WRITE_B_in_stdl AND PAL_ACCESS_inout_stdlv(8) AND LATCH_2_STATE_int_stdl AND NOT NEXT_STATE_QUIESCENT_int_stdl) OR (NOT LTCHD_WRITE_B_in_stdl AND LATCH_2_STATE_int_stdl AND NOT NEXT_STATE_QUIESCENT_int_stdl AND OCB_CHIP_SEL_int_stdlv(1)) OR (NOT LTCHD_WRITE_B_in_stdl AND LATCH_2_STATE_int_stdl AND NOT NEXT_STATE_QUIESCENT_int_stdl AND OCB_CHIP_SEL_int_stdlv(0))); OCB_WRITE_STRB_B_inout_stdl_PRE <= (NOT VME_SYSRESET_B_in_stdl AND NOT SYSRESET_TMP_1_int_stdl AND NOT SYSRESET_TMP_2_int_stdl AND NOT SYSRESET_TMP_3_int_stdl); FDCPE_PAL_ACCESS_inout_stdlv1: FDCPE port map (PAL_ACCESS_inout_stdlv_I(1),DS1_tmp_int_stdl,NOT PAL_BX_CLOCK_in_stdl,'0','0'); PAL_ACCESS_inout_stdlv(1) <= PAL_ACCESS_inout_stdlv_I(1) when PAL_ACCESS_inout_stdlv_OE(1) = '1' else 'Z'; PAL_ACCESS_inout_stdlv_OE(1) <= BOARD_CONTROL_1_DATA_int_stdlv(6); PAL_ACCESS_inout_stdlv_I(11) <= OCB_DATA_inout_stdlv(0).PIN; PAL_ACCESS_inout_stdlv(11) <= PAL_ACCESS_inout_stdlv_I(11) when PAL_ACCESS_inout_stdlv_OE(11) = '1' else 'Z'; PAL_ACCESS_inout_stdlv_OE(11) <= BOARD_CONTROL_1_DATA_int_stdlv(6); PAL_ACCESS_inout_stdlv_I(14) <= (PAL_ACCESS_inout_stdlv(8) AND NOT OCB_ADRS_in_stdlv(1) AND NOT OCB_ADRS_in_stdlv(4) AND NOT OCB_ADRS_in_stdlv(2) AND NOT OCB_ADRS_in_stdlv(3)); PAL_ACCESS_inout_stdlv(14) <= PAL_ACCESS_inout_stdlv_I(14) when PAL_ACCESS_inout_stdlv_OE(14) = '1' else 'Z'; PAL_ACCESS_inout_stdlv_OE(14) <= BOARD_CONTROL_1_DATA_int_stdlv(6); FDCPE_PAL_ACCESS_inout_stdlv9: FDCPE port map (PAL_ACCESS_inout_stdlv_I(9),PAL_ACCESS_inout_stdlv(9),PAL_BX_CLOCK_in_stdl,PAL_ACCESS_inout_stdlv_CLR(9),'0'); PAL_ACCESS_inout_stdlv(9) <= (LTCHD_WRITE_B_in_stdl AND PAL_ACCESS_inout_stdlv(8) AND NEXT_STATE_QUIESCENT_B_int_stdl); PAL_ACCESS_inout_stdlv_CLR(9) <= (NOT VME_SYSRESET_B_in_stdl AND NOT SYSRESET_TMP_1_int_stdl AND NOT SYSRESET_TMP_2_int_stdl AND NOT SYSRESET_TMP_3_int_stdl); PAL_ACCESS_inout_stdlv(9) <= PAL_ACCESS_inout_stdlv_I(9) when PAL_ACCESS_inout_stdlv_OE(9) = '1' else 'Z'; PAL_ACCESS_inout_stdlv_OE(9) <= BOARD_CONTROL_1_DATA_int_stdlv(6); PAL_ACCESS_inout_stdlv_I(0) <= PAL_BX_CLOCK_in_stdl; PAL_ACCESS_inout_stdlv(0) <= PAL_ACCESS_inout_stdlv_I(0) when PAL_ACCESS_inout_stdlv_OE(0) = '1' else 'Z'; PAL_ACCESS_inout_stdlv_OE(0) <= BOARD_CONTROL_1_DATA_int_stdlv(6); FDCPE_PAL_FIRST_X8_EDGE_out_stdl: FDCPE port map (PAL_FIRST_X8_EDGE_out_stdl,PAL_FIRST_X8_EDGE_out_stdl_D,PAL_BX_X8_CLOCK_in_stdl,PAL_FIRST_X8_EDGE_out_stdl_CLR,'0'); PAL_FIRST_X8_EDGE_out_stdl_D <= (NOT CNT_BIT_VAL_4_inout_stdl AND CNT_BIT_VAL_1_int_stdl AND NOT CNT_BIT_VAL_2_int_stdl); PAL_FIRST_X8_EDGE_out_stdl_CLR <= (NOT VME_SYSRESET_B_in_stdl AND NOT SYSRESET_TMP_1_int_stdl AND NOT SYSRESET_TMP_2_int_stdl AND NOT SYSRESET_TMP_3_int_stdl); PHASE_DET_OUT_out_stdl <= RCVD_BX_CLOCK_inout_stdl XOR PHASE_DET_OUT_out_stdl <= LOOP_FILTER_REF_inout_stdl; FDCPE_OCB_DATA_inout_stdlv0: FDCPE port map (OCB_DATA_inout_stdlv_I(0),OCB_DATA_inout_stdlv(0),PAL_BX_CLOCK_in_stdl,'0',OCB_DATA_inout_stdlv_PRE(0)); OCB_DATA_inout_stdlv(0) <= ((IO_2_STATE_int_stdl.EXP) OR (PAL_ACCESS_inout_stdlv(8) AND OCB_ADRS_in_stdlv(1) AND NOT OCB_ADRS_in_stdlv(4) AND OCB_ADRS_in_stdlv(2) AND OCB_ADRS_in_stdlv(3) AND CNFG_INIT_B_in_stdlv(0)) OR (PAL_ACCESS_inout_stdlv(8) AND OCB_ADRS_in_stdlv(1) AND NOT OCB_ADRS_in_stdlv(4) AND OCB_ADRS_in_stdlv(2) AND NOT OCB_ADRS_in_stdlv(3) AND CRATE_STATUS_B_in_stdlv(0)) OR (PAL_ACCESS_inout_stdlv(8) AND NOT OCB_ADRS_in_stdlv(1) AND NOT OCB_ADRS_in_stdlv(4) AND OCB_ADRS_in_stdlv(2) AND NOT OCB_ADRS_in_stdlv(3) AND FPGA_0_STATUS_in_stdlv(0))); OCB_DATA_inout_stdlv_PRE(0) <= (NOT VME_SYSRESET_B_in_stdl AND NOT SYSRESET_TMP_1_int_stdl AND NOT SYSRESET_TMP_2_int_stdl AND NOT SYSRESET_TMP_3_int_stdl); OCB_DATA_inout_stdlv(0) <= OCB_DATA_inout_stdlv_I(0) when OCB_DATA_inout_stdlv_OE(0) = '1' else 'Z'; OCB_DATA_inout_stdlv_OE(0) <= PAL_ACCESS_inout_stdlv(9); FDCPE_OCB_DATA_inout_stdlv1: FDCPE port map (OCB_DATA_inout_stdlv_I(1),OCB_DATA_inout_stdlv(1),PAL_BX_CLOCK_in_stdl,'0',OCB_DATA_inout_stdlv_PRE(1)); OCB_DATA_inout_stdlv(1) <= ((LATCH_2_STATE_int_stdl.EXP) OR (LATCH_1_STATE_int_stdl.EXP) OR (PAL_ACCESS_inout_stdlv(8) AND OCB_ADRS_in_stdlv(1) AND NOT OCB_ADRS_in_stdlv(4) AND OCB_ADRS_in_stdlv(2) AND OCB_ADRS_in_stdlv(3) AND CNFG_INIT_B_in_stdlv(1)) OR (PAL_ACCESS_inout_stdlv(8) AND OCB_ADRS_in_stdlv(1) AND NOT OCB_ADRS_in_stdlv(4) AND OCB_ADRS_in_stdlv(2) AND NOT OCB_ADRS_in_stdlv(3) AND CRATE_STATUS_B_in_stdlv(1)) OR (PAL_ACCESS_inout_stdlv(8) AND NOT OCB_ADRS_in_stdlv(1) AND NOT OCB_ADRS_in_stdlv(4) AND OCB_ADRS_in_stdlv(2) AND NOT OCB_ADRS_in_stdlv(3) AND FPGA_0_STATUS_in_stdlv(1))); OCB_DATA_inout_stdlv_PRE(1) <= (NOT VME_SYSRESET_B_in_stdl AND NOT SYSRESET_TMP_1_int_stdl AND NOT SYSRESET_TMP_2_int_stdl AND NOT SYSRESET_TMP_3_int_stdl); OCB_DATA_inout_stdlv(1) <= OCB_DATA_inout_stdlv_I(1) when OCB_DATA_inout_stdlv_OE(1) = '1' else 'Z'; OCB_DATA_inout_stdlv_OE(1) <= PAL_ACCESS_inout_stdlv(9); FDCPE_OCB_DATA_inout_stdlv2: FDCPE port map (OCB_DATA_inout_stdlv_I(2),OCB_DATA_inout_stdlv(2),PAL_BX_CLOCK_in_stdl,'0',OCB_DATA_inout_stdlv_PRE(2)); OCB_DATA_inout_stdlv(2) <= ((EXP11_.EXP) OR (EXP12_.EXP) OR (PAL_ACCESS_inout_stdlv(8) AND OCB_ADRS_in_stdlv(1) AND NOT OCB_ADRS_in_stdlv(4) AND OCB_ADRS_in_stdlv(2) AND OCB_ADRS_in_stdlv(3) AND CNFG_BUSY_in_stdlv(0)) OR (PAL_ACCESS_inout_stdlv(8) AND OCB_ADRS_in_stdlv(1) AND NOT OCB_ADRS_in_stdlv(4) AND OCB_ADRS_in_stdlv(2) AND NOT OCB_ADRS_in_stdlv(3) AND CRATE_STATUS_B_in_stdlv(2)) OR (PAL_ACCESS_inout_stdlv(8) AND NOT OCB_ADRS_in_stdlv(1) AND NOT OCB_ADRS_in_stdlv(4) AND OCB_ADRS_in_stdlv(2) AND NOT OCB_ADRS_in_stdlv(3) AND FPGA_0_STATUS_in_stdlv(2))); OCB_DATA_inout_stdlv_PRE(2) <= (NOT VME_SYSRESET_B_in_stdl AND NOT SYSRESET_TMP_1_int_stdl AND NOT SYSRESET_TMP_2_int_stdl AND NOT SYSRESET_TMP_3_int_stdl); OCB_DATA_inout_stdlv(2) <= OCB_DATA_inout_stdlv_I(2) when OCB_DATA_inout_stdlv_OE(2) = '1' else 'Z'; OCB_DATA_inout_stdlv_OE(2) <= PAL_ACCESS_inout_stdlv(9); FDCPE_OCB_DATA_inout_stdlv3: FDCPE port map (OCB_DATA_inout_stdlv_I(3),OCB_DATA_inout_stdlv(3),PAL_BX_CLOCK_in_stdl,'0',OCB_DATA_inout_stdlv_PRE(3)); OCB_DATA_inout_stdlv(3) <= (NOT _n0105/_n0105_D2 AND NOT _n0106/_n0106_D2 AND NOT _n0107/_n0107_D2 AND NOT _n0104/_n0104_D2 AND NOT _n0109/_n0109_D2 AND NOT _n0108/_n0108_D2); OCB_DATA_inout_stdlv_PRE(3) <= (NOT VME_SYSRESET_B_in_stdl AND NOT SYSRESET_TMP_1_int_stdl AND NOT SYSRESET_TMP_2_int_stdl AND NOT SYSRESET_TMP_3_int_stdl); OCB_DATA_inout_stdlv(3) <= OCB_DATA_inout_stdlv_I(3) when OCB_DATA_inout_stdlv_OE(3) = '1' else 'Z'; OCB_DATA_inout_stdlv_OE(3) <= PAL_ACCESS_inout_stdlv(9); FDCPE_OCB_DATA_inout_stdlv4: FDCPE port map (OCB_DATA_inout_stdlv_I(4),OCB_DATA_inout_stdlv(4),PAL_BX_CLOCK_in_stdl,'0',OCB_DATA_inout_stdlv_PRE(4)); OCB_DATA_inout_stdlv(4) <= (NOT _n0111/_n0111_D2 AND NOT _n0112/_n0112_D2 AND NOT _n0113/_n0113_D2 AND NOT _n0110/_n0110_D2 AND NOT _n0115/_n0115_D2 AND NOT _n0114/_n0114_D2); OCB_DATA_inout_stdlv_PRE(4) <= (NOT VME_SYSRESET_B_in_stdl AND NOT SYSRESET_TMP_1_int_stdl AND NOT SYSRESET_TMP_2_int_stdl AND NOT SYSRESET_TMP_3_int_stdl); OCB_DATA_inout_stdlv(4) <= OCB_DATA_inout_stdlv_I(4) when OCB_DATA_inout_stdlv_OE(4) = '1' else 'Z'; OCB_DATA_inout_stdlv_OE(4) <= PAL_ACCESS_inout_stdlv(9); FDCPE_OCB_DATA_inout_stdlv5: FDCPE port map (OCB_DATA_inout_stdlv_I(5),OCB_DATA_inout_stdlv(5),PAL_BX_CLOCK_in_stdl,'0',OCB_DATA_inout_stdlv_PRE(5)); OCB_DATA_inout_stdlv(5) <= ((LED_STRETCHER_CB16CE/Q(13).EXP) OR (PAL_ACCESS_inout_stdlv(8) AND BOARD_CONTROL_1_DATA_int_stdlv(5) AND NOT OCB_ADRS_in_stdlv(1) AND NOT OCB_ADRS_in_stdlv(4) AND NOT OCB_ADRS_in_stdlv(2) AND NOT OCB_ADRS_in_stdlv(3)) OR (PAL_ACCESS_inout_stdlv(8) AND OCB_ADRS_in_stdlv(1) AND NOT OCB_ADRS_in_stdlv(4) AND OCB_ADRS_in_stdlv(2) AND OCB_ADRS_in_stdlv(3) AND CNFG_DONE_in_stdlv(1)) OR (PAL_ACCESS_inout_stdlv(8) AND NOT OCB_ADRS_in_stdlv(1) AND NOT OCB_ADRS_in_stdlv(4) AND OCB_ADRS_in_stdlv(2) AND NOT OCB_ADRS_in_stdlv(3) AND FPGA_1_STATUS_in_stdlv(1))); OCB_DATA_inout_stdlv_PRE(5) <= (NOT VME_SYSRESET_B_in_stdl AND NOT SYSRESET_TMP_1_int_stdl AND NOT SYSRESET_TMP_2_int_stdl AND NOT SYSRESET_TMP_3_int_stdl); OCB_DATA_inout_stdlv(5) <= OCB_DATA_inout_stdlv_I(5) when OCB_DATA_inout_stdlv_OE(5) = '1' else 'Z'; OCB_DATA_inout_stdlv_OE(5) <= PAL_ACCESS_inout_stdlv(9); FDCPE_OCB_DATA_inout_stdlv6: FDCPE port map (OCB_DATA_inout_stdlv_I(6),OCB_DATA_inout_stdlv(6),PAL_BX_CLOCK_in_stdl,'0',OCB_DATA_inout_stdlv_PRE(6)); OCB_DATA_inout_stdlv(6) <= ((PAL_ACCESS_inout_stdlv(8) AND BOARD_CONTROL_1_DATA_int_stdlv(6) AND NOT OCB_ADRS_in_stdlv(1) AND NOT OCB_ADRS_in_stdlv(4) AND NOT OCB_ADRS_in_stdlv(2) AND NOT OCB_ADRS_in_stdlv(3)) OR (PAL_ACCESS_inout_stdlv(8) AND BOARD_CONTROL_2_DATA_int_stdlv(6) AND OCB_ADRS_in_stdlv(1) AND NOT OCB_ADRS_in_stdlv(4) AND NOT OCB_ADRS_in_stdlv(2) AND NOT OCB_ADRS_in_stdlv(3)) OR (PAL_ACCESS_inout_stdlv(8) AND NOT OCB_ADRS_in_stdlv(1) AND NOT OCB_ADRS_in_stdlv(4) AND OCB_ADRS_in_stdlv(2) AND NOT OCB_ADRS_in_stdlv(3) AND FPGA_1_STATUS_in_stdlv(2))); OCB_DATA_inout_stdlv_PRE(6) <= (NOT VME_SYSRESET_B_in_stdl AND NOT SYSRESET_TMP_1_int_stdl AND NOT SYSRESET_TMP_2_int_stdl AND NOT SYSRESET_TMP_3_int_stdl); OCB_DATA_inout_stdlv(6) <= OCB_DATA_inout_stdlv_I(6) when OCB_DATA_inout_stdlv_OE(6) = '1' else 'Z'; OCB_DATA_inout_stdlv_OE(6) <= PAL_ACCESS_inout_stdlv(9); FDCPE_OCB_DATA_inout_stdlv7: FDCPE port map (OCB_DATA_inout_stdlv_I(7),OCB_DATA_inout_stdlv(7),PAL_BX_CLOCK_in_stdl,'0',OCB_DATA_inout_stdlv_PRE(7)); OCB_DATA_inout_stdlv(7) <= ((PAL_ACCESS_inout_stdlv(8) AND ADC_ENABLE_reg_stdl AND NOT OCB_ADRS_in_stdlv(1) AND NOT OCB_ADRS_in_stdlv(4) AND NOT OCB_ADRS_in_stdlv(2) AND NOT OCB_ADRS_in_stdlv(3)) OR (PAL_ACCESS_inout_stdlv(8) AND NOT OCB_ADRS_in_stdlv(1) AND NOT OCB_ADRS_in_stdlv(4) AND OCB_ADRS_in_stdlv(2) AND NOT OCB_ADRS_in_stdlv(3) AND FPGA_1_STATUS_in_stdlv(3))); OCB_DATA_inout_stdlv_PRE(7) <= (NOT VME_SYSRESET_B_in_stdl AND NOT SYSRESET_TMP_1_int_stdl AND NOT SYSRESET_TMP_2_int_stdl AND NOT SYSRESET_TMP_3_int_stdl); OCB_DATA_inout_stdlv(7) <= OCB_DATA_inout_stdlv_I(7) when OCB_DATA_inout_stdlv_OE(7) = '1' else 'Z'; OCB_DATA_inout_stdlv_OE(7) <= PAL_ACCESS_inout_stdlv(9); FTCPE_RCVD_BX_CLOCK_inout_stdl: FTCPE port map (RCVD_BX_CLOCK_inout_stdl,'1',PAL_BX_CLOCK_in_stdl,RCVD_BX_CLOCK_inout_stdl_CLR,'0'); RCVD_BX_CLOCK_inout_stdl_CLR <= (NOT VME_SYSRESET_B_in_stdl AND NOT SYSRESET_TMP_1_int_stdl AND NOT SYSRESET_TMP_2_int_stdl AND NOT SYSRESET_TMP_3_int_stdl); FDCPE_SER_DC_BALANCE_reg_stdl: FDCPE port map (SER_DC_BALANCE_reg_stdl,SER_DC_BALANCE_reg_stdl_D,PAL_BX_CLOCK_in_stdl,SER_DC_BALANCE_reg_stdl_CLR,'0'); SER_DC_BALANCE_reg_stdl_D <= ((SER_DC_BALANCE_reg_stdl AND NOT N1861/N1861_D2) OR (PAL_ACCESS_inout_stdlv(8) AND NOT PAL_ACCESS_inout_stdlv(10) AND PAL_ACCESS_inout_stdlv(13) AND NOT OCB_ADRS_in_stdlv(1) AND NOT OCB_ADRS_in_stdlv(4) AND NOT OCB_ADRS_in_stdlv(2) AND OCB_DATA_inout_stdlv(1).PIN AND NOT OCB_ADRS_in_stdlv(3))); SER_DC_BALANCE_reg_stdl_CLR <= (NOT VME_SYSRESET_B_in_stdl AND NOT SYSRESET_TMP_1_int_stdl AND NOT SYSRESET_TMP_2_int_stdl AND NOT SYSRESET_TMP_3_int_stdl); FDCPE_SER_DESKEW_B_reg_stdl: FDCPE port map (SER_DESKEW_B_reg_stdl,SER_DESKEW_B_reg_stdl_D,PAL_BX_CLOCK_in_stdl,'0',SER_DESKEW_B_reg_stdl_PRE); SER_DESKEW_B_reg_stdl_D <= ((SER_DESKEW_B_reg_stdl AND NOT N1861/N1861_D2) OR (PAL_ACCESS_inout_stdlv(8) AND NOT PAL_ACCESS_inout_stdlv(10) AND PAL_ACCESS_inout_stdlv(13) AND NOT OCB_ADRS_in_stdlv(1) AND NOT OCB_ADRS_in_stdlv(4) AND NOT OCB_ADRS_in_stdlv(2) AND OCB_DATA_inout_stdlv(0).PIN AND NOT OCB_ADRS_in_stdlv(3))); SER_DESKEW_B_reg_stdl_PRE <= (NOT VME_SYSRESET_B_in_stdl AND NOT SYSRESET_TMP_1_int_stdl AND NOT SYSRESET_TMP_2_int_stdl AND NOT SYSRESET_TMP_3_int_stdl); FDCPE_PAL_ACCESS_inout_stdlv15: FDCPE port map (PAL_ACCESS_inout_stdlv_I(15),PAL_ACCESS_inout_stdlv(15),PAL_BX_CLOCK_in_stdl,'0',PAL_ACCESS_inout_stdlv_PRE(15)); PAL_ACCESS_inout_stdlv(15) <= ((SER_DESKEW_B_reg_stdl AND NOT N1861/N1861_D2) OR (PAL_ACCESS_inout_stdlv(8) AND NOT PAL_ACCESS_inout_stdlv(10) AND PAL_ACCESS_inout_stdlv(13) AND NOT OCB_ADRS_in_stdlv(1) AND NOT OCB_ADRS_in_stdlv(4) AND NOT OCB_ADRS_in_stdlv(2) AND OCB_DATA_inout_stdlv(0).PIN AND NOT OCB_ADRS_in_stdlv(3))); PAL_ACCESS_inout_stdlv_PRE(15) <= (NOT VME_SYSRESET_B_in_stdl AND NOT SYSRESET_TMP_1_int_stdl AND NOT SYSRESET_TMP_2_int_stdl AND NOT SYSRESET_TMP_3_int_stdl); PAL_ACCESS_inout_stdlv(15) <= PAL_ACCESS_inout_stdlv_I(15) when PAL_ACCESS_inout_stdlv_OE(15) = '1' else 'Z'; PAL_ACCESS_inout_stdlv_OE(15) <= BOARD_CONTROL_1_DATA_int_stdlv(6); FDCPE_SET_QUIESCENT_STATE_int_stdl: FDCPE port map (SET_QUIESCENT_STATE_int_stdl,SET_QUIESCENT_STATE_int_stdl_D,PAL_BX_CLOCK_in_stdl,SET_QUIESCENT_STATE_int_stdl_CLR,'0'); SET_QUIESCENT_STATE_int_stdl_D <= (NOT PAL_ACCESS_inout_stdlv(1) AND NOT LATCH_2_STATE_int_stdl AND IO_2_STATE_int_stdl AND NOT IO_1_STATE_int_stdl AND NOT LATCH_1_STATE_int_stdl AND NOT SET_QUIESCENT_STATE_int_stdl AND NOT IDLE_STATE_int_stdl); SET_QUIESCENT_STATE_int_stdl_CLR <= (NOT VME_SYSRESET_B_in_stdl AND NOT SYSRESET_TMP_1_int_stdl AND NOT SYSRESET_TMP_2_int_stdl AND NOT SYSRESET_TMP_3_int_stdl); FDCPE_SYSRESET_TMP_1_int_stdl: FDCPE port map (SYSRESET_TMP_1_int_stdl,VME_SYSRESET_B_in_stdl,PAL_BX_CLOCK_in_stdl,'0','0'); FDCPE_SYSRESET_TMP_2_int_stdl: FDCPE port map (SYSRESET_TMP_2_int_stdl,SYSRESET_TMP_1_int_stdl,PAL_BX_CLOCK_in_stdl,'0','0'); FDCPE_SYSRESET_TMP_3_int_stdl: FDCPE port map (SYSRESET_TMP_3_int_stdl,SYSRESET_TMP_2_int_stdl,PAL_BX_CLOCK_in_stdl,'0','0'); VALID_CYCLE_B_int_stdl <= NOT PAL_ACCESS_inout_stdlv(3); PAL_ACCESS_inout_stdlv_I(3) <= ((PAL_ACCESS_int_stdlv(1).EXP) OR (CNT_BIT_VAL_4_inout_stdl_OBUF.EXP) OR (NOT LTCHD_IACK_B_in_stdl AND LTCHD_AM_in_stdlv(5) AND LTCHD_AM_in_stdlv(4) AND NOT LTCHD_AM_in_stdlv(1) AND LTCHD_AM_in_stdlv(3) AND LTCHD_AM_in_stdlv(0) AND NOT OCB_ADRS_in_stdlv(23) AND VME_GEO_B_in_stdlv(0) AND NOT OCB_ADRS_in_stdlv(18) AND VME_GEO_B_in_stdlv(1) AND NOT OCB_ADRS_in_stdlv(19) AND VME_GEO_B_in_stdlv(2) AND NOT OCB_ADRS_in_stdlv(20) AND _n0142/_n0142_D AND _n0145/_n0145_D) OR (NOT LTCHD_IACK_B_in_stdl AND LTCHD_AM_in_stdlv(5) AND LTCHD_AM_in_stdlv(4) AND NOT LTCHD_AM_in_stdlv(1) AND LTCHD_AM_in_stdlv(3) AND LTCHD_AM_in_stdlv(0) AND NOT OCB_ADRS_in_stdlv(23) AND VME_GEO_B_in_stdlv(0) AND NOT OCB_ADRS_in_stdlv(18) AND NOT VME_GEO_B_in_stdlv(1) AND OCB_ADRS_in_stdlv(19) AND VME_GEO_B_in_stdlv(2) AND NOT OCB_ADRS_in_stdlv(20) AND _n0142/_n0142_D AND _n0145/_n0145_D) OR (NOT LTCHD_IACK_B_in_stdl AND LTCHD_AM_in_stdlv(5) AND LTCHD_AM_in_stdlv(4) AND NOT LTCHD_AM_in_stdlv(1) AND LTCHD_AM_in_stdlv(3) AND LTCHD_AM_in_stdlv(0) AND NOT OCB_ADRS_in_stdlv(23) AND NOT VME_GEO_B_in_stdlv(0) AND OCB_ADRS_in_stdlv(18) AND VME_GEO_B_in_stdlv(1) AND NOT OCB_ADRS_in_stdlv(19) AND VME_GEO_B_in_stdlv(2) AND NOT OCB_ADRS_in_stdlv(20) AND _n0142/_n0142_D AND _n0145/_n0145_D) OR (NOT LTCHD_IACK_B_in_stdl AND LTCHD_AM_in_stdlv(5) AND LTCHD_AM_in_stdlv(4) AND NOT LTCHD_AM_in_stdlv(1) AND LTCHD_AM_in_stdlv(3) AND LTCHD_AM_in_stdlv(0) AND NOT OCB_ADRS_in_stdlv(23) AND NOT VME_GEO_B_in_stdlv(0) AND OCB_ADRS_in_stdlv(18) AND NOT VME_GEO_B_in_stdlv(1) AND OCB_ADRS_in_stdlv(19) AND VME_GEO_B_in_stdlv(2) AND NOT OCB_ADRS_in_stdlv(20) AND _n0142/_n0142_D AND _n0145/_n0145_D)); PAL_ACCESS_inout_stdlv(3) <= PAL_ACCESS_inout_stdlv_I(3) when PAL_ACCESS_inout_stdlv_OE(3) = '1' else 'Z'; PAL_ACCESS_inout_stdlv_OE(3) <= BOARD_CONTROL_1_DATA_int_stdlv(6); FDCPE_VME_LTCH_CLK_out_stdl: FDCPE port map (VME_LTCH_CLK_out_stdl,VME_LTCH_CLK_out_stdl_D,PAL_BX_CLOCK_in_stdl,VME_LTCH_CLK_out_stdl_CLR,'0'); VME_LTCH_CLK_out_stdl_D <= (PAL_ACCESS_inout_stdlv(1) AND IDLE_STATE_int_stdl); VME_LTCH_CLK_out_stdl_CLR <= (NOT VME_SYSRESET_B_in_stdl AND NOT SYSRESET_TMP_1_int_stdl AND NOT SYSRESET_TMP_2_int_stdl AND NOT SYSRESET_TMP_3_int_stdl); FDCPE_PAL_ACCESS_inout_stdlv4: FDCPE port map (PAL_ACCESS_inout_stdlv_I(4),PAL_ACCESS_inout_stdlv(4),PAL_BX_CLOCK_in_stdl,PAL_ACCESS_inout_stdlv_CLR(4),'0'); PAL_ACCESS_inout_stdlv(4) <= (PAL_ACCESS_inout_stdlv(1) AND IDLE_STATE_int_stdl); PAL_ACCESS_inout_stdlv_CLR(4) <= (NOT VME_SYSRESET_B_in_stdl AND NOT SYSRESET_TMP_1_int_stdl AND NOT SYSRESET_TMP_2_int_stdl AND NOT SYSRESET_TMP_3_int_stdl); PAL_ACCESS_inout_stdlv(4) <= PAL_ACCESS_inout_stdlv_I(4) when PAL_ACCESS_inout_stdlv_OE(4) = '1' else 'Z'; PAL_ACCESS_inout_stdlv_OE(4) <= BOARD_CONTROL_1_DATA_int_stdlv(6); PAL_ACCESS_inout_stdlv_I(13) <= (NOT LTCHD_WRITE_B_in_stdl AND PAL_ACCESS_inout_stdlv(8)); PAL_ACCESS_inout_stdlv(13) <= PAL_ACCESS_inout_stdlv_I(13) when PAL_ACCESS_inout_stdlv_OE(13) = '1' else 'Z'; PAL_ACCESS_inout_stdlv_OE(13) <= BOARD_CONTROL_1_DATA_int_stdlv(6); _n0104/_n0104_D2 <= (PAL_ACCESS_inout_stdlv(8) AND NOT OCB_ADRS_in_stdlv(1) AND NOT OCB_ADRS_in_stdlv(4) AND OCB_ADRS_in_stdlv(2) AND NOT OCB_ADRS_in_stdlv(3) AND FPGA_0_STATUS_in_stdlv(3)); _n0105/_n0105_D2 <= (PAL_ACCESS_inout_stdlv(8) AND OCB_ADRS_in_stdlv(1) AND NOT OCB_ADRS_in_stdlv(4) AND OCB_ADRS_in_stdlv(2) AND NOT OCB_ADRS_in_stdlv(3) AND CRATE_STATUS_B_in_stdlv(3)); _n0106/_n0106_D2 <= (PAL_ACCESS_inout_stdlv(8) AND OCB_ADRS_in_stdlv(1) AND NOT OCB_ADRS_in_stdlv(4) AND OCB_ADRS_in_stdlv(2) AND OCB_ADRS_in_stdlv(3) AND CNFG_BUSY_in_stdlv(1)); _n0107/_n0107_D2 <= (PAL_ACCESS_inout_stdlv(8) AND BOARD_CONTROL_1_DATA_int_stdlv(3) AND NOT OCB_ADRS_in_stdlv(1) AND NOT OCB_ADRS_in_stdlv(4) AND NOT OCB_ADRS_in_stdlv(2) AND NOT OCB_ADRS_in_stdlv(3)); _n0108/_n0108_D2 <= (PAL_ACCESS_inout_stdlv(8) AND DRV_CRATE_STATUS_reg_stdlv(3) AND OCB_ADRS_in_stdlv(1) AND NOT OCB_ADRS_in_stdlv(4) AND NOT OCB_ADRS_in_stdlv(2) AND NOT OCB_ADRS_in_stdlv(3)); _n0109/_n0109_D2 <= (PAL_ACCESS_inout_stdlv(8) AND CNFG_CS_B_reg_stdlv(1) AND OCB_ADRS_in_stdlv(1) AND NOT OCB_ADRS_in_stdlv(4) AND NOT OCB_ADRS_in_stdlv(2) AND OCB_ADRS_in_stdlv(3)); _n0110/_n0110_D2 <= (PAL_ACCESS_inout_stdlv(8) AND NOT OCB_ADRS_in_stdlv(1) AND NOT OCB_ADRS_in_stdlv(4) AND OCB_ADRS_in_stdlv(2) AND NOT OCB_ADRS_in_stdlv(3) AND FPGA_1_STATUS_in_stdlv(0)); _n0111/_n0111_D2 <= (PAL_ACCESS_inout_stdlv(8) AND OCB_ADRS_in_stdlv(1) AND NOT OCB_ADRS_in_stdlv(4) AND OCB_ADRS_in_stdlv(2) AND NOT OCB_ADRS_in_stdlv(3) AND LAST_DAC_OUTPUT_DATA_in_stdl); _n0112/_n0112_D2 <= (PAL_ACCESS_inout_stdlv(8) AND OCB_ADRS_in_stdlv(1) AND NOT OCB_ADRS_in_stdlv(4) AND OCB_ADRS_in_stdlv(2) AND OCB_ADRS_in_stdlv(3) AND CNFG_DONE_in_stdlv(0)); _n0113/_n0113_D2 <= (PAL_ACCESS_inout_stdlv(8) AND BOARD_CONTROL_1_DATA_int_stdlv(4) AND NOT OCB_ADRS_in_stdlv(1) AND NOT OCB_ADRS_in_stdlv(4) AND NOT OCB_ADRS_in_stdlv(2) AND NOT OCB_ADRS_in_stdlv(3)); _n0114/_n0114_D2 <= (PAL_ACCESS_inout_stdlv(8) AND DRV_CRATE_TO_SCLD_reg_stdlv(0) AND OCB_ADRS_in_stdlv(1) AND NOT OCB_ADRS_in_stdlv(4) AND NOT OCB_ADRS_in_stdlv(2) AND NOT OCB_ADRS_in_stdlv(3)); _n0115/_n0115_D2 <= (PAL_ACCESS_inout_stdlv(8) AND CNFG_RDWR_B_reg_stdl AND OCB_ADRS_in_stdlv(1) AND NOT OCB_ADRS_in_stdlv(4) AND NOT OCB_ADRS_in_stdlv(2) AND OCB_ADRS_in_stdlv(3)); _n0142/_n0142_D <= OCB_ADRS_in_stdlv(21) XOR _n0142/_n0142_D <= VME_GEO_B_in_stdlv(3); _n0145/_n0145_D <= OCB_ADRS_in_stdlv(22) XOR _n0145/_n0145_D <= VME_GEO_B_in_stdlv(4); Register Legend: FDCPE (Q,D,C,CLR,PRE,CE); FTCPE (Q,D,C,CLR,PRE,CE); LDCP (Q,D,G,CLR,PRE); **************************** Device Pin Out **************************** Device : XC95144XL-5-TQ144 Pin Signal Pin Signal No. Name No. Name 1 VCC 73 VCC 2 CNFG_CS_B_reg_stdlv(1) 74 OCB_ADRS_in_stdlv(22) 3 CNFG_INIT_B_in_stdlv(1) 75 OCB_DATA_inout_stdlv(7) 4 CNFG_BUSY_in_stdlv(1) 76 OCB_ADRS_in_stdlv(21) 5 DATA_BUF_DIR_out_stdl 77 OCB_DATA_inout_stdlv(6) 6 OCB_DIRECTION_out_stdl 78 OCB_ADRS_in_stdlv(20) 7 CNFG_DONE_in_stdlv(1) 79 OCB_ADRS_in_stdlv(19) 8 VCC 80 OCB_ADRS_in_stdlv(18) 9 CNFG_CCLK_out_stdl 81 OCB_ADRS_in_stdlv(17) 10 CNFG_RDWR_B_reg_stdl 82 OCB_ADRS_in_stdlv(16) 11 CNFG_PROG_B_out_stdlv(0) 83 OCB_DATA_inout_stdlv(5) 12 CNFG_CS_B_reg_stdlv(0) 84 VCC 13 CNFG_INIT_B_in_stdlv(0) 85 OCB_DATA_inout_stdlv(4) 14 CNFG_BUSY_in_stdlv(0) 86 OCB_ADRS_in_stdlv(15) 15 CNFG_DONE_in_stdlv(0) 87 OCB_ADRS_in_stdlv(14) 16 FPGA_1_STATUS_in_stdlv(0) 88 OCB_ADRS_in_stdlv(13) 17 FPGA_1_STATUS_in_stdlv(1) 89 GND 18 GND 90 GND 19 FPGA_1_STATUS_in_stdlv(2) 91 OCB_ADRS_in_stdlv(12) 20 FPGA_1_STATUS_in_stdlv(3) 92 OCB_ADRS_in_stdlv(11) 21 FPGA_0_STATUS_in_stdlv(0) 93 OCB_ADRS_in_stdlv(10) 22 FPGA_0_STATUS_in_stdlv(1) 94 OCB_DATA_inout_stdlv(3) 23 FPGA_0_STATUS_in_stdlv(2) 95 OCB_DATA_inout_stdlv(2) 24 FPGA_0_STATUS_in_stdlv(3) 96 OCB_ADRS_in_stdlv(9) 25 PAL_ACCESS_inout_stdlv(0) 97 OCB_ADRS_in_stdlv(8) 26 ADC_ENABLE_reg_stdl 98 OCB_ADRS_in_stdlv(7) 27 SER_DC_BALANCE_reg_stdl 99 GND 28 SER_DESKEW_B_reg_stdl 100 OCB_DATA_inout_stdlv(1) 29 GND 101 OCB_ADRS_in_stdlv(6) 30 PAL_BX_CLOCK_in_stdl 102 OCB_ADRS_in_stdlv(5) 31 DRV_CRATE_TO_SCLD_reg_stdlv(0) 103 OCB_ADRS_in_stdlv(4) 32 RCVD_BX_CLOCK_inout_stdl 104 OCB_ADRS_in_stdlv(3) 33 CNT_BIT_VAL_4_inout_stdl 105 OCB_ADRS_in_stdlv(2) 34 PAL_FIRST_X8_EDGE_out_stdl 106 OCB_ADRS_in_stdlv(1) 35 DRV_CRATE_TO_SCLD_reg_stdlv(1) 107 OCB_DATA_inout_stdlv(0) 36 GND 108 GND 37 VCC 109 VCC 38 PAL_BX_X8_CLOCK_in_stdl 110 PAL_ACCESS_inout_stdlv(12) 39 LOOP_FILTER_REF_inout_stdl 111 PAL_ACCESS_inout_stdlv(13) 40 PHASE_DET_OUT_out_stdl 112 PAL_ACCESS_inout_stdlv(14) 41 PAL_ACCESS_inout_stdlv(1) 113 PAL_ACCESS_inout_stdlv(15) 42 VCC 114 GND 43 PAL_ACCESS_inout_stdlv(2) 115 PAL_ACCESS_inout_stdlv(16) 44 PAL_ACCESS_inout_stdlv(3) 116 DRV_PAL_LED_out_stdlv(0) 45 PAL_ACCESS_inout_stdlv(4) 117 DRV_CRATE_STATUS_reg_stdlv(0) 46 PAL_ACCESS_inout_stdlv(5) 118 CRATE_STATUS_B_in_stdlv(2) 47 GND 119 DRV_CRATE_STATUS_reg_stdlv(1) 48 PAL_ACCESS_inout_stdlv(6) 120 DRV_CRATE_STATUS_reg_stdlv(2) 49 PAL_ACCESS_inout_stdlv(7) 121 DRV_CRATE_STATUS_reg_stdlv(3) 50 PAL_ACCESS_inout_stdlv(8) 122 TDO 51 PAL_ACCESS_inout_stdlv(9) 123 GND 52 DATA_BUF_ENB_B_out_stdl 124 CRATE_STATUS_B_in_stdlv(0) 53 VME_LTCH_CLK_out_stdl 125 CRATE_STATUS_B_in_stdlv(1) 54 DRV_DTACK_out_stdl 126 CRATE_STATUS_B_in_stdlv(3) 55 VCC 127 VCC 56 RCVD_DS1_in_stdl 128 DRV_PAL_LED_out_stdlv(1) 57 PAL_ACCESS_inout_stdlv(10) 129 VME_GEO_B_in_stdlv(0) 58 PAL_ACCESS_inout_stdlv(11) 130 VME_GEO_B_in_stdlv(1) 59 LTCHD_AM_in_stdlv(4) 131 VME_GEO_B_in_stdlv(2) 60 LTCHD_IACK_B_in_stdl 132 VME_GEO_B_in_stdlv(3) 61 LTCHD_AM_in_stdlv(3) 133 VME_GEO_B_in_stdlv(4) 62 GND 134 DATA_TO_FIRST_DAC_INPUT_out_stdl 63 TDI 135 DAC_SERIAL_DATA_CLOCK_out_stdl 64 LTCHD_AM_in_stdlv(2) 136 DAC_CHIP_SELECT_B_out_stdl 65 TMS 137 LAST_DAC_OUTPUT_DATA_in_stdl 66 LTCHD_AM_in_stdlv(1) 138 OCB_CHIP_SEL_B_out_stdlv(1) 67 TCK 139 OCB_CHIP_SEL_B_out_stdlv(0) 68 LTCHD_AM_in_stdlv(0) 140 OCB_WRITE_STRB_B_inout_stdl 69 LTCHD_WRITE_B_in_stdl 141 VCC 70 LTCHD_AM_in_stdlv(5) 142 CNFG_PROG_B_out_stdlv(1) 71 OCB_ADRS_in_stdlv(23) 143 VME_SYSRESET_B_in_stdl 72 GND 144 GND Legend : NC = Not Connected, unbonded pin PGND = Unused I/O configured as additional Ground pin TIE = Unused I/O floating -- must tie to VCC, GND or other signal VCC = Dedicated Power Pin GND = Dedicated Ground Pin TDI = Test Data In, JTAG pin TDO = Test Data Out, JTAG pin TCK = Test Clock, JTAG pin TMS = Test Mode Select, JTAG pin PE = Port Enable pin PROHIBITED = User reserved pin **************************** Compiler Options **************************** Following is a list of all global compiler options used by the fitter run. Device(s) Specified : xc95144xl-5-TQ144 Optimization Method : DENSITY Multi-Level Logic Optimization : OFF Ignore Timing Specifications : OFF Default Register Power Up Value : LOW Keep User Location Constraints : ON What-You-See-Is-What-You-Get : OFF Exhaustive Fitting : OFF Keep Unused Inputs : ON Slew Rate : SLOW Power Mode : STD Set Unused I/O Pin Termination : GROUND Set I/O Pin Termination : KEEPER Global Clock Optimization : ON Global Set/Reset Optimization : ON Global Ouput Enable Optimization : ON Input Limit : 54 Pterm Limit : 20