# DAC_LOADING.do # # This simulation confirms the control signals for loading the DACs. # The inputs for this simulation are OCB_ADRS, OCB_DATA, and the register bits # ENABLE_DAC_LOADING and DAC_CHIP_SEL_B_REQ. The outputs for this simulations # are DAC_SERIAL_CLOCK, DAC_CHIP_SEL_B and DATA_TO_FIRST_DAC_INPUT. # # Powerup States # ============== # Cycle 0 # ------- # The powerup states should be as follows. # ENABLE_LOADING_DACS = 0 # DAC_CHIP_SEL_B_REQ = 1 # DAC_CHIP_SEL_B = 1 # DAC_SERIAL_DATA_CLOCK = 0 # DATA_TO_FIRST_DAC = 1 # # VME_AM, OCB_ADRS, and VME_GEO are set so that # VALID_CYCLE = 0 # # Quiescent States during VME IO Cycle not for this card # ====================================================== # Cycles 3-13 # ----------- # DS1 is asserted initiating a VME IO cycle but the target is an FPGA on another # card. # VALID_CYCLE = 0 # The direction is set to WRITE. # The following signals should have the stated values through the whole VME IO # cycle. # ENABLE_LOADING_DACS = 0 # DAC_CHIP_SEL_B_REQ = 1 # DAC_CHIP_SEL_B = 1 # DAC_SERIAL_DATA_CLOCK = 0 # DATA_TO_FIRST_DAC = 1 # # ENABLE_LOADING_DACS # =================== # Cycles 15-48 # ------------ # The OCB_ADRS is set so that VALID_CYCLE is asserted. # The Board Control 2 Register is written to so that DAC_CHIP_SEL_B_REQ is # asserted. # Data is written to the BOARD LEVEL DAC DATA register. # DAC_CHIP_SEL_B, DAC_SERIAL_CLOCK and DATA_TO_FIRST_DAC should remain at # powerup values because ENABLE_LOADING_DACS is not asserted. # # LOAD DACS # ======== # Cycles 51-85 # ------------ # The Board Control 1 Register is writen to so that ENABLE_LOADING_DACS is # asserted. # The Board Control 2 Register is written to so that DAC_CHIP_SEL_B_REQ is # asserted. # Data is written to the BOARD LEVEL DAC DATA register. # DAC_CHIP_SEL_B should be asseted from LATCH_2 through SET_QUIESCENT states # and DAC_SERIAL_DATA_CLOCK should be asserted during the IO_1 state. # # SysReset # ======== # Cycles 87-100 # ------------- # A write to the BOARD LEVEL DAC DATA register is done. # Sysreset is asserted. The signals should return to their powerup states. # restart simulation without confirming and clearing wave window. restart -force -nowave # Add signals to wave window. do DAC_LOAD_waves.do # Clock definition force /bcp/pal_bx_clock_in_stdl 1 66ns, 0 132ns -r 132ns set cycle 132 set 1_cycle [expr $cycle*1]ns set 2_cycles [expr $cycle*2]ns set 3_cycles [expr $cycle*3]ns set 4_cycles [expr $cycle*4]ns set 5_cycles [expr $cycle*5]ns set 6_cycles [expr $cycle*6]ns set 7_cycles [expr $cycle*7]ns set 8_cycles [expr $cycle*8]ns set 9_cycles [expr $cycle*9]ns set 10_cycles [expr $cycle*10]ns #===================================================================================== # Cycle 0 #===================================================================================== # Signal initial values for clock, sysreset, and ds1. force /bcp/pal_bx_clock_in_stdl 0 force /bcp/vme_sysreset_b_in_stdl 1 force /bcp/rcvd_ds1_in_stdl 0 # Addressing Prerequisites # PAL on another card # Valid cycle should be deasserted because ocb_adrs != vme_geo. force /bcp/ltchd_iack_b_in_stdl 0 force /bcp/ltchd_am_in_stdlv 100111 force /bcp/vme_geo_b_in_stdlv 10000 force /bcp/ocb_adrs_in_stdlv 16#0 force /bcp/ocb_adrs_in_stdlv(18:22) 01110 force /bcp/ocb_adrs_in_stdlv(5:17) 0000000000000 force /bcp/ocb_adrs_in_stdlv(1:4) 0010 force /bcp/ocb_data_inout_stdlv(0:7) 00000000 # VME I/O directon is write to ADF force /bcp/ltchd_write_b_in_stdl 0 #===================================================================================== # Cycles 1-2 #===================================================================================== run $2_cycles #===================================================================================== # Cycles 3-13 #===================================================================================== # LOAD DACS on another card force /bcp/rcvd_ds1_in_stdl 1 run $9_cycles force /bcp/rcvd_ds1_in_stdl 0 run $3_cycles #===================================================================================== # Cycles 15-24 #===================================================================================== # # Seet ocb_adrs so that VALID_CYCLE is asserted force /bcp/ocb_adrs_in_stdlv(18:22) 01111 # Assert DAC_CHIP_SEL_B_REQ force /bcp/ocb_adrs_in_stdlv(1:4) 1000 force /bcp/ocb_data_inout_stdlv(0:7) 00000000 force /bcp/rcvd_ds1_in_stdl 1 run $9_cycles force /bcp/rcvd_ds1_in_stdl 0 run $3_cycles # Write '1' to BOARD LEVEL DAC DATA Register force /bcp/ocb_adrs_in_stdlv(1:4) 0010 force /bcp/ocb_data_inout_stdlv(0:7) 00000000 force /bcp/rcvd_ds1_in_stdl 1 run $9_cycles force /bcp/rcvd_ds1_in_stdl 0 run $3_cycles # Deassert DAC_CHIP_SEL_B_REQ force /bcp/ocb_adrs_in_stdlv(1:4) 1000 force /bcp/ocb_data_inout_stdlv(0:7) 00000010 force /bcp/rcvd_ds1_in_stdl 1 run $9_cycles force /bcp/rcvd_ds1_in_stdl 0 run $3_cycles #===================================================================================== # Cycles 15-24 #===================================================================================== # # Assert ENABLE_LOADING_DACS force /bcp/ocb_adrs_in_stdlv(1:4) 0000 force /bcp/ocb_data_inout_stdlv(0:7) 00000100 force /bcp/rcvd_ds1_in_stdl 1 run $9_cycles force /bcp/rcvd_ds1_in_stdl 0 run $3_cycles # Assert DAC_CHIP_SEL_B_REQ force /bcp/ocb_adrs_in_stdlv(1:4) 1000 force /bcp/ocb_data_inout_stdlv(0:7) 00000000 force /bcp/rcvd_ds1_in_stdl 1 run $9_cycles force /bcp/rcvd_ds1_in_stdl 0 run $3_cycles # Write '1' to BOARD LEVEL DAC DATA Register force /bcp/ocb_adrs_in_stdlv(1:4) 0010 force /bcp/ocb_data_inout_stdlv(0:7) 10000000 force /bcp/rcvd_ds1_in_stdl 1 run $9_cycles force /bcp/rcvd_ds1_in_stdl 0 run $3_cycles #===================================================================================== # Cycles 15-24 #===================================================================================== # # Sysreset # Write '1' to BOARD LEVEL DAC DATA Register force /bcp/ocb_adrs_in_stdlv(1:4) 0010 force /bcp/ocb_data_inout_stdlv(0:7) 10000000 force /bcp/rcvd_ds1_in_stdl 1 run $5_cycles force /bcp/vme_sysreset_b_in_stdl 0 run $9_cycles