# FPGA_CONFIG.do # # This simulation confirms the control signals for configuring the FPGAs. # The inputs for this simulation are OCB_ADRS, OCB_DATA, and the register bits # ENABLE_FPGA_CONFIGURATION and CNFG_PROG_B_REQ. The outputs for this simulations # are CNFG_CCLK, and CNFG_PROG_B. All other signals to the FPGA are register # controlled bits. # # Powerup States # ============== # Cycle 0 # ------- # The powerup states should be as follows. # ENABLE_FPGA_CONFIGURATION = 0 # CNFG_PROG_B_REQ = 1 # CNFG_PROG_B = 1 # CNFG_CS_B = 1 # CNFG_RDWR_B = 1 # CNFG_CCLK = 0 # # VME_AM, OCB_ADRS, and VME_GEO are set so that # VALID_CYCLE = 0 # # Quiescent States during VME IO Cycle not for this card # ====================================================== # Cycles 3-13 # ----------- # DS1 is asserted initiating a VME IO cycle but the target is an FPGA on another # card. # VALID_CYCLE = 0 # The direction is set to WRITE. # The following signals should have the stated values through the whole VME IO # cycle. # ENABLE_FPGA_CONFIGURATION = 0 # CNFG_PROG_B_REQ = 1 # CNFG_PROG_B = 1 # CNFG_CS_B = 1 # CNFG_RDWR_B = 1 # CNFG_CCLK = 0 # # ENABLE_FPGA_CONFIGURATION # ========================= # Cycles 15-25 # ------------ # The OCB_ADRS is set so that VALID_CYCLE is asserted. # # The Configuration Control Register is written to so that CNFG_CS_B and # CNFG_PROG_B_REQ are asserted. # # Cycles 27-37 # ------------ # The Configuration Control Register is written to so that CNFG_PROG_B_REQ is # Data is written to the CONFIGURATION DATA register. # CNFG_PROG_B should remain 1 because ENABLE_FPGA_CONFIGURATION is not asserted. # The CNFG_CCLK should remain 0 because ENABLE_FPGA_CONFIGURATION is not asserted. # # LOAD DACS # ======== # Cycles 39-49 # ------------ # The Board Level Control Register 1 is written to so that # ENABLE_FPGA_CONFIGURATION is asserted. # CNFG_PROG_B should be asserted since both ENABLE_FPGA_CONFIGURATION and # CNFG_PROG_B_REQ are asserted. # # Cycles 51-61 # ------------ # Data is written to the CONFIGURATION DATA register. # CNFG_PROG_B should be 0 because ENABLE_FPGA_CONFIGURATION and CNFG_PROG_B_REQ are # asserted. # The CNFG_CCLK should pulse high during the IO_1 state because # # SysReset # ======== # Cycles 63-73 # ------------- # A write to the FPGA CONFIGURATION DATA register is done. # Sysreset is asserted. The signals should return to their powerup states. # restart simulation without confirming and clearing wave window. restart -force -nowave # Add signals to wave window. do FPGA_CONFIG_waves.do # Clock definition force /bcp/pal_bx_clock_in_stdl 1 66ns, 0 132ns -r 132ns set cycle 132 set 1_cycle [expr $cycle*1]ns set 2_cycles [expr $cycle*2]ns set 3_cycles [expr $cycle*3]ns set 4_cycles [expr $cycle*4]ns set 5_cycles [expr $cycle*5]ns set 6_cycles [expr $cycle*6]ns set 7_cycles [expr $cycle*7]ns set 8_cycles [expr $cycle*8]ns set 9_cycles [expr $cycle*9]ns set 10_cycles [expr $cycle*10]ns #===================================================================================== # Cycle 0 #===================================================================================== # Signal initial values for clock, sysreset, and ds1. force /bcp/pal_bx_clock_in_stdl 0 force /bcp/vme_sysreset_b_in_stdl 1 force /bcp/rcvd_ds1_in_stdl 0 # Addressing Prerequisites # PAL on another card # Valid cycle should be deasserted because ocb_adrs != vme_geo. force /bcp/ltchd_iack_b_in_stdl 0 force /bcp/ltchd_am_in_stdlv 100111 force /bcp/vme_geo_b_in_stdlv 10000 force /bcp/ocb_adrs_in_stdlv 16#0 force /bcp/ocb_adrs_in_stdlv(18:22) 01110 force /bcp/ocb_adrs_in_stdlv(5:17) 0000000000000 force /bcp/ocb_adrs_in_stdlv(1:4) 0110 force /bcp/ocb_data_inout_stdlv(0:7) 00000000 # VME I/O directon is write to ADF force /bcp/ltchd_write_b_in_stdl 0 #===================================================================================== # Cycles 1-2 #===================================================================================== run $2_cycles #===================================================================================== # Cycles 3-13 #===================================================================================== # FPGA Configuration on another card force /bcp/rcvd_ds1_in_stdl 1 run $9_cycles force /bcp/rcvd_ds1_in_stdl 0 run $3_cycles #===================================================================================== # Cycles 15-24 #===================================================================================== # # Seet ocb_adrs so that VALID_CYCLE is asserted force /bcp/ocb_adrs_in_stdlv(18:22) 01111 # Assert CNFG_CS_B(0:1) and leave CNFG_PROG_B(0:1) and CNFG_RDWR_B # deasserted. force /bcp/ocb_adrs_in_stdlv(1:4) 1010 force /bcp/ocb_data_inout_stdlv(0:7) 00001000 force /bcp/rcvd_ds1_in_stdl 1 run $9_cycles force /bcp/rcvd_ds1_in_stdl 0 run $3_cycles #===================================================================================== # Cycles 26-36 #===================================================================================== # Write '0' to CONFIGURATION DATA Register force /bcp/ocb_adrs_in_stdlv(1:4) 0110 force /bcp/ocb_data_inout_stdlv(0:7) 00000000 force /bcp/rcvd_ds1_in_stdl 1 run $9_cycles force /bcp/rcvd_ds1_in_stdl 0 run $3_cycles #===================================================================================== # Cycles 39-49 #===================================================================================== # # Assert ENABLE_FPGA_CONFIGURATION force /bcp/ocb_adrs_in_stdlv(1:4) 0000 force /bcp/ocb_data_inout_stdlv(0:7) 00001000 force /bcp/rcvd_ds1_in_stdl 1 run $9_cycles force /bcp/rcvd_ds1_in_stdl 0 run $3_cycles # Write '0' to CONFIGURATION DATA Register force /bcp/ocb_adrs_in_stdlv(1:4) 0110 force /bcp/ocb_data_inout_stdlv(0:7) 00000000 force /bcp/rcvd_ds1_in_stdl 1 run $9_cycles force /bcp/rcvd_ds1_in_stdl 0 run $3_cycles #===================================================================================== # Cycles - #===================================================================================== # # Sysreset # Write '0' to BOARD LEVEL DAC DATA Register force /bcp/ocb_adrs_in_stdlv(1:4) 0110 force /bcp/ocb_data_inout_stdlv(0:7) 00000000 force /bcp/rcvd_ds1_in_stdl 1 run $5_cycles force /bcp/vme_sysreset_b_in_stdl 0 run $9_cycles