# OCB_IO.do
#
# This simulation confirms the OCB control signals and Data Buffer
# control signals for both VME read and write I/O cycles.  The inputs for this 
# simulation are LTCHD_WRITE_B, OCB_ADRS.  The outputs for this simulations are
# DATA_BUF_ENB_B, DATA_BUF_DIR, OCB_DIRECTION, OCB_WRITE_STRB_B, OCB_CHIP_SEL,
# OCB_CHIP_SEL_B, OCB_OUTPUT_ENABLE.
#
# Powerup States
# ==============
#   Cycle 0
#   -------
#   The powerup states should be as follows.
#     DATA_BUF_ENB_B        = 1
#     DATA_BUF_DIR          = 1
#     OCB_DIRECTION         = 1
#     OCB_WRITE_STB_B       = 1
#     OCB_CHIP_SEL_B(0:1)   = 1 
#     OCB_DATA_OUTPUT_ENABLE= 0  
#
#   VME_AM, OCB_ADRS, and VME_GEO are set so that 
#     VALID_CYCLE           = 0
#
# Quiescent States during VME IO Cycle not for this card
# ======================================================
#   Cycles 3-13
#   -----------
#   DS1 is asserted initiating a VME IO cycle but the target is an FPGA on another
#   card.
#     VALID_CYCLE = 0
#   The direction is set to WRITE.  
#   The following signals should have the stated values through the whole VME IO 
#   cycle.
#     DATA_BUF_ENB_B    = 0
#     DATA_BUF_DIR      = 0
#     OCB_DIRECTION     = 0
#     OCB_WRITE_STB_B   = 0
#     OCB_CHIP_SEL_B(x) = 1
#
#   Cycles 15-24
#   ------------
#   DS1 is asserted initiating a VME IO cycle but the target is an FPGA on another
#   card.
#     VALID_CYCLE = 1
#   The direction is set to READ.  
#   The following signals should have the stated values through the whole VME IO 
#   cycle.
#     DATA_BUF_ENB_B    = 0
#     DATA_BUF_DIR      = 0
#     OCB_DIRECTION     = 0
#     OCB_WRITE_STB_B   = 0
#     OCB_CHIP_SEL_B(x) = 1
#
# VME Write
# =========
#   FPGA 0/Cycles 26-35
#   -------------------
#   A VME write IO cycle to FPGA 0 Global register is initiated.  
#   During the IO cycle the following signals should have the specified levels
#   for the specified states.
#     Signal               Level   Duration
#     ----------------------------------------------------
#     OCB_WRITE_STRB_B       0     IO_1
#     OCB_DIRECTION          0     IO_1 -> SET_QIESCENT 
#     OCB_BUF_DIR            0     LATCH_2 -> SET_QUIESCENT
#     OCB_DATA_OUTPUT_ENABLE 0     Whole VME IO Cycle
#     DATA_BUF_ENB_B         0     LATCH_2 -> SET_QUIESCENT
#     DATA_BUF_DIR           0     LATCH_2 -> SET_QUIESCENT
#     OCB_CHIP_SEL_B(0:1)    01    LATCH_2 -> SET_QUIESCENT
#     OCB_CHIP_SEL(0:2)      100   LATCH_1 -> SET_QUIESCENT
#
#   OCB_CHIP_SEL(0:2) will not change at the approprate time because the external
#   latch is not simulated.  OCB_ADRS will only change during the LATCH_1 state
#   in real operation, but in the simulation it changes with the DS_1 asssertion.
#
#   After the VME IO cycle (when the state machine returns to the IDLE state) 
#   OCB_CHIP_SEL_B, OCB_DIRECTION, DATA_BUF_ENB_B, and DATA_BUF_DIR should return to 
#   thier powerup and quiescent state of high/1.
# 
#   FPGA 1/Cycles 37-46
#   -------------------
#   A VME write IO cycle to FPGA 1 Global register is initiated.  
#   During the IO cycle the following signals should have the specified levels
#   for the specified states.
#     Signal               Level   Duration
#     ----------------------------------------------------
#     OCB_WRITE_STRB_B       0     IO_1
#     OCB_DIRECTION          0     IO_1 -> SET_QIESCENT 
#     OCB_BUF_DIR            0     LATCH_2 -> SET_QUIESCENT
#     OCB_DATA_OUTPUT_ENABLE 0     Whole VME IO Cycle
#     DATA_BUF_ENB_B         0     LATCH_2 -> SET_QUIESCENT
#     DATA_BUF_DIR           0     LATCH_2 -> SET_QUIESCENT
#     OCB_CHIP_SEL_B(0:1)    10    LATCH_2 -> SET_QUIESCENT
#     OCB_CHIP_SEL(0:2)      010   LATCH_1 -> SET_QUIESCENT
#
#   OCB_CHIP_SEL(0:2) will not change at the approprate time because the external
#   latch is not simulated.  OCB_ADRS will only change during the LATCH_1 state
#   in real operation, but in the simulation it changes with the DS_1 asssertion.
#
#   After the VME IO cycle (when the state machine returns to the IDLE state) 
#   OCB_CHIP_SEL_B, OCB_DIRECTION, DATA_BUF_ENB_B, and DATA_BUF_DIR should return to 
#   thier powerup and quiescent state of high/1.
# 
#   PAL/Cycles 48-57
#   ----------------
#   A VME write IO cycle to PAL Board Control 1 register is initiated.  
#   During the IO cycle the following signals should have the specified levels
#   for the specified states.
#     Signal               Level   Duration
#     ----------------------------------------------------
#     OCB_WRITE_STRB_B       0     IO_1
#     OCB_DIRECTION          0     IO_1 -> SET_QIESCENT 
#     OCB_BUF_DIR            0     LATCH_2 -> SET_QUIESCENT
#     OCB_DATA_OUTPUT_ENABLE 0     Whole VME IO Cycle
#     DATA_BUF_ENB_B         0     LATCH_2 -> SET_QUIESCENT
#     DATA_BUF_DIR           0     LATCH_2 -> SET_QUIESCENT
#     OCB_CHIP_SEL_B(0:1)    11    LATCH_2 -> SET_QUIESCENT
#     OCB_CHIP_SEL(0:2)      001   LATCH_1 -> SET_QUIESCENT
#
#   OCB_CHIP_SEL(0:2) will not change at the approprate time because the external
#   latch is not simulated.  OCB_ADRS will only change during the LATCH_1 state
#   in real operation, but in the simulation it changes with the DS_1 asssertion.
#
#   After the VME IO cycle (when the state machine returns to the IDLE state) 
#   OCB_CHIP_SEL_B, OCB_DIRECTION, DATA_BUF_ENB_B, and DATA_BUF_DIR should return to 
#   thier powerup and quiescent state of high/1.
# 
# VME Read
# ========
#   PAL/Cycles 59-68
#   ----------------
#   A VME read IO cycle is initiated targeted for the PAL.  
#
#   The following signals should have the indicated levels for the specified duration.
#
#     Signal               Level   Duration
#     ----------------------------------------------------
#     OCB_WRITE_STRB_B       1     Whole VME IO Cyle
#     OCB_DIRECTION          0     Whole VME IO Cyle 
#     OCB_BUF_DIR            1     Whole VME IO Cyle  
#     OCB_BUF_ENB_B          0     IO_2 -> SET_QUIESCENT
#     OCB_DATA_OUTPUT_ENABLE 1     IO_2 -> SET_QUIESCENT
#     OCB_CHIP_SEL_B(0:1)    11    LATCH_2 -> SET_QUIESCENT
#     OCB_CHIP_SEL(0:2)      001   LATCH_1 -> SET_QUIESCENT
#   
#   After the VME IO cycle, OCB_CHIP_SEL_B, OCB_DIRECTION, DATA_BUF_ENB_B, and 
#   DATA_BUF_DIR should return to thier powerup and quiescent state of high/1.
#
#   FPGA 0/Cycles 70-79
#   -------------------
#   A VME read IO cycle is initiated targeted for FPGA 0.  
#
#   The following signals should have the indicated levels for the specified duration.
#
#     Signal               Level   Duration
#     ----------------------------------------------------
#     OCB_WRITE_STRB_B       1     Whole VME IO Cyle
#     OCB_DIRECTION          0     Whole VME IO Cyle 
#     OCB_BUF_DIR            1     Whole VME IO Cyle  
#     OCB_BUF_ENB_B          0     IO_2 -> SET_QUIESCENT
#     OCB_DATA_OUTPUT_ENABLE 0     Whole VME IO Cyle  
#     OCB_CHIP_SEL_B(0:1)    01    LATCH_2 -> SET_QUIESCENT
#     OCB_CHIP_SEL(0:2)      100   LATCH_1 -> SET_QUIESCENT
#   
#   After the VME IO cycle, OCB_CHIP_SEL_B, OCB_DIRECTION, DATA_BUF_ENB_B, and 
#   DATA_BUF_DIR should return to thier powerup and quiescent state of high/1.
#
#   FPGA 1/Cycles 81-90
#   -------------------
#   A VME read IO cycle is initiated targeted for FPGA 1.  
#
#   The following signals should have the indicated levels for the specified duration.
#
#     Signal               Level   Duration
#     ----------------------------------------------------
#     OCB_WRITE_STRB_B       1     Whole VME IO Cyle
#     OCB_DIRECTION          0     Whole VME IO Cyle 
#     OCB_BUF_DIR            1     Whole VME IO Cyle  
#     OCB_BUF_ENB_B          0     IO_2 -> SET_QUIESCENT
#     OCB_DATA_OUTPUT_ENABLE 0     Whole VME IO Cyle  
#     OCB_CHIP_SEL_B(0:1)    10    LATCH_2 -> SET_QUIESCENT
#     OCB_CHIP_SEL(0:2)      010   LATCH_1 -> SET_QUIESCENT
#   
#   After the VME IO cycle, OCB_CHIP_SEL_B, OCB_DIRECTION, DATA_BUF_ENB_B, and 
#   DATA_BUF_DIR should return to thier powerup and quiescent state of high/1.
#
# SysReset
# ========
#   Cycles 92-101
#   -------------
#   A VME Write cycle targeted for the FPGA 1 on this card is initiated.  During the 
#   IO_2 state Sysreset is asserted.  DATA_BUF_ENB_B, DATA_BUF_DIR, OCB_DIRECTION, 
#   OCB_CHIP_SEL_B(0:1), OCB_DATA_OUTPUT_ENBABLE should be high/1 and 
#   OCB_CHIP_SEL(0:2) should be low.
#




# restart simulation without confirming and clearing wave window.
restart -force -nowave

# Add signals to wave window.
do OCB_IO_waves.do

# Clock definition
force /bcp/pal_bx_clock_in_stdl 1 66ns, 0 132ns -r 132ns

set cycle 132

set 1_cycle  [expr $cycle*1]ns
set 2_cycles [expr $cycle*2]ns
set 3_cycles [expr $cycle*3]ns
set 4_cycles [expr $cycle*4]ns
set 5_cycles [expr $cycle*5]ns
set 6_cycles [expr $cycle*6]ns
set 7_cycles [expr $cycle*7]ns
set 8_cycles [expr $cycle*8]ns
set 9_cycles [expr $cycle*9]ns
set 10_cycles [expr $cycle*10]ns

#=====================================================================================
# Cycle 0
#=====================================================================================
# Signal initial values for clock, sysreset, and ds1.
force /bcp/pal_bx_clock_in_stdl 0
force /bcp/vme_sysreset_b_in_stdl 1
force /bcp/rcvd_ds1_in_stdl 0

# Addressing Prerequisites
# FPGA on another card
# Valid cycle should be deasserted because ocb_adrs != vme_geo.
force /bcp/ltchd_iack_b_in_stdl 0
force /bcp/ltchd_am_in_stdlv 100111
force /bcp/vme_geo_b_in_stdlv 10000
force /bcp/ocb_adrs_in_stdlv 16#0
force /bcp/ocb_adrs_in_stdlv(18:22) 01110
force /bcp/ocb_adrs_in_stdlv(5:17) 0000010000000

# VME I/O directon is write to ADF
force /bcp/ltchd_write_b_in_stdl 0

#=====================================================================================
# Cycles 1-2
#=====================================================================================
run $2_cycles

#=====================================================================================
# Cycles 3-13
#=====================================================================================
# Write to FPGA on another card
force /bcp/rcvd_ds1_in_stdl 1

run $9_cycles

#=====================================================================================
# Cycles 13-15
#=====================================================================================
force /bcp/rcvd_ds1_in_stdl 0

run $3_cycles

#=====================================================================================
# Cycles 15-24
#=====================================================================================
# Read to FPGA on another card
force /bcp/rcvd_ds1_in_stdl 1

# VME I/O directon is write to ADF
force /bcp/ltchd_write_b_in_stdl 1

run $9_cycles

#=====================================================================================
# Cycles 13-15
#=====================================================================================
force /bcp/rcvd_ds1_in_stdl 0

#=====================================================================================
# Cycles 24-26
#=====================================================================================
run $3_cycles

# VME I/O directon is write to ADF
force /bcp/ltchd_write_b_in_stdl 0

#=====================================================================================
# Cycles 26-35
#=====================================================================================
# Write to FPGA0 global register
#                                  0000011111111
#                                  5678901234567
force /bcp/ocb_adrs_in_stdlv(5:17) 0000010000000
force /bcp/ocb_adrs_in_stdlv(18:22) 01111

force /bcp/rcvd_ds1_in_stdl 1

run $8_cycles

force /bcp/rcvd_ds1_in_stdl 0

#=====================================================================================
# Cycles 35-37
#=====================================================================================
run $3_cycles

#=====================================================================================
# Cycles 37-46
#=====================================================================================
# Write to FPGA1 global register
#                                  0000011111111
#                                  5678901234567
force /bcp/ocb_adrs_in_stdlv(5:17) 0000010000001

force /bcp/rcvd_ds1_in_stdl 1

run $8_cycles

force /bcp/rcvd_ds1_in_stdl 0

#=====================================================================================
# Cycles 46-48
#=====================================================================================
run $3_cycles

#=====================================================================================
# Cycles 48-57
#=====================================================================================
# Write to PAL BOARD CONTROL 1register
#                                  0000011111111
#                                  5678901234567
force /bcp/ocb_adrs_in_stdlv(5:17) 0000000000000

force /bcp/rcvd_ds1_in_stdl 1

run $8_cycles

force /bcp/rcvd_ds1_in_stdl 0

#=====================================================================================
# Cycles 57-59
#=====================================================================================
run $3_cycles

# VME I/O directon is READ from ADF
force /bcp/ltchd_write_b_in_stdl 1

#=====================================================================================
# Cycles 59-68
#=====================================================================================
# Read from PAL
#                                  0000011111111
#                                  5678901234567
force /bcp/ocb_adrs_in_stdlv(5:17) 0000000000000
force /bcp/rcvd_ds1_in_stdl 1

run $8_cycles

force /bcp/rcvd_ds1_in_stdl 0

#=====================================================================================
# Cycles 68-70
#=====================================================================================
run $3_cycles


#=====================================================================================
# Cycles 70-79
#=====================================================================================
# Read from FPGA0 HD Et Loockup Register for Trigger Tower 7
#                                  0000011111111
#                                  5678901234567
force /bcp/ocb_adrs_in_stdlv(5:17) 0000010111110

force /bcp/rcvd_ds1_in_stdl 1

run $8_cycles

force /bcp/rcvd_ds1_in_stdl 0

#=====================================================================================
# Cycles 79-81
#=====================================================================================
run $3_cycles

#=====================================================================================
# Cycles 81-90
#=====================================================================================
# Read from FPGA1 HD Et Loockup Register for Trigger Tower 7
#                                  0000011111111
#                                  5678901234567
force /bcp/ocb_adrs_in_stdlv(5:17) 0000010111111

force /bcp/rcvd_ds1_in_stdl 1

run $8_cycles

force /bcp/rcvd_ds1_in_stdl 0

#=====================================================================================
# Cycles 90-92
#=====================================================================================
run $3_cycles




#=====================================================================================
# Cycles 92-99
#=====================================================================================
# Read from FPGA1 HD Et Loockup Register for Trigger Tower 7
force /bcp/rcvd_ds1_in_stdl 1

run $6_cycles

force /bcp/vme_sysreset_b_in_stdl 0

#=====================================================================================
# Cycles 99-103
#=====================================================================================
run $5_cycles