# REGISTER_IO.do
#
# This simulation confirms the writing to and reading from registers
# inside the PAL.
#
#
# Powerup States
# ==============
# Cycle 0
# -------
# The registers should startup with the following states per 
# board control pal implementation document.  
#
#    BOARD_CONTROL_DATA_1(0:7) = 10010000
#    -------------------------
#   Power
#    UP |Bit| Signal
#   ----+---+--------
#     1 | 0 | SER_DESKEW_B
#     0 | 1 | SER_DC_BALANCE
#     0 | 2 | 
#     1 | 3 | CNTRL_PAL_LED_1
#     0 | 4 | ENABLE_FPGA_CONFIGURATION
#     0 | 5 | ENABLE_LOADING_DACS
#     0 | 6 | ENABLE_PAL_ACCESS_OUTPUT
#     0 | 7 | ADC_ENABLE
#
#    BOARD_CONTROL_DATA_2(0:7) = 00000010
#    -------------------------
#
#        Bit| Signal
#        ---+---------------
#     0   0 | DRV_CRATE_STATUS(0)
#     0   1 | DRV_CRATE_STATUS(1)
#     0   2 | DRV_CRATE_STATUS(2) 
#     0   3 | DRV_CRATE_STATUS(3) 
#     0   4 | DRV_CRATE_TO_SCLD(0)
#     0   5 | DRV_CRATE_TO_SCLD(1)
#     1   6 | DAC_CHIP_SELECT_B_REQ
#     0   7 | 
#  
#    CNFG_CONTROL_DATA(0:7) = 11111000
#    ----------------------
#
#        Bit| Signal
#        ---+---------------
#     1   0 | CNFG_PROG_B_REQ(0)
#     1   1 | CNFG_PROG_B_REQ(1)
#     1   2 | CNFG_CS_B(0)
#     1   3 | CNFG_CS_B(1)
#     1   4 | CNFG_RDWR_B
#     0   5 | 
#     0   6 |
#     0   7 | 
#
#    The OCB_DATA(0:7) should be initialized with all 0s.
#    
#  Addressing Prerequisites
#  ======================== 
#  Cycle 0
#  -------
#  LTCHD_IACK_B, LTCHD_AM, VME_GEO_B, and OCB_ADRS are set
#  so that VALID_CYCLE is asserted initially.
#
#  PAL Control Registers
#  =====================
#  Note, usused bits in a register are always 0.
#
#  Board Control 1 Register
#  ------------------------
#    Cycles 3-12
#    -----------
#    A VME Write IO cycle is initiated.  The OCB_ADRS is set 
#    so that the PAL Board Control 1 Register is the target.  
#    The DATA is set to all 1s.  
#    board_control_1_data(0:7) should change to 11011111.
#
#    Cycle 14-23
#    -----------
#    A VME Read IO cycle is initiated.  The OCB_ADRS is set 
#    so that the PAL Board Control 1 Register is the target.  
#    ocb_data_inout(0:7) should change to 11011111.
#
#    Cycle 25-34
#    -----------
#    A VME Write IO cycle is initiated.  The OCB_ADRS is set 
#    so that the PAL Board Control 1 Register is the target.  
#    The DATA is set to all 0s.  
#    board_control_1_data(0:7) should change to 00000000.
#
#    Cycle 36-45
#    -----------
#    A VME Read IO cycle is initiated.  The OCB_ADRS is set 
#    so that the PAL Board Control 1 Register is the target.  
#    ocb_data_inout(0:7) should change to 00000000.
#
#  Board Control 2 Register
#  ------------------------
#    Cycle 47-56
#    -----------
#    A VME Write IO cycle is initiated.  The OCB_ADRS is set 
#    so that the PAL Board Control 2 Register is the target.  
#    The DATA is set to all 1s.  
#    board_control_2_data(0:7) should change to 11111110.
#
#    Cycle 58-67
#    -----------
#    A VME Read IO cycle is initiated.  The OCB_ADRS is set 
#    so that the PAL Board Control 2 Register is the target.  
#    ocb_data_inout(0:7) should change to 11111110.
#
#    Cycle 69-78
#    -----------
#    A VME Write IO cycle is initiated.  The OCB_ADRS is set 
#    so that the PAL Board Control 2 Register is the target.  
#    The DATA is set to all 0s.  
#    board_control_2_data(0:7) should change to 00000000.
#
#    Cycle 80-89
#    -----------
#    A VME Read IO cycle is initiated.  The OCB_ADRS is set 
#    so that the PAL Board Control 2 Register is the target.  
#    ocb_data_inout(0:7) should change to 00000000.
#
#  CNFG Control  Register
#  ------------------------
#    Cycle 91-100
#    ------------
#    A VME Write IO cycle is initiated.  The OCB_ADRS is set 
#    so that the PAL CNFG Control Register is the target.  
#    The DATA is set to all 1s.  
#    cnfg_control_data(0:7) should change to 11111000.
#
#    Cycle 102-111
#    -------------
#    A VME Read IO cycle is initiated.  The OCB_ADRS is set 
#    so that the PAL CNFG Control Register is the target.  
#    ocb_data_inout(0:7) should change to 11111000.
#
#    Cycle 113-122
#    -------------
#    A VME Write IO cycle is initiated.  The OCB_ADRS is set 
#    so that the PAL CNFG Control Register is the target.  
#    The DATA is set to all 0s.  
#    cnfg_control_data(0:7) should change to 00000000.
#
#    Cycle 124-133
#    -------------
#    A VME Read IO cycle is initiated.  The OCB_ADRS is set 
#    so that the PAL CNFG Control Register is the target.  
#    ocb_data_inout(0:7) should change to 00000000.
#
#  PAL Status Registers
#  ====================
#
#  Board Status 1 Register  
#  -----------------------
#    Cycle 135-144
#    -------------
#    All the bits in the board_status_1 register are set to 1.
#    A VME Read IO cycle is initiated.  The OCB_ADRS is set 
#    so that the PAL Board Status 1 Register is the target.  
#    ocb_data_inout(0:7) should change to 11111111.
#
#    Cycle 146-155
#    -------------
#    All the bits in the board_status_1 register are set to 0.
#    A VME Read IO cycle is initiated.  The OCB_ADRS is set 
#    so that the PAL Board Status 1 Register is the target.  
#    ocb_data_inout(0:7) should change to 00000000.
#
#  Board Status 2 Register  
#  -----------------------
#    Cycle 157-166
#    -------------
#    All the bits in the board_status_2 register are set to 1.
#    A VME Read IO cycle is initiated.  The OCB_ADRS is set 
#    so that the PAL Board Status 2 Register is the target.  
#    ocb_data_inout(0:7) should change to 11111111.
#
#    Cycle 168-177
#    -------------
#    All the bits in the board_status_2 register are set to 0.
#    A VME Read IO cycle is initiated.  The OCB_ADRS is set 
#    so that the PAL Board Status 2 Register is the target.  
#    ocb_data_inout(0:7) should change to 00000000.
#
#  CNFG Status  Register  
#  ---------------------
#    Cycle 179-188
#    -------------
#    All the bits in the cnfg_status register are set to 1.
#    A VME Read IO cycle is initiated.  The OCB_ADRS is set 
#    so that the PAL CNFG Status Register is the target.  
#    ocb_data_inout(0:7) should change to 11111111.
#
#    Cycle 190-199
#    -------------
#    All the bits in the cnfg_status_ register are set to 0.
#    A VME Read IO cycle is initiated.  The OCB_ADRS is set 
#    so that the PAL CNFG Status Register is the target.  
#    ocb_data_inout(7:0) should change to 00000000.
#
#  FGPA READ/WRITE Tests
#  =====================
#  
#  Write Tests
#  -----------
#    Cycle 201-210/FPGA 0
#    --------------
#    A VME Write IO cycle is initiated with the target being
#    FGPA 0.  None of the registers in the PAL should change.
#
#    Cycle 212-221/FPGA 1
#    --------------
#    A VME Write IO cycle is initiated with the target being
#    FGPA 1.  None of the registers in the PAL should change.
#
#  Read Tests
#  ----------
#    The ocb_data(7:0) bus is forced to all 1s and then released.
#    All PAL registers are set to all 0s.  The ocb_data should
#    remain all 1s if the PAL registers truely do not connect to 
#    the bus while the FPGAs are being read.
#
#    Cycle U/FPGA 0
#    --------------
#    A VME Read IO cycle is initiated and is targeted at FPGA 0.
#    The ocb_data should remain all 1s.
#
#    Cycle V/FPGA 1
#    --------------
#    A VME Read IO cycle is initiated and is targeted at FPGA 1.  
#    The ocb_data should remain all 1s.
#
#  Sysreset
#  ========
#  Cycle W
#  -------
#  Sysreset is asserted.  All registers should reset to their 
#  powerup values. 
#
#  board_control_1_data(7:0)=00001011
#  board_control_2_data(7:0)=01000000
#  cnfg_control_data(7:0)=   00000000
#  ocb_data(7:0)=            00000000



#  A VME Write IO cycle 
# restart simulation without confirming and clearing wave window.
restart -force -nowave

# Add signals to wave window.
do register_io_waves.do

# Clock definition
force /bcp/pal_bx_clock_in_stdl 1 61ns, 0 132ns -r 132ns

set cycle 132

set 1_cycle  [expr $cycle*1]ns
set 2_cycles [expr $cycle*2]ns
set 3_cycles [expr $cycle*3]ns
set 4_cycles [expr $cycle*4]ns
set 5_cycles [expr $cycle*5]ns
set 6_cycles [expr $cycle*6]ns
set 7_cycles [expr $cycle*7]ns
set 8_cycles [expr $cycle*8]ns
set 9_cycles [expr $cycle*9]ns
set 10_cycles [expr $cycle*10]ns

#-------------------------------------------------------------------------------
# Cycle 0
#-------------------------------------------------------------------------------

# Signal initial values for clock, sysreset, and ds1.
force /bcp/pal_bx_clock_in_stdl 0
force /bcp/vme_sysreset_b_in_stdl 1
force /bcp/rcvd_ds1_in_stdl 0

# VME I/O directon is write to ADF
force /bcp/ltchd_write_b_in_stdl 0 

# Addressing Prerequisites
# Valid cycle should be asserted.
force /bcp/ltchd_iack_b_in_stdl 0
force /bcp/ltchd_am_in_stdlv 100111
force /bcp/vme_geo_b_in_stdlv 10000
force /bcp/ocb_adrs_in_stdlv 16#0
force /bcp/ocb_adrs_in_stdlv(18:22) 01111

# Set Status register values
# Status 1
force /bcp/fpga_0_status_in_stdlv(0:3) 1100
force /bcp/fpga_1_status_in_stdlv(0:3) 0101
# Status 2
force /bcp/crate_status_b_in_stdlv(0:3) 1001
force /bcp/last_dac_output_data_in_stdl 0
# FPGA Configuration Status
force /bcp/cnfg_init_b_in_stdlv(0:1) 11 
force /bcp/cnfg_busy_in_stdlv(0:1) 00 
force /bcp/cnfg_done_in_stdlv(0:1) 11 

# Initialize the OCB data to 0.
force /bcp/ocb_data_inout_stdlv(0:7) 00000000

# Address the PAL
force /bcp/ocb_adrs_in_stdlv(5:17) 16#0

run $2_cycles

#================================================================================
# PAL Board Control Register 1
# Set Address to PAL
force /bcp/ocb_adrs_in_stdlv(5:17) 16#0
# Address Control Register 1
force /bcp/ocb_adrs_in_stdlv(1:4) 0000

#-------------------------------------------------------------------------------
# Cycles 3-12
#-------------------------------------------------------------------------------
# Write to PAL Control Register 1

# Initialize the OCB data to all 1s.
force /bcp/ocb_data_inout_stdlv(0:7) 11111111

# VME I/O directon is write to ADF
force /bcp/ltchd_write_b_in_stdl 0

force /bcp/rcvd_ds1_in_stdl 1

run $8_cycles

force /bcp/rcvd_ds1_in_stdl 0

run $3_cycles

#-------------------------------------------------------------------------------
# Cycles 14-23
#-------------------------------------------------------------------------------
# Read from PAL Control Register 1

# noforce ocb_data so it can be driven 
noforce /bcp/ocb_data_inout_stdlv

# VME I/O directon is read from ADF
force /bcp/ltchd_write_b_in_stdl 1

force /bcp/rcvd_ds1_in_stdl 1

run $8_cycles

force /bcp/rcvd_ds1_in_stdl 0

run $3_cycles

#-------------------------------------------------------------------------------
# Cycles 25-34
#-------------------------------------------------------------------------------
# Write to PAL Control Register 1

# Initialize the OCB data to 0.
force /bcp/ocb_data_inout_stdlv(0:7) 00000000

# VME I/O directon is write to ADF
force /bcp/ltchd_write_b_in_stdl 0

force /bcp/rcvd_ds1_in_stdl 1

run $8_cycles

force /bcp/rcvd_ds1_in_stdl 0

run $3_cycles

#-------------------------------------------------------------------------------
# Cycles 36-45
#-------------------------------------------------------------------------------
# Read from PAL Control Register 1

# noforce ocb_data so it can be driven 
noforce /bcp/ocb_data_inout_stdlv

# VME I/O directon is read from ADF
force /bcp/ltchd_write_b_in_stdl 1

force /bcp/rcvd_ds1_in_stdl 1

run $8_cycles

force /bcp/rcvd_ds1_in_stdl 0

run $3_cycles
#================================================================================

#================================================================================
# PAL Board Control Register 2
# Set Address to PAL
force /bcp/ocb_adrs_in_stdlv(5:17) 16#0
# Address Control Register 2
force /bcp/ocb_adrs_in_stdlv(1:4) 1000

#-------------------------------------------------------------------------------
# Cycles 47-56
#-------------------------------------------------------------------------------
# Write to PAL Control Register 2

# Initialize the OCB data to all 1s.
force /bcp/ocb_data_inout_stdlv(0:7) 11111111

# VME I/O directon is write to ADF
force /bcp/ltchd_write_b_in_stdl 0

force /bcp/rcvd_ds1_in_stdl 1

run $8_cycles

force /bcp/rcvd_ds1_in_stdl 0

run $3_cycles

#-------------------------------------------------------------------------------
# Cycles 58-67
#-------------------------------------------------------------------------------
# Read from PAL Control Register 2

# noforce ocb_data so it can be driven 
noforce /bcp/ocb_data_inout_stdlv

# VME I/O directon is read from ADF
force /bcp/ltchd_write_b_in_stdl 1

force /bcp/rcvd_ds1_in_stdl 1

run $8_cycles

force /bcp/rcvd_ds1_in_stdl 0

run $3_cycles

#-------------------------------------------------------------------------------
# Cycles 69-78
#-------------------------------------------------------------------------------
# Write to PAL Control Register 2

# Initialize the OCB data to 0.
force /bcp/ocb_data_inout_stdlv(0:7) 00000000

# VME I/O directon is write to ADF
force /bcp/ltchd_write_b_in_stdl 0

force /bcp/rcvd_ds1_in_stdl 1

run $8_cycles

force /bcp/rcvd_ds1_in_stdl 0

run $3_cycles

#-------------------------------------------------------------------------------
# Cycles 80-89
#-------------------------------------------------------------------------------
# Read from PAL Control Register 2

# noforce ocb_data so it can be driven 
noforce /bcp/ocb_data_inout_stdlv

# VME I/O directon is read from ADF
force /bcp/ltchd_write_b_in_stdl 1

force /bcp/rcvd_ds1_in_stdl 1

run $8_cycles

force /bcp/rcvd_ds1_in_stdl 0

run $3_cycles
#================================================================================

#================================================================================
# PAL CNFG Control Register 
# Set Address to PAL
force /bcp/ocb_adrs_in_stdlv(5:17) 16#0
# Address CNFG Control Register 
force /bcp/ocb_adrs_in_stdlv(1:4) 1010

#-------------------------------------------------------------------------------
# Cycles 91-100
#-------------------------------------------------------------------------------
# Write to PAL CNFG Control Register

# Initialize the OCB data to all 1s.
force /bcp/ocb_data_inout_stdlv(0:7) 11111111

# VME I/O directon is write to ADF
force /bcp/ltchd_write_b_in_stdl 0

force /bcp/rcvd_ds1_in_stdl 1

run $8_cycles

force /bcp/rcvd_ds1_in_stdl 0

run $3_cycles

#-------------------------------------------------------------------------------
# Cycles 102-111
#-------------------------------------------------------------------------------
# Read from PAL CNFG Control Register

# noforce ocb_data so it can be driven 
noforce /bcp/ocb_data_inout_stdlv

# VME I/O directon is read from ADF
force /bcp/ltchd_write_b_in_stdl 1

force /bcp/rcvd_ds1_in_stdl 1

run $8_cycles

force /bcp/rcvd_ds1_in_stdl 0

run $3_cycles

#-------------------------------------------------------------------------------
# Cycles 113-122
#-------------------------------------------------------------------------------
# Write to PAL CNFG Control Register

# Initialize the OCB data to 0.
force /bcp/ocb_data_inout_stdlv(0:7) 00000000

# VME I/O directon is write to ADF
force /bcp/ltchd_write_b_in_stdl 0

force /bcp/rcvd_ds1_in_stdl 1

run $8_cycles

force /bcp/rcvd_ds1_in_stdl 0

run $3_cycles

#-------------------------------------------------------------------------------
# Cycles 124-133
#-------------------------------------------------------------------------------
# Read from PAL CNFG Control Register

# noforce ocb_data so it can be driven 
noforce /bcp/ocb_data_inout_stdlv

# VME I/O directon is read from ADF
force /bcp/ltchd_write_b_in_stdl 1

force /bcp/rcvd_ds1_in_stdl 1

run $8_cycles

force /bcp/rcvd_ds1_in_stdl 0

run $3_cycles
#================================================================================


#================================================================================
# PAL Status 1 Register 
# Set Address to PAL
force /bcp/ocb_adrs_in_stdlv(5:17) 16#0
# Address Status 1 Register 
force /bcp/ocb_adrs_in_stdlv(1:4) 0100

# noforce ocb_data so it can be driven 
noforce /bcp/ocb_data_inout_stdlv

#-------------------------------------------------------------------------------
# Cycles 135-144
#-------------------------------------------------------------------------------
# Read from PAL STATUS 1 Register

# Set Status 1 register values
force /bcp/fpga_0_status_in_stdlv(0:3) 1111
force /bcp/fpga_1_status_in_stdlv(0:3) 1111

# noforce ocb_data so it can be driven 
noforce /bcp/ocb_data_inout_stdlv

# VME I/O directon is read from ADF
force /bcp/ltchd_write_b_in_stdl 1

force /bcp/rcvd_ds1_in_stdl 1

run $8_cycles

force /bcp/rcvd_ds1_in_stdl 0

run $3_cycles

#-------------------------------------------------------------------------------
# Cycles 146-155
#-------------------------------------------------------------------------------
# Read from PAL STATUS 1 Register

# Set Status 1 register values
force /bcp/fpga_0_status_in_stdlv(0:3) 0000
force /bcp/fpga_1_status_in_stdlv(0:3) 0000

# noforce ocb_data so it can be driven 
noforce /bcp/ocb_data_inout_stdlv

# VME I/O directon is read from ADF
force /bcp/ltchd_write_b_in_stdl 1

force /bcp/rcvd_ds1_in_stdl 1

run $8_cycles

force /bcp/rcvd_ds1_in_stdl 0

run $3_cycles
#================================================================================

#================================================================================
# PAL Status 2 Register 
# Set Address to PAL
force /bcp/ocb_adrs_in_stdlv(5:17) 16#0
# Address Status 2 Register 
force /bcp/ocb_adrs_in_stdlv(1:4) 1100

# noforce ocb_data so it can be driven 
noforce /bcp/ocb_data_inout_stdlv

#-------------------------------------------------------------------------------
# Cycles 157-166
#-------------------------------------------------------------------------------
# Read from PAL STATUS 2 Register

# Set Status 2 register values
force /bcp/fpga_0_status_in_stdlv(0:3) 1111
force /bcp/fpga_1_status_in_stdlv(0:3) 1111

# noforce ocb_data so it can be driven 
noforce /bcp/ocb_data_inout_stdlv

# VME I/O directon is read from ADF
force /bcp/ltchd_write_b_in_stdl 1

force /bcp/rcvd_ds1_in_stdl 1

run $8_cycles

force /bcp/rcvd_ds1_in_stdl 0

run $3_cycles

#-------------------------------------------------------------------------------
# Cycles 168-177
#-------------------------------------------------------------------------------
# Read from PAL STATUS 2 Register

# Set Status 2 register values
force /bcp/fpga_0_status_in_stdlv(0:3) 0000
force /bcp/fpga_1_status_in_stdlv(0:3) 0000

# noforce ocb_data so it can be driven 
noforce /bcp/ocb_data_inout_stdlv

# VME I/O directon is read from ADF
force /bcp/ltchd_write_b_in_stdl 1

force /bcp/rcvd_ds1_in_stdl 1

run $8_cycles

force /bcp/rcvd_ds1_in_stdl 0

run $3_cycles
#================================================================================

#================================================================================
# PAL CNFG Status Register 
# Set Address to PAL
force /bcp/ocb_adrs_in_stdlv(5:17) 16#0
# Address CNFG Status Register 
force /bcp/ocb_adrs_in_stdlv(1:4) 1110

# noforce ocb_data so it can be driven 
noforce /bcp/ocb_data_inout_stdlv

#-------------------------------------------------------------------------------
# Cycles 179-188
#-------------------------------------------------------------------------------
# Read from PAL CNFG STATUS Register

# Set CNFG Status register values
force /bcp/fpga_0_status_in_stdlv(0:3) 1111
force /bcp/fpga_1_status_in_stdlv(0:3) 1111

# noforce ocb_data so it can be driven 
noforce /bcp/ocb_data_inout_stdlv

# VME I/O directon is read from ADF
force /bcp/ltchd_write_b_in_stdl 1

force /bcp/rcvd_ds1_in_stdl 1

run $8_cycles

force /bcp/rcvd_ds1_in_stdl 0

run $3_cycles

#-------------------------------------------------------------------------------
# Cycles 190-199
#-------------------------------------------------------------------------------
# Read from PAL CNFG STATUS Register

# Set CNFG Status register values
force /bcp/fpga_0_status_in_stdlv(0:3) 0000
force /bcp/fpga_1_status_in_stdlv(0:3) 0000

# noforce ocb_data so it can be driven 
noforce /bcp/ocb_data_inout_stdlv

# VME I/O directon is read from ADF
force /bcp/ltchd_write_b_in_stdl 1

force /bcp/rcvd_ds1_in_stdl 1

run $8_cycles

force /bcp/rcvd_ds1_in_stdl 0

run $3_cycles
#================================================================================

#================================================================================
# Write to FPGAs
#
#-------------------------------------------------------------------------------
# Cycles 201-210
#-------------------------------------------------------------------------------
# FPGA0 Global Register 
# Set Address to FGPA0 
#                                  0000011111111
#                                  5678901234567
force /bcp/ocb_adrs_in_stdlv(5:17) 0000010000000

# Initialize the OCB data to all 1s.
force /bcp/ocb_data_inout_stdlv(0:7) 11111111

# VME I/O directon is write to ADF
force /bcp/ltchd_write_b_in_stdl 0

force /bcp/rcvd_ds1_in_stdl 1

run $8_cycles

force /bcp/rcvd_ds1_in_stdl 0

run $3_cycles

#-------------------------------------------------------------------------------
# Cycles 212-221
#-------------------------------------------------------------------------------
# FPGA1 Global Register 
# Set Address to FGPA1 
#                                  0000011111111
#                                  5678901234567
force /bcp/ocb_adrs_in_stdlv(5:17) 0000010000001

# Initialize the OCB data to all 1s.
force /bcp/ocb_data_inout_stdlv(0:7) 11111111

# VME I/O directon is write to ADF
force /bcp/ltchd_write_b_in_stdl 0

force /bcp/rcvd_ds1_in_stdl 1

run $8_cycles

force /bcp/rcvd_ds1_in_stdl 0

run $3_cycles
#================================================================================

#================================================================================
# Read from FPGAs
#
#-------------------------------------------------------------------------------
# Cycles 223-232
#-------------------------------------------------------------------------------
# FPGA0 Global Register 
# Set Address to FGPA0 
#                                  0000011111111
#                                  5678901234567
force /bcp/ocb_adrs_in_stdlv(5:17) 0000010000000

# Initialize the OCB data to all 1s.
force /bcp/ocb_data_inout_stdlv(0:7) 00000000

# noforce ocb_data so it can be driven 
noforce /bcp/ocb_data_inout_stdlv

# VME I/O directon is read from ADF
force /bcp/ltchd_write_b_in_stdl 1

force /bcp/rcvd_ds1_in_stdl 1

run $8_cycles

force /bcp/rcvd_ds1_in_stdl 0

run $3_cycles

#-------------------------------------------------------------------------------
# Cycles 234-243
#-------------------------------------------------------------------------------
# FPGA1 Global Register 
# Set Address to FGPA1 
#                                  0000011111111
#                                  5678901234567
force /bcp/ocb_adrs_in_stdlv(5:17) 0000010000001

# Initialize the OCB data to all 1s.
force /bcp/ocb_data_inout_stdlv(0:7) 00000000

# noforce ocb_data so it can be driven 
noforce /bcp/ocb_data_inout_stdlv

# VME I/O directon is read from ADF
force /bcp/ltchd_write_b_in_stdl 1

force /bcp/rcvd_ds1_in_stdl 1

run $8_cycles

force /bcp/rcvd_ds1_in_stdl 0

run $3_cycles
#================================================================================

#================================================================================
# Assert Sysreset to reinitialize register values
#
#-------------------------------------------------------------------------------
# Cycles 243-252
#-------------------------------------------------------------------------------
force /bcp/vme_sysreset_b_in_stdl 0
run $9_cycles