# state_machine.do
#
# The function of this stimulis file is to test if the state machine
# for transistions due to input from DS1 and VALID_CYCLE and the
# assertion of the signals VME_LTCHD_CLK, DRV_DTACK, and 
# NEXT_STATE_QUIESCENT.
#
# Powerup STATES
# ==============
#   Startup/Cycle 0
#   ---------------
#   At startup the state machine should be in the state where IDLE_STATE
#   is asserted/1 and all other states are deasserted/0.  Next_State_Quiescent 
#   should start out asserted/1 and Valid_Cycle, VME_LTCHD_CLK, and DRV_DTACK
#   should start out deasserted/0.  
#
# VME IO cycle not for this ADF card
# ==================================
#   DRV_DTACK should be deasserted/0 for the whole VME IO cycle.
#
#   IDLE STATE/Cycle 2
#   ------------------
#   DS1 is asserted/1.  On the next pal_bx_clock assertion the state machine 
#   enters th LATCH_1 state.  In the LATCH_1 state, NEXT_STATE_QUIESCENT should be 
#   deasserted and VME_LTCH_CLK should be asserted.
#
#   LATCH_1 STATE/Cycle 3
#   ---------------------
#   The state machine should enter the LATCH_2 state on the next pal_bx_clock
#   assertion.  VME_LTCH_CLK should be deasserted.
#
#   LATCH_2 STATE/Cycle 4
#   ---------------------
#   Since VALID_CYCLE is deasserted, the the state machine should enter IO_2
#   on the next pal_bx_clock assertion.  It will wait for DS1 to be deasserted.
#   Since this VME_IO cycle is not for this card, NEXT_STATE_QUIESCENT is asserted.
#
#   IO_2 STATE/Cycles 5-12
#   ----------------------
#   DS1 is deasserted.  On the next pal_bx_clock assertion the state machine enters
#   the SET_QUIESCENT state.
#
#   SET_QUIESCENT STATE/Cycle 12
#   ----------------------------
#   On the next pal_bx_clock assertion the state machine enters the IDLE state.
#   NEXT_STATE_QUIESCENT is asserted/1.
#
#   IDLE STATE/Cycles 13-16 
#   -----------------------
#   All singals should be in their quiescent states.
#
# VME IO cycle for this ADF card
# ==============================
#   IDLE/Cycle 15
#   -------------
#   DS1 is asserted initiating another VME_IO cycle.  On the next
#   pal_bx_clock assertion the state machine should enter the LATCH_1
#   state.
#
#   LATCH_1/Cycle 16
#   ----------------
#   The OCB_ADRS(18:22) now matches the VME_GEO address so VALID_CYCLE should be
#   asserted.  The state machine should enter the LATCH_2 state on the next
#   pal_bx_clock assertion.  NEXT_STAE_QUIESCENT should be deasserted.  VME_LTCH_CLK
#   should be asserted.  VALID_CYCLE will not necessarily change during the 
#   VME_LTCH_CLK assertion because the external latch is not simulated.  The 
#   signals that VALID_CYCLE are dependent are forced to change and may change outside
#   of VME_LTCH_CLK assertion.  During real operation, Valid_Cycle should change
#   during the LATCH_1 state.
#
#   LATCH_2/Cycle 17
#   ----------------
#   Since VALID_CYCLE is asserted, the state machine should enter the IO_1 state
#   on the next pal_bx_clock assertion.  VME_LTCH_CLK should be deasserted.
#
#   IO_1/Cycle 18
#   -------------
#   READ/WRITE IO operations are performed.  The state machine enters IO_2 state on 
#   the next pal_bx_clock assertion. 
#
#   IO_2/Cycles 19-22
#   -----------------
#   DRV_ DTACK is asserted indicating to the VME Master that the VME Slave (ADF card)
#   is done with the IO cycle.  The state machine enters the SET_QUIESCENT state when
#   DS1 is deasserted.
#
#   SET_QUIESCENT/Cycle 22
#   ----------------------
#   DS1 is deasserted ending the VME IO cycle.  DRV_DTACK is deassertd.  The state 
#   machine enters the SET_QUIESCENT state on the next pal_bx_clock assertion.
#
#   IDLE/Cycle 23
#   -------------
#   The state machine enters the IDLE state on the next pal_bx_clock assertion.
# 
# Test Sysreset functionality on for the State Machine
# ====================================================
#   Cycles 24-31
#   ------------
#   A VME IO cycle is performed for this card.
#
#   Cycle 28(31)
#   ------------
#   SYS_RESET is asserted and the state machine is put in the IDLE state. 
#   NEXT_STATE_QUIESCENT is asserted and DRV_DTACK is deasserted.  There is a 3 cycle
#   latency from VME_SYSRESET_B assertion and the SYSRESET_DEBOUNCED assertion.


set cycle 132

set 1_cycle  [expr $cycle*1]ns
set 2_cycles [expr $cycle*2]ns
set 3_cycles [expr $cycle*3]ns
set 4_cycles [expr $cycle*4]ns
set 5_cycles [expr $cycle*5]ns
set 6_cycles [expr $cycle*6]ns
set 7_cycles [expr $cycle*7]ns
set 8_cycles [expr $cycle*8]ns
set 9_cycles [expr $cycle*9]ns
set 10_cycles [expr $cycle*10]ns
# restart simulation without confirming and clearing wave window.
restart -force -nowave

# Add signals to wave window.
do state_machine_waves.do

# Set clock to 0 initially.
force /bcp/pal_bx_clock_in_stdl 0

# Define clock cycle.
force /bcp/pal_bx_clock_in_stdl 1 66ns, 0 132ns -r 132ns

#=====================================================================================
# Cycle 0
#=====================================================================================
# Set DS1 to 0 initially (rcvd_ds1 to 0).
force /bcp/rcvd_ds1_in_stdl 0

# Set sysreset to 0 (VME_SYSRESET_B to 1).
force /bcp/vme_sysreset_b_in_stdl 1

# Set LTCHD_AM, VME_GEO_B, and IACK_B so that VALID_CYCLE is deasserted.
# Valid cycle will start out deasserted but will go undetermined on the 
# first rising edge because the inputs to its flip flop are undetermined 
# otherwise.

force /bcp/ltchd_am_in_stdlv 100111
force /bcp/vme_geo_b_in_stdlv 10000
force /bcp/ocb_adrs_in_stdlv 16#000000
force /bcp/ocb_adrs_in_stdlv(18:22) 11111
force /bcp/ltchd_iack_b_in_stdl 0

#=====================================================================================
# Cycles 1-2
#=====================================================================================
run $2_cycles

# Assert DS1, thus starting a VME I/O cycle.
# STATE Machine should go from IDLE -> LATCH_1 -> LATCH_2 -> IDLE since
# VALID_CYCLE is deasserted.
# VME_LTCHD_CLK should be asserted in the LATCH_1 state.
force /bcp/rcvd_ds1_in_stdl 1

#=====================================================================================
# Cycles 3-7
#=====================================================================================
run $9_cycles

# Deassert DS1 ending VME I/O cycle.
# There is a 3 cycle deleay between rcvd_ds1 and ds1_int
force /bcp/rcvd_ds1_in_stdl 0

#=====================================================================================
# Cycle
#=====================================================================================
run $3_cycles

# Set LTCHD_AM, VME_GEO_B, and IACK_B so that VALID_CYCLE is asserted.
force /bcp/ocb_adrs_in_stdlv(18:22) 01111

#=====================================================================================
# Cycle 
#=====================================================================================
run $1_cycle

# Assert DS1, thus starting a VME I/O cycle.
# STATE Machine should go from IDLE -> LATCH_1 -> LATCH_2 -> IO_1
# -> IO_2 since VALID_CYCLE is asserted.
# DRV_DTACK should be asserted.
# VME_LTCH_CLK should be asserted in the LATCH_1 state.

force /bcp/rcvd_ds1_in_stdl 1

#=====================================================================================
# Cycles
#=====================================================================================
run $6_cycles

# Deassert DS1 ending VME I/O cycle.
# DRV_DTACK should be deasserted and the state machine should return
# to the IDLE state.
force /bcp/rcvd_ds1_in_stdl 0

#=====================================================================================
# Cycles
#=====================================================================================
run $2_cycles

# Assert DS1, thus starting a VME I/O cycle.
# STATE Machine should go from IDLE -> LATCH_1 -> LATCH_2 -> IO_1
# -> IO_2 since VALID_CYCLE is asserted.
# DRV_DTACK should be asserted.
# VME_LTCH_CLK should be asserted in the LATCH_1 state.

force /bcp/rcvd_ds1_in_stdl 1

#=====================================================================================
# Cycles
#=====================================================================================
run $6_cycles

# Assert vme_sysreset_b.  IDLE should be asserted and all other states 
# should be desserted.

force /bcp/vme_sysreset_b_in_stdl 0

#=====================================================================================
# Cycles
#=====================================================================================
run $4_cycles