-- board_control_pal_firmware.vhd
-- created:       22-Jun-2004
-- last modified: 16-Feb-2005


------------------------------------------------------------------------------------
--  This is a vhdl structural implementation of the ADF-2 PAL firmware.  See
--  http://www.pa.msu.edu/hep/d0/ftp/run2b/l1cal/hardware/adf2/
--         drawings/adf_2_pal_signal_heirarchy.pdf and ps
--         drawings/adf_2_pal_top_level_schematic.pdf and ps
--         drawings/clock_bx_x8_generation.pdf and ps
--         general/board_control_pal_implementation.txt
------------------------------------------------------------------------------------

------------------------------------------------------------------------------------
--  Signal naming conventions
--
--  <SIGNAL NAME>_<direction>_<type>
--
--   Signal Name is a descriptive name of the signal
--   direction is either in, out, or inout
--   type is the signal type   
--      stdl  STD_LOGIC
--      stdlv STD_LOGIC_VECTOR
------------------------------------------------------------------------------------

------------------------------------------------------------------------------------
--  Singal Keep constraint values
--
--  Some signals have the keep constraint attached to them to prevent their logic
--  from being collapsed during the implementation process.  This helps make better
--  use of the CPLD resources by increasing the number of macrocells used a little 
--  and by greatly reducing the number of inputs needed to functional blocks.
------------------------------------------------------------------------------------

------------------------------------------------------------------------------------
--  DFF Power Up values
--
--  The power up values of the flip flops are set with the INIT attribute in the body
--  VHDL code when the flip flop is instanced.  
------------------------------------------------------------------------------------

------------------------------------------------------------------------------------
--  Bi directional pins
--
--  Bi-directional pins are implemented using the IOBUFE primitive from the Xilinx
--  library.  The OCB_DATA signals use this primitive.
------------------------------------------------------------------------------------

------------------------------------------------------------------------------------
--  Tri-Stated outputs
--
--  Tri-stated outputs are implemented using the OBUFE primitive from the Xilinx
--  library.  The PAL_ACCESS signals use this primitive.
------------------------------------------------------------------------------------

------------------------------------------------------------------------------------
--  File Organization
--
--  This VHDL design file is organized as follows:
--
--    Library and Package Declarations
--   -entity
--    Design entity declaration
--      Singal INPUT and OUTPUT decalations
--   -end
--   -architecture
--    Internal Signal Declarations
--      D inputs to Flip Flops
--      Q outputs from Flip Flops
--      Inverted input signals
--      Other internal signals
--      LED Stretcher Signals and Parameters
--    Constrain definistions
--      keep statements
--   -begin
--    Inverted signal definitions
--    Signal Definitions (Divided into functional sections and listed in alphabetical
--                        order)
--      VME INTERFACE
--        BOARD_CONTROL_REGISTER_1_SEL
--        BOARD_CONTROL_REGISTER_2_SEL 
--        BOARD_STATUS_REGISTER_1_SEL
--        BOARD_STATUS_REGISTER_2_SEL
--        CNFG_CONTROL_REGISTER_SEL
--        CNFG_STATUS_REGISTER_SEL
--        DATA_BUF_DIR
--        DATA_BUF_ENB_B
--        DRV_DTACK
--        DS1
--        IDLE_STATE
--        IO_1_STATE
--        IO_2_STATE
--        LATCH_1_STATE
--        LATCH_2_STATE
--        NEXT_STATE_QUIESCENT
--        OCB_CHIP_SEL(0:2)
--        OCB_CHIP_SEL_B(0:2)
--        OCB_DATA_OUTPUT_ENABLE
--        OCB_DIRECTION
--        OCB_WRITE_STROBE_B
--        PAL_LED(0)
--        PAL_REGISTER(0:15)
--        SET_QUIESCENT_STATE
--        SYSRESET_DEBOUNCED
--        THIS_CARD_int_stdl
--        VALID_AM_int_stdl 
--        VALID_CYCLE_int_stdl 
--        VME_LTCH_CLK
--        WRITE_TO_PAL 
--      BOARD LEVEL CONTROL
--        ADC_ENABLE
--        BOARD_CONTROL_DATA_1(0:7)
--        BOARD_CONTROL_DATA_2(0:7)
--        BOARD_STATUS_DATA_1(0:7)
--        BOARD_STATUS_2_DATA(0:7)
--        CONFIGURE_FPGAS
--        DAC_CHIP_SELECT_B_REQ
--        DAC_SERIAL_DATA_CLOCK
--        DATA_TO_FIRST_DAC_INPUT
--        DRV_CRATE_TO_SCLD(0:1)
--        DRV_CRATE_STATUS_B(0:3)
--        PAL_LED(1)
--        SER_DC_BALANCE
--        SER_DESKEW_B
--      FPGA CONFIGURATION
--        CNFG_CCLK
--        CNFG_CS_B(0:1)
--        CNFG_CONTROL_DATA(0:7)
--        CNFG_PROG_B(0:1)
--        CNFG_PROG_B_REQ(0:1)
--        CNFG_RDWR_B
--        CNFG_STATUS_DATA(0:7)
--        ENABLE_FPGA_CONFIGURATION
--        ENABLE_LOADING_DACS
--        LOAD_DACS 
--      BX X8 Clock Generation
--        CNT_BIT_VAL_1
--        CNT_BIT_VAL_2
--        CNT_BIT_VAL_4
--        LOOP_REF
--        PAL_FIRST_X8_EDGE
--        PHASE_DET_OUT
--        RCVD_BX_CLOCK
--      OCB Output
--        OCB_DATA(0:7)
--        OUTPUT_DATA(0:7)
--      PAL ACCESS 
--        PAL_ACCESS(0:16)
--   -end
------------------------------------------------------------------------------------

------------------------------------------------------------------------------------
-- The IEEE Standard Logic package is needed for STD_LOGIC and STD_LOGIC_VECTOR
-- signal types and operations.
-- IEEE.std_logic_unsigned is needed for the + operation on std_logic_vector.
------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;



------------------------------------------------------------------------------------
-- The unisim vcomponents package is needed for primitive components used in the
-- PAL such as the D Flip Flops and IO buffers.
------------------------------------------------------------------------------------
library unisim;
use unisim.vcomponents.all;

------------------------------------------------------------------------------------
-- My Xilinx library
-- This library contains counters obtained from the Xilinx Libraries Guide that need
-- to be infered rather than instantiated.
------------------------------------------------------------------------------------
library Xilinx_Components;
use Xilinx_Components.Counters.all;



entity bcp is
    port (


------------------------------------------------------------------------------------
--Inputs and Ouputs 
------------------------------------------------------------------------------------
  ADC_ENABLE_reg_stdl                    : inout   STD_LOGIC;                 
  PAL_BX_CLOCK_in_stdl                   : in      STD_LOGIC;
  CNFG_BUSY_in_stdlv                     : in      STD_LOGIC_VECTOR (0 to 1); 
  CNFG_CCLK_out_stdl                     : inout     STD_LOGIC;                 
  CNFG_CS_B_reg_stdlv                    : inout   STD_LOGIC_VECTOR (0 to 1); 
  CNFG_DONE_in_stdlv                     : in      STD_LOGIC_VECTOR (0 to 1); 
  CNFG_INIT_B_in_stdlv                   : in      STD_LOGIC_VECTOR (0 to 1); 
  CNFG_RDWR_B_reg_stdl                   : inout   STD_LOGIC; 
  CNFG_PROG_B_out_stdlv                  : inout     STD_LOGIC_VECTOR (0 to 1); 
  CNT_BIT_VAL_4_inout_stdl               : inout   STD_LOGIC;  
  CRATE_STATUS_B_in_stdlv                : in      STD_LOGIC_VECTOR (0 to 3); 
  DAC_CHIP_SELECT_B_out_stdl             : inout     STD_LOGIC;   
  DAC_SERIAL_DATA_CLOCK_out_stdl         : inout     STD_LOGIC;   
  DATA_BUF_DIR_out_stdl                  : inout     STD_LOGIC;   
  DATA_BUF_ENB_B_out_stdl                : inout     STD_LOGIC;                 
  DATA_TO_FIRST_DAC_INPUT_out_stdl       : out     STD_LOGIC;   
  DRV_CRATE_STATUS_reg_stdlv             : inout   STD_LOGIC_VECTOR (0 to 3); 
  DRV_CRATE_TO_SCLD_reg_stdlv            : inout   STD_LOGIC_VECTOR (0 to 1); 
  DRV_DTACK_out_stdl                     : inout     STD_LOGIC; 
  DRV_PAL_LED_out_stdlv                  : out     STD_LOGIC_VECTOR (0 to 1); 
  FPGA_1_STATUS_in_stdlv                 : in      STD_LOGIC_VECTOR (0 to 3); 
  FPGA_0_STATUS_in_stdlv                 : in      STD_LOGIC_VECTOR (0 to 3); 
  LAST_DAC_OUTPUT_DATA_in_stdl           : in      STD_LOGIC; 
  LOOP_FILTER_REF_inout_stdl             : inout   STD_LOGIC;  
  LTCHD_AM_in_stdlv                      : in      STD_LOGIC_VECTOR (0 to 5); 
  LTCHD_IACK_B_in_stdl                   : in      STD_LOGIC;  
  LTCHD_WRITE_B_in_stdl                  : in      STD_LOGIC;  
  OCB_ADRS_in_stdlv                      : in      STD_LOGIC_VECTOR (1 to 23);
  OCB_CHIP_SEL_B_out_stdlv               : inout     STD_LOGIC_VECTOR (0 to 1);
  OCB_DATA_inout_stdlv                   : inout   STD_LOGIC_VECTOR (0 to 7);
  OCB_DIRECTION_out_stdl                 : inout     STD_LOGIC;  
  OCB_WRITE_STRB_B_inout_stdl            : inout   STD_LOGIC;     
  PAL_ACCESS_out_stdlv                   : out     STD_LOGIC_VECTOR (0 to 16);
  PAL_BX_X8_CLOCK_in_stdl                : in      STD_LOGIC;              
  PAL_FIRST_X8_EDGE_out_stdl             : out     STD_LOGIC;      
  PHASE_DET_OUT_out_stdl                 : out     STD_LOGIC;       
  RCVD_BX_CLOCK_inout_stdl               : inout   STD_LOGIC;               
  RCVD_DS1_in_stdl                       : in      STD_LOGIC;               
  SER_DC_BALANCE_reg_stdl                : inout   STD_LOGIC;            
  SER_DESKEW_B_reg_stdl                  : inout   STD_LOGIC;              
  VME_GEO_B_in_stdlv                     : in      STD_LOGIC_VECTOR (0 to 4); 
  VME_LTCH_CLK_out_stdl                  : out     STD_LOGIC;               
  VME_SYSRESET_B_in_stdl                 : in      STD_LOGIC
  
           );
  
end bcp;

architecture bcp_structural of bcp is


------------------------------------------------------------------------------------
--Inverted and internal signals decalations
------------------------------------------------------------------------------------

--Flip Flop inputs

  signal D_ADC_ENABLE                         : STD_LOGIC;
  signal D_CNFG_CCLK                          : STD_LOGIC;
  signal D_CNFG_CS_B                          : STD_LOGIC_VECTOR(0 to 1);
  signal D_CNFG_PROG_B                        : STD_LOGIC_VECTOR(0 to 1);
  signal D_CNFG_PROG_B_REQ                    : STD_LOGIC_VECTOR(0 to 1);
  signal D_CNFG_RDWR_B                        : STD_LOGIC;
  signal D_CNT_BIT_VAL_1                      : STD_LOGIC;
  signal D_CNT_BIT_VAL_2                      : STD_LOGIC;
  signal D_CNT_BIT_VAL_4                      : STD_LOGIC;
  signal D_CNTRL_PAL_LED_1                    : STD_LOGIC;
  signal D_DAC_CHIP_SELECT_B                  : STD_LOGIC;
  signal D_DAC_CHIP_SELECT_B_REQ              : STD_LOGIC;
  signal D_DAC_SERIAL_DATA_CLOCK              : STD_LOGIC;
  signal D_DATA_BUF_DIR                       : STD_LOGIC;
  signal D_DATA_BUF_ENB_B                     : STD_LOGIC;
  signal D_DATA_TO_FIRST_DAC_INPUT            : STD_LOGIC;
  signal D_DRV_CRATE_TO_SCLD                  : STD_LOGIC_VECTOR(0 to 1);
  signal D_DRV_CRATE_STATUS                   : STD_LOGIC_VECTOR(0 to 3);
  signal D_DRV_DTACK                          : STD_LOGIC;
  signal D_DS1_TMP                            : STD_LOGIC;
  signal D_DS1                                : STD_LOGIC;
  signal D_ENABLE_FPGA_CONFIGURATION          : STD_LOGIC;
  signal D_ENABLE_LOADING_DACS                : STD_LOGIC;
  signal D_ENABLE_PAL_ACCESS_OUTPUT           : STD_LOGIC;
  signal D_IDLE_STATE                         : STD_LOGIC;
  signal D_IO_1_STATE                         : STD_LOGIC;
  signal D_IO_2_STATE                         : STD_LOGIC;
  signal D_LATCH_1_STATE                      : STD_LOGIC;
  signal D_LATCH_2_STATE                      : STD_LOGIC;
  signal D_NEXT_STATE_QUIESCENT               : STD_LOGIC;
  signal D_OCB_CHIP_SEL_B                     : STD_LOGIC_VECTOR(0 to 2);
  signal D_OCB_DATA_OUTPUT_ENABLE             : STD_LOGIC;
  signal D_OCB_DIRECTION                      : STD_LOGIC;
  signal D_OCB_WRITE_STRB_B                   : STD_LOGIC;
  signal D_PAL_FIRST_X8_EDGE                  : STD_LOGIC;
  signal D_SER_DC_BALANCE                     : STD_LOGIC;
  signal D_SER_DESKEW_B                       : STD_LOGIC;
  signal D_SET_QUIESCENT_STATE                : STD_LOGIC;
  signal D_VME_LTCH_CLK                       : STD_LOGIC;

--Flip Flop Outputs

  signal Q_OCB_DATA                           : STD_LOGIC_VECTOR(0 to 7);


--Inverted input signals

  signal PAL_BX_CLOCK_B_int_stdl              : STD_LOGIC;                 
  signal CNT_BIT_VAL_4_B_int_stdl             : STD_LOGIC;  
  signal LOOP_FILTER_REF_B_int_stdl           : STD_LOGIC;  
  signal LTCHD_AM_B_int_stdlv                 : STD_LOGIC_VECTOR (0 to 5);
  signal LTCHD_IACK_int_stdl                  : STD_LOGIC;
  signal LTCHD_WRITE_int_stdl                 : STD_LOGIC;  
  signal OCB_ADRS_B_int_stdlv                 : STD_LOGIC_VECTOR (1 to 23);
  signal RCVD_BX_CLOCK_DIV2_stdl              : STD_LOGIC;               
  signal RCVD_BX_CLOCK_DIV2_B_stdl            : STD_LOGIC;               
  signal VME_GEO_int_stdlv                    : STD_LOGIC_VECTOR (0 to 4);


--Internal signals

  signal BOARD_CONTROL_REGISTER_1_SEL_int_stdl         : STD_LOGIC;
  signal BOARD_CONTROL_REGISTER_1_SEL_B_int_stdl       : STD_LOGIC;
  signal BOARD_CONTROL_1_DATA_int_stdlv       : STD_LOGIC_VECTOR(0 to 7);
  signal BOARD_CONTROL_REGISTER_2_SEL_int_stdl         : STD_LOGIC;
  signal BOARD_CONTROL_REGISTER_2_SEL_B_int_stdl       : STD_LOGIC;
  signal BOARD_CONTROL_2_DATA_int_stdlv       : STD_LOGIC_VECTOR(0 to 7);
  signal BOARD_STATUS_REGISTER_1_SEL_int_stdl          : STD_LOGIC;
  signal BOARD_STATUS_REGISTER_1_SEL_B_int_stdl        : STD_LOGIC;
  signal BOARD_STATUS_1_DATA_int_stdlv        : STD_LOGIC_VECTOR(0 to 7);
  signal BOARD_STATUS_REGISTER_2_SEL_int_stdl          : STD_LOGIC;
  signal BOARD_STATUS_REGISTER_2_SEL_B_int_stdl        : STD_LOGIC;
  signal BOARD_STATUS_2_DATA_int_stdlv        : STD_LOGIC_VECTOR(0 to 7);
  signal CNFG_CONTROL_REGISTER_SEL_int_stdl            : STD_LOGIC;
  signal CNFG_CONTROL_REGISTER_SEL_B_int_stdl          : STD_LOGIC;
  signal CNFG_CONTROL_DATA_int_stdlv          : STD_LOGIC_VECTOR(0 to 7);
  signal CNFG_PROG_B_REQ_reg_stdlv            : STD_LOGIC_VECTOR (0 to 1); 
  signal CNFG_STATUS_REGISTER_SEL_int_stdl             : STD_LOGIC;
  signal CNFG_STATUS_REGISTER_SEL_B_int_stdl           : STD_LOGIC;
  signal CNFG_STATUS_DATA_int_stdlv           : STD_LOGIC_VECTOR(0 to 7);
  signal CNT_BIT_VAL_1_int_stdl               : STD_LOGIC;
  signal CNT_BIT_VAL_1_B_int_stdl             : STD_LOGIC;
  signal CNT_BIT_VAL_2_int_stdl               : STD_LOGIC;
  signal CNT_BIT_VAL_2_B_int_stdl             : STD_LOGIC;
  signal CNTRL_PAL_LED_1_reg_stdl             : STD_LOGIC;
  signal CNTRL_PAL_LED_1_B_reg_stdl           : STD_LOGIC;
  signal CONFIGURE_FPGAS_int_stdl             : STD_LOGIC;
  signal DAC_CHIP_SELECT_B_REQ_reg_stdl       : STD_LOGIC;   
  signal DAC_CHIP_SELECT_B_REQ_B_int_stdl     : STD_LOGIC;
  signal DS1_int_stdl                         : STD_LOGIC;
  signal DS1_B_int_stdl                       : STD_LOGIC;
  signal DS1_tmp_int_stdl                     : STD_LOGIC;
  signal ENABLE_FPGA_CONFIGURATION_reg_stdl   : STD_LOGIC;
  signal ENABLE_FPGA_CONFIGURATION_B_int_stdl : STD_LOGIC;
  signal ENABLE_LOADING_DACS_reg_stdl         : STD_LOGIC;
  signal ENABLE_LOADING_DACS_B_int_stdl       : STD_LOGIC;
  signal ENABLE_PAL_ACCESS_OUTPUT_reg_stdl    : STD_LOGIC;
  signal IDLE_STATE_int_stdl                  : STD_LOGIC;
  signal IDLE_STATE_B_int_stdl                : STD_LOGIC;
  signal IO_1_STATE_int_stdl                  : STD_LOGIC;
  signal IO_1_STATE_B_int_stdl                : STD_LOGIC;
  signal IO_2_STATE_int_stdl                  : STD_LOGIC;
  signal IO_2_STATE_B_int_stdl                : STD_LOGIC;
  signal LATCH_1_STATE_int_stdl               : STD_LOGIC;
  signal LATCH_1_STATE_B_int_stdl             : STD_LOGIC;
  signal LATCH_2_STATE_int_stdl               : STD_LOGIC;
  signal LATCH_2_STATE_B_int_stdl             : STD_LOGIC;
  signal LED_STRETCHER_CE_int_stdl            : STD_LOGIC;
  signal LED_STRETCHER_TC_int_stdl            : STD_LOGIC;
  signal LED_STRETCHER_COUNTER_IS_NOT_ZERO_int_stdl: STD_LOGIC;
  signal LED_STRETCHER_COUNTER_IS_ZERO_int_stdl: STD_LOGIC;
  signal LOAD_DACS_B_int_stdl                 : STD_LOGIC;
  signal LOAD_DACS_int_stdl                   : STD_LOGIC;
  signal NEXT_STATE_QUIESCENT_int_stdl        : STD_LOGIC;
  signal NEXT_STATE_QUIESCENT_B_int_stdl      : STD_LOGIC;
  signal OCB_CHIP_SEL_int_stdlv               : STD_LOGIC_VECTOR (0 to 2);
  signal OCB_CHIP_SEL_B_int_stdlv             : STD_LOGIC_VECTOR (0 to 2);
  signal OCB_DATA_int_stdlv                   : STD_LOGIC_VECTOR (0 to 7);
  signal OCB_DATA_OUTPUT_ENABLE_int_stdl      : STD_LOGIC;
  signal OCB_WRITE_STRB_int_stdl              : STD_LOGIC;
  signal OUTPUT_DATA_int_stdlv                : STD_LOGIC_VECTOR (0 to 7);
  signal PAL_ACCESS_int_stdlv                 : STD_LOGIC_VECTOR (0 to 16);
  signal PAL_REGISTER_int_stdlv               : STD_LOGIC_VECTOR (0 to 15);
--new  signal READ_FROM_PAL_int_stdl               : STD_LOGIC;
  signal SET_QUIESCENT_STATE_int_stdl         : STD_LOGIC;
  signal SET_QUIESCENT_STATE_B_int_stdl       : STD_LOGIC;
  signal SYSRESET_DEBOUNCED_int_stdl          : STD_LOGIC;
  signal SYSRESET_TMP_1_int_stdl              : STD_LOGIC;
  signal SYSRESET_TMP_2_int_stdl              : STD_LOGIC;
  signal SYSRESET_TMP_3_int_stdl              : STD_LOGIC;
  signal SYSRESET_TMP_4_int_stdl              : STD_LOGIC;
  signal THIS_CARD_int_stdl                   : STD_LOGIC;
--new  signal TURN_ON_LED_B_int_stdl               : STD_LOGIC;
  signal VALID_AM_int_stdl                    : STD_LOGIC;
  signal VALID_CYCLE_int_stdl                 : STD_LOGIC;
  signal VALID_CYCLE_B_int_stdl               : STD_LOGIC;
  signal WRITE_TO_PAL_int_stdl                : STD_LOGIC;
  signal WRITE_TO_PAL_B_int_stdl              : STD_LOGIC;


------------------------------------------------------------------------------------
--  LED Stretcher counter width
--  This value affects how long the LED will stay on.  
--  See board_control_pal_firmware_implementation.txt.
------------------------------------------------------------------------------------
--constant COUNTER_WIDTH : INTEGER := 14;
--constant COUNTER_WIDTH : INTEGER := 15;
constant COUNTER_WIDTH : INTEGER := 16;

------------------------------------------------------------------------------------
--  These are signals for the LED Stretcher circuit.
------------------------------------------------------------------------------------
  signal  LED_STRETCHER_Q_int_stdlv  :std_logic_vector(0 to COUNTER_WIDTH-1);
  signal  LED_STRETCHER_CEO:std_logic;



------------------------------------------------------------------------------------
-- Contraints
--  
------------------------------------------------------------------------------------
  attribute keep: string;

  attribute keep of  NEXT_STATE_QUIESCENT_int_stdl        : signal is "true"; 
  attribute keep of  NEXT_STATE_QUIESCENT_B_int_stdl      : signal is "true"; 
  attribute keep of  OCB_CHIP_SEL_int_stdlv               : signal is "true"; 
  attribute keep of  OCB_CHIP_SEL_B_int_stdlv             : signal is "true"; 
  attribute keep of  VALID_CYCLE_int_stdl                 : signal is "true"; 
  attribute keep of  VALID_CYCLE_B_int_stdl               : signal is "true"; 
  attribute keep of  WRITE_TO_PAL_int_stdl                : signal is "true"; 



begin
------------------------------------------------------------------------------------
--  Inverse signal definitions
------------------------------------------------------------------------------------
  BOARD_CONTROL_REGISTER_1_SEL_B_int_stdl <= 
                                          NOT BOARD_CONTROL_REGISTER_1_SEL_int_stdl;
  BOARD_CONTROL_REGISTER_2_SEL_B_int_stdl <= 
                                          NOT BOARD_CONTROL_REGISTER_2_SEL_int_stdl;
  BOARD_STATUS_REGISTER_1_SEL_B_int_stdl <= NOT BOARD_STATUS_REGISTER_1_SEL_int_stdl;
  BOARD_STATUS_REGISTER_2_SEL_B_int_stdl <= NOT BOARD_STATUS_REGISTER_2_SEL_int_stdl;
  CNFG_CONTROL_REGISTER_SEL_B_int_stdl   <= NOT CNFG_CONTROL_REGISTER_SEL_int_stdl;
  CNFG_STATUS_REGISTER_SEL_B_int_stdl    <= NOT CNFG_STATUS_REGISTER_SEL_int_stdl;
  CNTRL_PAL_LED_1_B_reg_stdl           <= NOT CNTRL_PAL_LED_1_reg_stdl;    
  CNT_BIT_VAL_1_B_int_stdl             <= NOT CNT_BIT_VAL_1_int_stdl;
  CNT_BIT_VAL_2_B_int_stdl             <= NOT CNT_BIT_VAL_2_int_stdl;
  CNT_BIT_VAL_4_B_int_stdl             <= NOT CNT_BIT_VAL_4_inout_stdl;
  DS1_B_int_stdl                       <= NOT DS1_int_stdl;
  ENABLE_LOADING_DACS_B_int_stdl       <= NOT ENABLE_LOADING_DACS_reg_stdl;
  ENABLE_FPGA_CONFIGURATION_B_int_stdl <= NOT ENABLE_FPGA_CONFIGURATION_reg_stdl; 
  IDLE_STATE_B_int_stdl                <= NOT IDLE_STATE_int_stdl;
  IO_1_STATE_B_int_stdl                <= NOT IO_1_STATE_int_stdl;  
  IO_2_STATE_B_int_stdl                <= NOT IO_2_STATE_int_stdl;  
  LATCH_1_STATE_B_int_stdl             <= NOT LATCH_1_STATE_int_stdl; 
  LATCH_2_STATE_B_int_stdl             <= NOT LATCH_2_STATE_int_stdl; 
  LED_STRETCHER_COUNTER_IS_ZERO_int_stdl 
                                  <= NOT LED_STRETCHER_COUNTER_IS_NOT_ZERO_int_stdl;
  LOAD_DACS_B_int_stdl                 <= NOT LOAD_DACS_int_stdl;
  LOOP_FILTER_REF_B_int_stdl           <= NOT LOOP_FILTER_REF_inout_stdl;
  LTCHD_AM_B_int_stdlv                 <= NOT LTCHD_AM_in_stdlv;        
  LTCHD_IACK_int_stdl                  <= NOT LTCHD_IACK_B_in_stdl;
  LTCHD_WRITE_int_stdl                 <= NOT LTCHD_WRITE_B_in_stdl;
  NEXT_STATE_QUIESCENT_B_int_stdl      <= NOT NEXT_STATE_QUIESCENT_int_stdl;
  OCB_ADRS_B_int_stdlv                 <= NOT OCB_ADRS_in_stdlv;
  OCB_CHIP_SEL_B_int_stdlv             <= NOT OCB_CHIP_SEL_int_stdlv;
  OCB_WRITE_STRB_int_stdl              <= NOT OCB_WRITE_STRB_B_inout_stdl;
  PAL_BX_CLOCK_B_int_stdl              <= NOT PAL_BX_CLOCK_in_stdl;
  RCVD_BX_CLOCK_DIV2_B_stdl            <= NOT RCVD_BX_CLOCK_DIV2_stdl;
  SET_QUIESCENT_STATE_B_int_stdl       <= NOT SET_QUIESCENT_STATE_int_stdl;  
--New  TURN_ON_LED_B_int_stdl           <= NOT LED_STRETCHER_COUNTER_IS_NOT_ZERO_int_stdl;
  VALID_CYCLE_B_int_stdl               <= NOT VALID_CYCLE_int_stdl;
  VME_GEO_int_stdlv                    <= NOT VME_GEO_B_in_stdlv;
  WRITE_TO_PAL_B_int_stdl              <= NOT WRITE_TO_PAL_int_stdl;


--XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
--XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX


--\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\
--VME INTERFACE SECTION
--//////////////////////////////////////////////////////////////////////////////////

--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--  BOARD_CONCTROL_REGISTER_1_SEL
--
--    This signal is asserted when the PAL is the target of the current IO cycle 
--    (OCB_CHIP_SEL(2) is asserted) and PAL Register 0 (Board Control Register 1) is 
--    the target.
------------------------------------------------------------------------------------
  BOARD_CONTROL_REGISTER_1_SEL_int_stdl <=     PAL_REGISTER_int_stdlv(0) 
                                  AND OCB_CHIP_SEL_int_stdlv(2);


--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--  BOARD_CONTROL_REGISTER_2_SEL 
--
--    This signal is asserted when the PAL is the target of the current IO cycle 
--    (OCB_CHIP_SEL(2) is asserted) and PAL Register 1 (Board Control Register 2) is 
--    the target.
------------------------------------------------------------------------------------
  BOARD_CONTROL_REGISTER_2_SEL_int_stdl <=     PAL_REGISTER_int_stdlv(1)
                                  AND OCB_CHIP_SEL_int_stdlv(2);

--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--  BOARD_STATUS_REGISTER_1_SEL 
--
--    This signal is asserted when the PAL is the target of the current IO cycle 
--    (OCB_CHIP_SEL(2) is asserted) and PAL Register 2 (Board Status Register 1) is 
--    the target.
------------------------------------------------------------------------------------
  BOARD_STATUS_REGISTER_1_SEL_int_stdl <=     PAL_REGISTER_int_stdlv(2)
                                 AND OCB_CHIP_SEL_int_stdlv(2);


--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--  BOARD_STATUS_REGISTER_2_SEL 
--
--    This signal is asserted when the PAL is the target of the current IO cycle 
--    (OCB_CHIP_SEL(2) is asserted) and PAL Register 3 (Board Status Register 2) is 
--    the target.
------------------------------------------------------------------------------------
  BOARD_STATUS_REGISTER_2_SEL_int_stdl <=     PAL_REGISTER_int_stdlv(3)
                                 AND OCB_CHIP_SEL_int_stdlv(2);



--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--  CNFG_CONTROL_REGISTER_SEL 
--
--    This signal is asserted when the PAL is the target of the current IO cycle 
--    (OCB_CHIP_SEL(2) is asserted) and PAL Register 5 (Configuration Control 
--    Register) is the target.
------------------------------------------------------------------------------------
  CNFG_CONTROL_REGISTER_SEL_int_stdl <=     PAL_REGISTER_int_stdlv(5)
                               AND OCB_CHIP_SEL_int_stdlv(2);



--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--  CNFG_STATUS_REGISTER_SEL 
--
--    This signal is asserted when the PAL is the target of the current IO cycle 
--    (OCB_CHIP_SEL(2) is asserted) and PAL Register 7 (Configuration Status 
--    Register) is the target.
------------------------------------------------------------------------------------

    CNFG_STATUS_REGISTER_SEL_int_stdl <=     
                            PAL_REGISTER_int_stdlv(7) AND OCB_CHIP_SEL_int_stdlv(2);


--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--  DATA_BUF_DIR
--
--    This is a latched signal that is updated on the rising edge of the 
--    PAL_BX_CLOCK.  It is quiescent high (read) and set low (write) 
--    during the LATCH_2, IO_1, IO_2, and SET_QUIESCENT states when LTCHD_WRITE_B
--    is deasserted low (write) and VALID_CYCLE is asserted.
--
--  D_DATA_BUF_DIR
--    The NEXT_STATE_QUIESCENT term sets DATA_BUF_DIR high during the IDLE and 
--    LATCH_1 states. The SET_QUIESCENT state sets DATA_BUF_DIR high for the first 
--    IDLE clock cycle after the completion of an IO cycle.  The third term 
--    (VALID_CYCLE_B OR LTCHD_WRITE_B) sets DATA_BUF_DIR high when the current IO 
--    cycyle is not valid or when the direction is read (LTCHD_WRITE_B asserted).
--
-- new D_DATA_BUF_DIR
-- new    The NEXT_STATE_QUIESCENT term sets DATA_BUF_DIR high during the IDLE and 
-- new    LATCH_1 states.  The third term (VALID_CYCLE_B OR LTCHD_WRITE_B) sets 
-- new    DATA_BUF_DIR high when the current IO cycyle is not valid or when the direction
-- new    is read (LTCHD_WRITE_B asserted).
-------------------------------------------------------------------------------------

  D_DATA_BUF_DIR  <=  SET_QUIESCENT_STATE_int_stdl
                  OR  NEXT_STATE_QUIESCENT_int_stdl 
                  OR  (VALID_CYCLE_B_int_stdl OR LTCHD_WRITE_B_in_stdl);

-- New  D_DATA_BUF_DIR  <=  NEXT_STATE_QUIESCENT_int_stdl  
-- New                  OR  (VALID_CYCLE_B_int_stdl OR LTCHD_WRITE_B_in_stdl);

  DATA_BUF_DIR_DFF: FDCP 
    generic map ( INIT => '1' )
    port map (    D    => D_DATA_BUF_DIR, 
                  PRE  => SYSRESET_DEBOUNCED_int_stdl,
                  CLR  => '0',
                  C    => PAL_BX_CLOCK_in_stdl,
                  Q    => DATA_BUF_DIR_out_stdl
             );
 

--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--  DATA_BUF_ENB_B
--
--    This is a latched signal that updates on the rising edge of the PAL_BX_CLOCK.
--    It is quiescent high and is asserted low during the LATCH_2, IO_1, IO_2, and 
--    SET_QUIESCENT states when VALID_CYCLE is asserted.
--
--  D_DATA_BUF_ENB_B
--    The NEXT_STATE_QUIESCENT term deasserts DATA_BUF_ENB_B during the IDLE and
--    LATCH_1 states.  The SET_QUIESCENT_STATE term deasserts DATA_BUF_ENB_B 
--    for the first IDLE cycle of the state machine after an IO cycle.  The term
--    VALID_CYCLE_B deasserts DATA_BUF_ENB_B when the current IO cycle is not valid.
--
-- new D_DATA_BUF_ENB_B
-- new    The NEXT_STATE_QUIESCENT term deasserts DATA_BUF_ENB_B during the IDLE and
-- new    LATCH_1 states.  
-- new    The term VALID_CYCLE_B deasserts DATA_BUF_ENB_B when the current IO cycle is not valid.
-------------------------------------------------------------------------------------
  
  
  D_DATA_BUF_ENB_B  <=  SET_QUIESCENT_STATE_int_stdl 
                    OR  NEXT_STATE_QUIESCENT_int_stdl  OR  VALID_CYCLE_B_int_stdl;

-- New  D_DATA_BUF_ENB_B  <=  NEXT_STATE_QUIESCENT_int_stdl   
-- New                    OR  VALID_CYCLE_B_int_stdl;

  DATA_BUF_ENB_B_DFF: FDCP 
    generic map ( INIT => '1' )
    port map (    D    => D_DATA_BUF_ENB_B,
                  PRE  => SYSRESET_DEBOUNCED_int_stdl,
                  CLR  => '0',
                  C    => PAL_BX_CLOCK_in_stdl,
                  Q    => DATA_BUF_ENB_B_out_stdl
             );


--+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--  DRV_DTACK 
--
--    This is a latched signal that updates on the rising edge of the 
--    PAL_BX_CLOCK.  DRV_DTACK is asserted high in the IO_2 and SET_QUIESCENT states 
--    when VALID_CYCLE is asserted.  DRV_DTACK is deasserted low by the assertion of 
--    SYSRESET_DEBOUNCED.  DRV_DTACK is deasserted low at powerup.
--
--  D_DRV_DTACK
--    The NEXT_STATE_QUIESCENT and the (IO_1_STATE OR IO_2_STATE) terms allows 
--    DRV_DTACK to be asserted only during the IO_2 and SET_QUIESCENT states.  The
--    VALID_CYCLE term allows DRV_DTACK to be asserted during a valid IO cycle.
-------------------------------------------------------------------------------------

  D_DRV_DTACK <= NEXT_STATE_QUIESCENT_B_int_stdl 
                 AND VALID_CYCLE_int_stdl AND 
                 (IO_1_STATE_int_stdl OR IO_2_STATE_int_stdl);


  DRV_DTACK_DFF: FDCP 
    generic map ( INIT => '0' )
    port map (    D    => D_DRV_DTACK,
                  CLR  => SYSRESET_DEBOUNCED_int_stdl,
                  PRE  => '0',
                  C    => PAL_BX_CLOCK_in_stdl,
                  Q    => DRV_DTACK_out_stdl
              );


--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--   DRV_PAL_LED(0)
--
--     This is a latched signal that updates on the rising edge of the PAL_BX_CLOCK.
--     This signal drives the PAL_LED_0.  The LED cathode is pulled to ground to 
--     turn on the LED, so the LED is on when this signal is low.  This signal is
--     controlled by the inverse of the output of the LED Stretcher circuit.  The
--     output of the LED Stretcher circuit is LED_STRETCHER_COUTNER_IS_NOT_ZERO
--     and its inverse is TURN_ON_LED_B.  TURN_ON_LED_B is asserted low for 2ms
--     after VALID_CYCLE is asserted high.
--
------------------------------------------------------------------------------------
--New DRV_PAL_LED_0_DFF: FDCP 
--New   generic map ( INIT => '1' )
--New   port map (    D => TURN_ON_LED_B_int_stdl,
--New                 PRE => SYSRESET_DEBOUNCED_int_stdl,
--New                 CLR => '0',
--New                 C => PAL_BX_CLOCK_in_stdl,
--New                 Q => DRV_PAL_LED_out_stdlv(0)
--New            );

  DRV_PAL_LED_0_DFF: FDCP 
    generic map ( INIT => '1' )
    port map (    D    => LED_STRETCHER_COUNTER_IS_ZERO_int_stdl,
                  PRE  => SYSRESET_DEBOUNCED_int_stdl,
                  CLR  => '0',
                  C    => PAL_BX_CLOCK_in_stdl,
                  Q    => DRV_PAL_LED_out_stdlv(0)
             );


--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--  DS1
--
--    This is a synchronized copy of RCVD_DS1.  RCVD_DS1 is not garanteed to 
--    be stable when the flip flop in the PAL samples it and the flip flop may
--    be in a metastable state.  The RCVD_DS1 signal is passed through two flip
--    flops to reduce the chance of the internal DS1 signal from being in a 
--    metastable state.
--    
--    The first flip flop is updated on the rising edge of PAL_BX_CLOCK and the 
--    second flip flop is updated on the falling edge of PAL_BX_CLOCK (rising 
--    edge of PAL_BX_CLOCK_B).
--
--                 +---+               +---+        
--      RCVD_DS1---|D Q|----DS1_TMP----|D Q|---DS1
--                 |   |               |   |
--  PAL_BX_CLOCK-+-|>  |             +-|>  |
--               | +---+             | +---+
--               |                   |
--               | +---+             |
--               +-|NOT|-------------+             
--                 +---+
--
-------------------------------------------------------------------------------------

  D_DS1_TMP <= RCVD_DS1_in_stdl;

  INT_DS1_DFF: FDCP 
    generic map ( INIT => '0' )
    port map (    D => D_DS1_TMP,
                  PRE => '0',
                  CLR => '0',
                  C => PAL_BX_CLOCK_in_stdl,
                  Q => DS1_TMP_int_stdl
             );

  D_DS1 <= DS1_TMP_int_stdl;

  DS1_DFF: FDCP 
    generic map ( INIT => '0' )
    port map (    D => D_DS1,
                  PRE => '0',
                  CLR => '0',
                  C => PAL_BX_CLOCK_B_int_stdl,
                  Q => DS1_int_stdl
             );

 
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--  IDLE_STATE
--
--    This is a latched signal that is updated on the rising edge of the 
--    PAL_BX_CLOCK and is asserted high.
--
--    This signal is part of the state machine and represents the IDLE state.  When
--    the state machine is in the IDLE state this signal is asserted.  It is asserted
--    in on the next PAL_BX_CLOCK rising edge under the following conditions.  See 
--    State Transition Truth Tables in implementation document.
-- 
-- 
--      
--      1) !IDLE_STATE * !LATCH_1_STATE * !LATCH_2_STATE * !IO_1_STATE * !IO_2_STATE*
--         !SET_QUIESCENT_STATE +
--           This is an invalid state because no state signals are asserted so the 
--           next state is the IDLE state.
--      2) !IDLE_STATE * !LATCH_1_STATE * !LATCH_2_STATE * !IO_1_STATE * !IO_2_STATE*
--          SET_QUIESCENT_STATE +
--           This state is valid state and by definition lasts one cycle and the 
--           next state is IDLE state.
--      3) !IDLE_STATE * !LATCH_1_STATE * !LATCH_2_STATE * !IO_1_STATE * (IO_2_STATE*
--          SET_QUIESCENT_STATE)+
--           This state is an invalid state becuase more than one state variable 
--           is asserted so the next state is IDLE state.
--      4) !IDLE_STATE * !LATCH_1_STATE * !LATCH_2_STATE *  IO_1_STATE * !IO_2_STATE*
--         !SET_QUIESCENT_STATE * !VALID_CYCLE +
--           This is an invalid state because the state machine is in the IO_1 state
--           but VALID_CYCLE is deasserted.  IO_1 state is defined to be asserted
--           only when VALID_CYCLE is asserted.
--      5) !IDLE_STATE * !LATCH_1_STATE * !LATCH_2_STATE *  IO_1_STATE * !IO_2_STATE*
--         !SET_QUIESCENT_STATE * !DS1 +
--           This is an invalid state because the current state is IO_1 but DS1 is 
--           deasserted.  DRV_DTACK is not asserted until after the IO_1 state so 
--           DS1 being deasserted in the IO_1 state is invalid therefore the next
--           state is IDLE.
--      6) !IDLE_STATE * !LATCH_1_STATE * !LATCH_2_STATE *  IO_1_STATE * (IO_2_STATE+
--          SET_QUIESCENT_STATE) +
--           This state is an invalid state becuase more than one state variable 
--           is asserted so the next state is IDLE state.
--      7) !IDLE_STATE * !LATCH_1_STATE *  LATCH_2_STATE * !IO_1_STATE * !IO_2_STATE 
--         !SET_QUIESCENT_STATE * !DS1 +
--           This is an invalid state because the current state is LATCH_2 but DS1 is
--           deasserted.  DRV_DTACK is not asserted until after the IO_1 state so 
--           DS1 being deasserted in the LATCH_2 state is invalid therefore the next
--           state is IDLE.
--      8) !IDLE_STATE * !LATCH_1_STATE *  LATCH_2_STATE * (IO_1_STATE +  IO_2_STATE+
--          SET_QUIESCENT_STATE) +
--           This state is an invalid state becuase more than one state variable 
--           is asserted so the next state is IDLE state.
--      9) !IDLE_STATE *  LATCH_1_STATE * !LATCH_2_STATE * !IO_1_STATE * !IO_2_STATE 
--          * !DS1 +
--           This is an invalid state because the current state is LATCH_1 but DS1 is
--           deasserted.  DRV_DTACK is not asserted until after the IO_1 state so 
--           DS1 being deasserted in the LATCH_1 state is invalid therefore the next
--           state is IDLE.
--     10) !IDLE_STATE *  LATCH_1_STATE * (LATCH_2_STATE +  IO_1_STATE +  IO_2_STATE+
--          SET_QUIESCENT_STATE) +
--           This state is an invalid state becuase more than one state variable 
--           is asserted so the next state is IDLE state.
--     11)  IDLE_STATE * !LATCH_1_STATE * !LATCH_2_STATE * !IO_1_STATE * !IO_2_STATE 
--         !SET_QUIESCENT_STATE * !DS1 +
--           This is a valid state and means that the state machine is currently IDLE
--           and that the VME master has not initiated a VME IO cycle this cycle so
--           the next cycle will also be IDLE.
--     12)  IDLE_STATE * (LATCH_1_STATE +  LATCH_2_STATE +  IO_1_STATE +  IO_2_STATE)
--          SET_QUIESCENT_STATE)
--           This state is an invalid state becuase more than one state variable 
--           is asserted so the next state is IDLE state.
--
------------------------------------------------------------------------------------

  D_IDLE_STATE <= 
--                1
                  (    IDLE_STATE_B_int_stdl    AND LATCH_1_STATE_B_int_stdl 
                   AND LATCH_2_STATE_B_int_stdl AND IO_1_STATE_B_int_stdl 
                   AND IO_2_STATE_B_int_stdl    AND SET_QUIESCENT_STATE_B_int_stdl) 
                OR
--                2
                  (    IDLE_STATE_B_int_stdl    AND LATCH_1_STATE_B_int_stdl 
                   AND LATCH_2_STATE_B_int_stdl AND IO_1_STATE_B_int_stdl 
                   AND IO_2_STATE_B_int_stdl    AND SET_QUIESCENT_STATE_int_stdl)
                OR
--                3
                  (    IDLE_STATE_B_int_stdl    AND LATCH_1_STATE_B_int_stdl 
                   AND LATCH_2_STATE_B_int_stdl AND  IO_1_STATE_B_int_stdl 
                   AND IO_2_STATE_int_stdl      AND SET_QUIESCENT_STATE_int_stdl)
                OR
--                4
                  (    IDLE_STATE_B_int_stdl    AND LATCH_1_STATE_B_int_stdl 
                   AND LATCH_2_STATE_B_int_stdl AND IO_1_STATE_int_stdl 
                   AND IO_2_STATE_B_int_stdl    AND SET_QUIESCENT_STATE_B_int_stdl
                   AND VALID_CYCLE_B_int_stdl)
                OR
--                5
                  (    IDLE_STATE_B_int_stdl    AND LATCH_1_STATE_B_int_stdl 
                   AND LATCH_2_STATE_B_int_stdl AND IO_1_STATE_int_stdl 
                   AND IO_2_STATE_B_int_stdl    AND SET_QUIESCENT_STATE_B_int_stdl
                   AND DS1_B_int_stdl)
                OR
--                6
                  (    IDLE_STATE_B_int_stdl    AND LATCH_1_STATE_B_int_stdl 
                   AND LATCH_2_STATE_B_int_stdl AND IO_1_STATE_int_stdl 
                   AND(IO_2_STATE_int_stdl      OR  SET_QUIESCENT_STATE_int_stdl))
                 OR
--                7
                  (    IDLE_STATE_B_int_stdl   AND LATCH_1_STATE_B_int_stdl 
                   AND LATCH_2_STATE_int_stdl  AND IO_1_STATE_B_int_stdl 
                   AND IO_2_STATE_B_int_stdl   AND SET_QUIESCENT_STATE_B_int_stdl
                   AND DS1_B_int_stdl)
                 OR
--                8
                  (    IDLE_STATE_B_int_stdl   AND LATCH_1_STATE_B_int_stdl 
                   AND LATCH_2_STATE_int_stdl  AND (IO_1_STATE_int_stdl 
                   OR  IO_2_STATE_int_stdl     OR  SET_QUIESCENT_STATE_int_stdl))
                 OR
--                9
                  (    IDLE_STATE_B_int_stdl   AND LATCH_1_STATE_int_stdl 
                   AND LATCH_2_STATE_B_int_stdl AND IO_1_STATE_B_int_stdl  
                   AND IO_2_STATE_B_int_stdl   AND SET_QUIESCENT_STATE_B_int_stdl
                   AND DS1_B_int_stdl)
                 OR
--               10
                  (    IDLE_STATE_B_int_stdl    AND LATCH_1_STATE_int_stdl 
                   AND(LATCH_2_STATE_int_stdl   OR  IO_1_STATE_int_stdl 
                   OR  IO_2_STATE_int_stdl      OR SET_QUIESCENT_STATE_int_stdl))
                 OR
--               11
                  (    IDLE_STATE_int_stdl      AND LATCH_1_STATE_B_int_stdl 
                   AND LATCH_2_STATE_B_int_stdl AND IO_1_STATE_B_int_stdl  
                   AND IO_2_STATE_B_int_stdl    AND SET_QUIESCENT_STATE_B_int_stdl
                   AND DS1_B_int_stdl)
                 OR
--               12
                  (    IDLE_STATE_int_stdl      AND (LATCH_1_STATE_int_stdl 
                                                  OR LATCH_2_STATE_int_stdl 
                                                  OR  IO_1_STATE_int_stdl 
                                                  OR  IO_2_STATE_int_stdl
                                                  OR SET_QUIESCENT_STATE_int_stdl));

  IDLE_STATE_DFF: FDCP 
    generic map ( INIT => '1' )
    port map (    D    => D_IDLE_STATE,
                  PRE  => SYSRESET_DEBOUNCED_int_stdl,
                  CLR  => '0',
                  C    => PAL_BX_CLOCK_in_stdl,
                  Q    => IDLE_STATE_int_stdl
             );


--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--  IO_1_STATE
--    This is a latched signal that is updated on the rising edge of the PAL_BX_CLOCK
--    and is asserted high.  This signal represents the IO_1 state and is asserted
--    when the state machine is in the IO_1 state and deasserted when the state
--    machine is in any other state.
--
--    The IO_1 state follow the LATCH_2 state when DS1 and VALID_CYCLE are asserted.
--    If VALID_CYCLE is deasserted in the LATCH_2 state the state machine skips the 
--    IO_1 state and goes into the IO_2 state.  
------------------------------------------------------------------------------------

  D_IO_1_STATE <=     IDLE_STATE_B_int_stdl    AND LATCH_1_STATE_B_int_stdl 
                  AND LATCH_2_STATE_int_stdl   AND IO_1_STATE_B_int_stdl 
                  AND IO_2_STATE_B_int_stdl    AND SET_QUIESCENT_STATE_B_int_stdl
                  AND DS1_int_stdl             AND VALID_CYCLE_int_stdl;

  IO_1_STATE_DFF: FDCP 
    generic map ( INIT => '0' )
    port map (    D    => D_IO_1_STATE,
                  PRE  => '0',
                  CLR  => SYSRESET_DEBOUNCED_int_stdl,
                  C    => PAL_BX_CLOCK_in_stdl,
                  Q    => IO_1_STATE_int_stdl
              );
    

--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--  IO_2_STATE
--    This is a latched signal that is updated on the rising edge of the PAL_BX_CLOCK
--    and is asserted high.  This signal represents the IO_2 state of the state
--    machine.  When the state machine is in the IO_2 state this signal is asserted
--    and all other state signals are deasserted.
--
--    The IO_2 state is asserted during the next clock cycle if the current state is
--    IO_1 and VALID_CYCLE and DS1 are asserted, if the current state is LATCH_2
--    and VALID_CYCLE is deasserted and DS1 is asserted, or if the current state is
--    IO_2 and VALID_CYCLE and DS1 are asserted.
------------------------------------------------------------------------------------

  D_IO_2_STATE <= (    IDLE_STATE_B_int_stdl    AND LATCH_1_STATE_B_int_stdl     
                   AND LATCH_2_STATE_B_int_stdl AND IO_1_STATE_B_int_stdl 
                   AND IO_2_STATE_int_stdl      AND SET_QUIESCENT_STATE_B_int_stdl
                   AND DS1_int_stdl)
--New              AND VALID_CYCLE
--Check state table in implementation documentation
                 OR
                  (    IDLE_STATE_B_int_stdl    AND LATCH_1_STATE_B_int_stdl 
                   AND LATCH_2_STATE_B_int_stdl AND IO_1_STATE_int_stdl 
                   AND IO_2_STATE_B_int_stdl    AND SET_QUIESCENT_STATE_B_int_stdl
                   AND DS1_int_stdl             AND VALID_CYCLE_int_stdl)
                 OR
                  (    IDLE_STATE_B_int_stdl    AND LATCH_1_STATE_B_int_stdl 
                   AND LATCH_2_STATE_int_stdl   AND IO_1_STATE_B_int_stdl 
                   AND IO_2_STATE_B_int_stdl    AND SET_QUIESCENT_STATE_B_int_stdl
                   AND VALID_CYCLE_B_int_stdl);
--New              AND DS1
--Check state table in implementation documentation

  IO_2_STATE_DFF: FDCP 
    generic map ( INIT => '0' )
    port map (    D    => D_IO_2_STATE,
                  PRE  => '0',
                  CLR  => SYSRESET_DEBOUNCED_int_stdl,
                  C    => PAL_BX_CLOCK_in_stdl,
                  Q    => IO_2_STATE_int_stdl
              );
    

--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--  LATCH_1_STATE
--    This is a latched signal that is updated on the rising edge of the PAL_BX_CLOCK
--    signal and is asserted high.  This signal represents the LATCH_1 state of the 
--    state machine.  It is asserted when the state machine is in the LATCH_1 state
--    and deasserted otherwise.
--
--    The LATCH_1 state follows the IDLE state when DS1 is asserted.
------------------------------------------------------------------------------------

  D_LATCH_1_STATE <=     IDLE_STATE_int_stdl      AND LATCH_1_STATE_B_int_stdl 
                     AND LATCH_2_STATE_B_int_stdl AND IO_1_STATE_B_int_stdl 
                     AND IO_2_STATE_B_int_stdl    AND SET_QUIESCENT_STATE_B_int_stdl
                     AND DS1_int_stdl;

  LATCH_1_STATE_DFF: FDCP 
    generic map ( INIT => '0' )
    port map (    D    => D_LATCH_1_STATE,
                  PRE  => '0',
                  CLR  => SYSRESET_DEBOUNCED_int_stdl,
                  C    => PAL_BX_CLOCK_in_stdl,
                  Q    => LATCH_1_STATE_int_stdl
              );

    
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--  LATCH_2_STATE
--    This is a latched signal that is updated on the rising edge of the PAL_BX_CLOCK
--    signal and is asserted high.  This signal represents the LATCH_2 state of the
--    state machine.  It is asserted when the state machine is in the LATCH_2 state
--    and deasserted otherwise.
--
--    The LATCH_2 state follows the LATCH_1 state when DS1 is asserted.
------------------------------------------------------------------------------------

  D_LATCH_2_STATE <=     IDLE_STATE_B_int_stdl    AND LATCH_1_STATE_int_stdl 
                     AND LATCH_2_STATE_B_int_stdl AND IO_1_STATE_B_int_stdl 
                     AND IO_2_STATE_B_int_stdl    AND SET_QUIESCENT_STATE_B_int_stdl
                     AND DS1_int_stdl;

  LATCH_2_STATE_DFF: FDCP 
    generic map ( INIT => '0' )
    port map (    D    => D_LATCH_2_STATE,
                  PRE  => '0',
                  CLR  => SYSRESET_DEBOUNCED_int_stdl,
                  C    => PAL_BX_CLOCK_in_stdl,
                  Q    => LATCH_2_STATE_int_stdl
              );
    
    
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--  LED STRETCHER
--
--            +----------------LED_STRETCHER_COUNTER_IS_NOT_ZERO--------------+
--            |                                                               |
--            | +---+                      CBCE                               |
--            +-|   |                  +-----------+                   +---+  |
-- VALID_CYCLE--|OR |-LED_STRETCHER_CE-|CE  Q[15:0]|--LED_STRETHCER_Q--|OR |--+
--              +---+                  |           |                   +---+
--                                     |           |
-- PAL_BX_CLOCK------------------------|>C      CEO|-----------LED_STRETCHER_CEO
--                                     |           |
--                                     |           |
-- SYSRESET_DEBOUNCED------------------|CLR      TC|--LED_STRETCHER_TC
--                                     +-----------+
--
-- The LED Stretcher circuit takes the VALID_CYCLE signal and stretches is out in 
-- time.  The assertion of the VALID_CYCLE signal starts a 14-bit counter.  The
-- counter continues to count until it wraps around and VALID_CYCLE is not asserted.
-- The output of the circuit is a singal named LED_STRETCHER_COUNTER_IS_NOT_ZERO.
-- As the name implies, it is asserted when the counter is output is not zero.  The
-- output is asserted for 2^14(16384) clock cycles after VALID_CYCLE has been 
-- asserted.  This is about 2ms for a 132ns clock.
------------------------------------------------------------------------------------
    LED_STRETCHER_CE_int_stdl <= VALID_CYCLE_int_stdl OR 
                                 LED_STRETCHER_COUNTER_IS_NOT_ZERO_int_stdl;

    LED_STRETCHER_COUNTER_IS_NOT_ZERO_int_stdl <= 
                    LED_STRETCHER_Q_int_stdlv(0)  OR LED_STRETCHER_Q_int_stdlv(1)  OR
                    LED_STRETCHER_Q_int_stdlv(2)  OR LED_STRETCHER_Q_int_stdlv(3)  OR
                    LED_STRETCHER_Q_int_stdlv(4)  OR LED_STRETCHER_Q_int_stdlv(5)  OR
                    LED_STRETCHER_Q_int_stdlv(6)  OR LED_STRETCHER_Q_int_stdlv(7)  OR
                    LED_STRETCHER_Q_int_stdlv(8)  OR LED_STRETCHER_Q_int_stdlv(9)  OR
                    LED_STRETCHER_Q_int_stdlv(10) OR LED_STRETCHER_Q_int_stdlv(11) OR
                    LED_STRETCHER_Q_int_stdlv(12) OR LED_STRETCHER_Q_int_stdlv(13);

    LED_STRETCHER_CB16CE : CBCE
      generic map (WIDTH => COUNTER_WIDTH)
      port map (   CE    => LED_STRETCHER_CE_int_stdl,
                   C     => PAL_BX_CLOCK_in_stdl,
                   CLR   => SYSRESET_DEBOUNCED_int_stdl,
                   Q     => LED_STRETCHER_Q_int_stdlv,
                   CEO   => LED_STRETCHER_CEO,
                   TC    => LED_STRETCHER_TC_int_stdl
                );

--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--  NEXT_STATE_QUIESCENT
--    This signal is asserted if the current state is IDLE_STATE or 
--    SET_QUIESCENT_STATE and when VALID_CYCLE is deasserted.  It is used to drive a 
--    Flip Flop to its quiescent state during the IDLE_STATE and LATCH_1_STATE 
--    states.
--
--  D_NEXT_STATE_QUIESCENT
--    The first term (IDLE_STATE and DS1_B) sets NEXT_STATE_QUIESCENT high during the
--    IDLE state but low during the LATCH_1 state.  The SET_QUIESCNENT term sets
--    NEXT_STATE_QUIESCENT high during the first cycle that the state machine is in
--    the IDLE state after the completion of an IO cycle.  The third term 
--    (VALID_CYCLE_B AND (LATCH_2_STATE OR IO_2_STATE) sets NEXT_STATE_QUIESCENT 
--    high during the IO_2 state during and SET_QUIESCENT state during an invalid
--    io cycle.  The fourth term (VALID_CYCLE AND IO_2_STATE AND DS1_B) sets
--    NEXT_STATE_QUIESCENT high during a valid io cycle during the SET_QUIESCENT.
------------------------------------------------------------------------------------

     D_NEXT_STATE_QUIESCENT <=   (    IDLE_STATE_int_stdl 
                                 AND DS1_B_int_stdl) 
                             OR  SET_QUIESCENT_STATE_int_stdl
                             OR (    VALID_CYCLE_B_int_stdl 
                                 AND (    LATCH_2_STATE_int_stdl 
                                       OR IO_2_STATE_int_stdl))
                             OR (    VALID_CYCLE_int_stdl 
                                 AND IO_2_STATE_int_stdl
                                 AND DS1_B_int_stdl);
    
     NEXT_STATE_QUIESCENT_DFF: FDCP generic map ( INIT => '1' )
      port map (    D    => D_NEXT_STATE_QUIESCENT,
                    CLR  => '0',
                    PRE  => SYSRESET_DEBOUNCED_int_stdl,
                    C    => PAL_BX_CLOCK_in_stdl,
                    Q    => NEXT_STATE_QUIESCENT_int_stdl
               );
    
--New NEXT_STATE_QUIESCENT_int_stdl <=
--New                           IDLE_STATE_int_stdl
--New                       OR  LATCH_1_STATE_int_stdl
--New                       OR  VALID_CYCLE_B_int_stdl;
 
   
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--  OCB_CHIP_SEL(0:2)
--  ----------------- 
--  The OCB_CHIP_SEL(0:2) signals are internal positive logic (asserted high) signals
--  and ,through invertors, drive the negative logice (asserted low) external signals
--  OCB_CHIPS_SELECT_B(0:1) and the internal signal OCB_CHIP_SELECT_B(2).  These 
--  signals are asserted when VALID_CYCLE is asserted and DS1 is asserted and 
--  when the OCB_ADRS matches the values specified in the table below.  
--
--                     Address
--               +---------------------------------+
--   OCB_CHIP_SEL|1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0|
--      Target   |7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1|
--   +-----------+---------------------------------+
--   | 0: FPGA 0 |0 <--Not all 0's--------> x x x x|
--   | 1: FPGA 1 |1 <--Not all 0's--------> x x x x|
--   | 2: PAL    |0 0 0 0 0 0 0 0 0 0 0 0 0 x x x x|
--   +-----------+---------------------------------+
--
------------------------------------------------------------------------------------

  OCB_CHIP_SEL_int_stdlv(0) <=  OCB_ADRS_B_int_stdlv(17) 
                              AND
                                (OCB_ADRS_in_stdlv(16) OR  OCB_ADRS_in_stdlv(15) OR
                                 OCB_ADRS_in_stdlv(14) OR  OCB_ADRS_in_stdlv(13) OR
                                 OCB_ADRS_in_stdlv(12) OR  OCB_ADRS_in_stdlv(11) OR
                                 OCB_ADRS_in_stdlv(10) OR  OCB_ADRS_in_stdlv(9)  OR
                                 OCB_ADRS_in_stdlv(8)  OR  OCB_ADRS_in_stdlv(7)  OR
                                 OCB_ADRS_in_stdlv(6)  OR  OCB_ADRS_in_stdlv(5))
                              AND VALID_CYCLE_int_stdl;

  OCB_CHIP_SEL_int_stdlv(1) <=  OCB_ADRS_in_stdlv(17) 
                              AND
                                (OCB_ADRS_in_stdlv(16) OR  OCB_ADRS_in_stdlv(15) OR
                                 OCB_ADRS_in_stdlv(14) OR  OCB_ADRS_in_stdlv(13) OR
                                 OCB_ADRS_in_stdlv(12) OR  OCB_ADRS_in_stdlv(11) OR
                                 OCB_ADRS_in_stdlv(10) OR  OCB_ADRS_in_stdlv(9)  OR
                                 OCB_ADRS_in_stdlv(8)  OR  OCB_ADRS_in_stdlv(7)  OR
                                 OCB_ADRS_in_stdlv(6)  OR  OCB_ADRS_in_stdlv(5))
                              AND VALID_CYCLE_int_stdl;

  OCB_CHIP_SEL_int_stdlv(2) <=   OCB_ADRS_B_int_stdlv(17) 
                             AND OCB_ADRS_B_int_stdlv(16)
                             AND OCB_ADRS_B_int_stdlv(15) 
                             AND OCB_ADRS_B_int_stdlv(14)
                             AND OCB_ADRS_B_int_stdlv(13) 
                             AND OCB_ADRS_B_int_stdlv(12)
                             AND OCB_ADRS_B_int_stdlv(11)
                             AND OCB_ADRS_B_int_stdlv(10)
                             AND OCB_ADRS_B_int_stdlv(9)  
                             AND OCB_ADRS_B_int_stdlv(8)
                             AND OCB_ADRS_B_int_stdlv(7)  
                             AND OCB_ADRS_B_int_stdlv(6)
                             AND OCB_ADRS_B_int_stdlv(5)  
                             AND VALID_CYCLE_int_stdl;


--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--  OCB_CHIP_SEL_B(0:1)
--    These are latched signals that update on the rising edge of the PAL_BX_CLOCK
--    signal and are asserted low.  They are the external control signals for the
--    On Card Bus that go to FPGA0 and FPGA1.
--
--    These signals are asserted low the clock cycle after OCB_CHIP_SEL(0:1) are
--    asserted high.  These signals are deasserted high during the IDLE and LATCH_1
--    states.
--
--  D_OCB_CHIP_SEL_B
--    The NEXT_STATE_QUIESCENT term deasserts OCB_CHIP_SEL_B(0:1) during the IDLE and
--    LATCH_1 states.  The OCB_CHIP_SEL_B_int term asserts OCB_CHIP_SEL_B_out during
--    the LATCH_2, IO_1, IO_2, and SET_QUIESCENT states.
------------------------------------------------------------------------------------
 D_OCB_CHIP_SEL_B(0) <= NEXT_STATE_QUIESCENT_int_stdl OR OCB_CHIP_SEL_B_int_stdlv(0);

  OCB_CHIP_SEL_B_0_DFF: FDCP 
    generic map ( INIT => '1' )
    port map (    D    => D_OCB_CHIP_SEL_B(0),
                  PRE  => SYSRESET_DEBOUNCED_int_stdl,
                  CLR  => '0',
                  C    => PAL_BX_CLOCK_in_stdl,
                  Q    => OCB_CHIP_SEL_B_out_stdlv(0)
             );

 D_OCB_CHIP_SEL_B(1) <= NEXT_STATE_QUIESCENT_int_stdl OR OCB_CHIP_SEL_B_int_stdlv(1);

  OCB_CHIP_SEL_B_1_DFF: FDCP 
    generic map ( INIT => '1' )
    port map (    D    => D_OCB_CHIP_SEL_B(1),
                  PRE  => SYSRESET_DEBOUNCED_int_stdl,
                  CLR  => '0',
                  C    => PAL_BX_CLOCK_in_stdl,
                  Q    => OCB_CHIP_SEL_B_out_stdlv(1)
             );


--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--  OCB_DIRECTION
--    This is a latched signal that updates on the rising edge of the PAL_BX_CLOCK
--    signal and is quiescent high.  This is a control signal for the On Card Bus
--    that indicates the direction of the current IO cycle.  When high, the direction
--    is read from the On Card Bus target.  When low, the direction is write to the 
--    On Card Bus target.
--
--    This signal is quiescent high and is set low only during an IO cycle during
--    the LATCH_2, IO_1, IO_2 and SET_QUIESCENT states if LATCHD_WRITE_B is low and
--    VALID_CYCLE is asserted.
--
--  D_OCB_DIRECTION
--    The NEXT_STATE_QUIESCENT term sets OCB_DIRECTION high in the IDLE and LATCH_1
--    states.  The (LATCH_2_STATE AND VALID_CYCLE_B) term sets OCB_DIRECTION high
--    during the first cycle of the IO_2 state during an invalid IO cycle.  The 
--    (VALID_CYCLE AND LTCHD_WRITE_B term) sets OCB_DIRECTION high during a valid
--    cycle when LTCHD_WRITE_B is high (read).
--
-- new D_OCB_DIRECTION
-- new   The NEXT_STATE_QUIESCENT term sets OCB_DIRECTION high in the IDLE and LATCH_1
-- new   states.  The (VALID_CYCLE AND LTCHD_WRITE_B term) sets OCB_DIRECTION high 
-- new   during a valid cycle when LTCHD_WRITE_B is high (read).
------------------------------------------------------------------------------------

  D_OCB_DIRECTION  <=   NEXT_STATE_QUIESCENT_int_stdl
                   OR  (LATCH_2_STATE_int_stdl AND VALID_CYCLE_B_int_stdl)
                   OR  (VALID_CYCLE_int_stdl AND LTCHD_WRITE_B_in_stdl);

-- new  D_OCB_DIRECTION  <=   NEXT_STATE_QUIESCENT_int_stdl
-- new                   OR  (VALID_CYCLE_int_stdl AND LTCHD_WRITE_B_in_stdl);

  OCB_DIRECTION_DFF: FDCP 
    generic map ( INIT => '1' )
    port map (    D    => D_OCB_DIRECTION,
                  PRE  => SYSRESET_DEBOUNCED_int_stdl,
                  CLR  => '0',
                  C    => PAL_BX_CLOCK_in_stdl,
                  Q    => OCB_DIRECTION_out_stdl
             );


--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--  OCB_WRITE_STRB_B
--    This is a latched signal that is updated on the rising edge of the PAL_BX_CLOCK
--    signal and is asserted low.  This is the clock signal for the On Card Bus.  
--    Writes are defined to happen the on falling edge of this signal.
--
--    OCB_WRITE_STRB_B is high during invalid IO cycles, valid read IO cycles and
--    during the LATCH_1, LATCH_2, IO_2 and SET_QUIESCENT states of a valid write
--    IO cycle.  It is only asserted low during the IO_1 state when the current IO
--    cycle is valid and a write to an On Card Bus target.
--
--  D_OCB_WRITE_STRB_B
--    The NEXT_STATE_QUIESCENT term deasserts OCB_WRITE_STRB_B during the IDLE and
--    LATCH_1 states.  The term (NOT(LATCH_2_STATE AND (OCB_CHIP_SEL(0) OR 
--    OCB_CHIP_SEL(1) OR OCB_CHIP_SEL(2)) deasserts OCB_WRITE_STRB when not in the
--    IO_1 state, or when LTCHD_WRITE_B is the read direction, or when the target
--    is not the PAL (OCB_CHIP_SEL(2)) or the FPGAs (OCB_CHIP_SEL(0:1)) on this card.
--    
-- new D_OCB_WRITE_STRB_B
-- new   The NEXT_STATE_QUIESCENT term deasserts OCB_WRITE_STRB_B during the IDLE and
-- new   LATCH_1 states.  The term (NOT(LATCH_2_STATE AND (OCB_CHIP_SEL(0) OR 
-- new   OCB_CHIP_SEL(1) OR OCB_CHIP_SEL(2)) deasserts OCB_WRITE_STRB when not in the
-- new   IO_1 state, or when LTCHD_WRITE_B is the read direction, or when the current
-- new   IO cycle is valid.
------------------------------------------------------------------------------------

  D_OCB_WRITE_STRB_B <=  NEXT_STATE_QUIESCENT_int_stdl 
                         OR 
                         NOT  (LATCH_2_STATE_int_stdl AND LTCHD_WRITE_int_stdl
                               AND 
                               ( OCB_CHIP_SEL_int_stdlv(0) OR 
                                 OCB_CHIP_SEL_int_stdlv(1) OR
                                 OCB_CHIP_SEL_int_stdlv(2))
                           );

-- new  D_OCB_WRITE_STRB_B <=  NEXT_STATE_QUIESCENT_int_stdl 
-- new                         OR 
-- new                         NOT  (LATCH_2_STATE_int_stdl AND LTCHD_WRITE_int_stdl
-- new                               AND VALID_CYCLE
-- new                           );

  OCB_WRITE_STRB_B_DFF: FDCP 
    generic map ( INIT => '1' )
    port map (    D    => D_OCB_WRITE_STRB_B,
                  PRE  => SYSRESET_DEBOUNCED_int_stdl,
                  CLR  => '0',
                  C    => PAL_BX_CLOCK_in_stdl,
                  Q    => OCB_WRITE_STRB_B_inout_stdl
             );


--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- PAL_REGISTER(0:15)
--
--  This array represents the decoding of the lower address bits OCB_ADRS(1:4).
--  An element of the array is asserted when its index matches the OCB_ADRS decoding.
--
--    PAL_REGISTER(0)  = !OCB_ADRS(4) * !OCB_ADRS(3) * !OCB_ADRS(2) * !OCB_ADRS(1)
--    PAL_REGISTER(1)  = !OCB_ADRS(4) * !OCB_ADRS(3) * !OCB_ADRS(2) *  OCB_ADRS(1)
--    PAL_REGISTER(2)  = !OCB_ADRS(4) * !OCB_ADRS(3) *  OCB_ADRS(2) * !OCB_ADRS(1)
--    PAL_REGISTER(3)  = !OCB_ADRS(4) * !OCB_ADRS(3) *  OCB_ADRS(2) *  OCB_ADRS(1)
--    PAL_REGISTER(4)  = !OCB_ADRS(4) *  OCB_ADRS(3) * !OCB_ADRS(2) * !OCB_ADRS(1)
--    PAL_REGISTER(5)  = !OCB_ADRS(4) *  OCB_ADRS(3) * !OCB_ADRS(2) *  OCB_ADRS(1)
--    PAL_REGISTER(6)  = !OCB_ADRS(4) *  OCB_ADRS(3) *  OCB_ADRS(2) * !OCB_ADRS(1)
--    PAL_REGISTER(7)  = !OCB_ADRS(4) *  OCB_ADRS(3) *  OCB_ADRS(2) *  OCB_ADRS(1)
--    PAL_REGISTER(8)  =  OCB_ADRS(4) * !OCB_ADRS(3) * !OCB_ADRS(2) * !OCB_ADRS(1)
--    PAL_REGISTER(9)  =  OCB_ADRS(4) * !OCB_ADRS(3) * !OCB_ADRS(2) *  OCB_ADRS(1)
--    PAL_REGISTER(10) =  OCB_ADRS(4) * !OCB_ADRS(3) *  OCB_ADRS(2) * !OCB_ADRS(1)
--    PAL_REGISTER(11) =  OCB_ADRS(4) * !OCB_ADRS(3) *  OCB_ADRS(2) *  OCB_ADRS(1)
--    PAL_REGISTER(12) =  OCB_ADRS(4) *  OCB_ADRS(3) * !OCB_ADRS(2) * !OCB_ADRS(1)
--    PAL_REGISTER(13) =  OCB_ADRS(4) *  OCB_ADRS(3) * !OCB_ADRS(2) *  OCB_ADRS(1)
--    PAL_REGISTER(14) =  OCB_ADRS(4) *  OCB_ADRS(3) *  OCB_ADRS(2) * !OCB_ADRS(1)
--    PAL_REGISTER(15) =  OCB_ADRS(4) *  OCB_ADRS(3) *  OCB_ADRS(2) *  OCB_ADRS(1)
--
--    +-------+---------+--------------------------------+ 
--    |Reg    | Addr Bit| Register                       |
--    |Address| 4 3 2 1 | Name                           |
--    +-------+---------+--------------------------------+
--    |   0   | 0 0 0 0 | Board Level Control Register #1|
--    |   1   | 0 0 0 1 | Board Level Control Register #2|
--    |   2   | 0 0 1 0 | Board Level Status  Register #1|
--    |   3   | 0 0 1 1 | Board Level Status  Register #2|
--    |   4   | 0 1 0 0 | Board Level DAC Data Register  |
--    |   5   | 0 1 0 1 | Configuration Control Register |
--    |   6   | 0 1 1 0 | Configuration Data Register    |
--    |   7   | 0 1 1 1 | Configuration Status Register  |
--    +-------+---------+--------------------------------+
--    |       | 1 x x x | Unused Addresses               |
--    +-------+---------+--------------------------------+
------------------------------------------------------------------------------------

 PAL_REGISTER_int_stdlv(0)  <=    OCB_ADRS_B_int_stdlv(4) AND OCB_ADRS_B_int_stdlv(3)
                             AND OCB_ADRS_B_int_stdlv(2) AND OCB_ADRS_B_int_stdlv(1);
 PAL_REGISTER_int_stdlv(1)  <=    OCB_ADRS_B_int_stdlv(4) AND OCB_ADRS_B_int_stdlv(3)
                              AND OCB_ADRS_B_int_stdlv(2) AND OCB_ADRS_in_stdlv(1);
 PAL_REGISTER_int_stdlv(2)  <=    OCB_ADRS_B_int_stdlv(4) AND OCB_ADRS_B_int_stdlv(3)
                              AND OCB_ADRS_in_stdlv(2)   AND OCB_ADRS_B_int_stdlv(1);
 PAL_REGISTER_int_stdlv(3)  <=    OCB_ADRS_B_int_stdlv(4) AND OCB_ADRS_B_int_stdlv(3)
                              AND OCB_ADRS_in_stdlv(2)   AND OCB_ADRS_in_stdlv(1);
 PAL_REGISTER_int_stdlv(4)  <=    OCB_ADRS_B_int_stdlv(4) AND OCB_ADRS_in_stdlv(3) 
                             AND OCB_ADRS_B_int_stdlv(2) AND OCB_ADRS_B_int_stdlv(1);
 PAL_REGISTER_int_stdlv(5)  <=    OCB_ADRS_B_int_stdlv(4) AND OCB_ADRS_in_stdlv(3) 
                              AND OCB_ADRS_B_int_stdlv(2) AND OCB_ADRS_in_stdlv(1);
 PAL_REGISTER_int_stdlv(6)  <=    OCB_ADRS_B_int_stdlv(4) AND OCB_ADRS_in_stdlv(3) 
                              AND OCB_ADRS_in_stdlv(2)   AND OCB_ADRS_B_int_stdlv(1);
 PAL_REGISTER_int_stdlv(7)  <=    OCB_ADRS_B_int_stdlv(4) AND OCB_ADRS_in_stdlv(3) 
                              AND OCB_ADRS_in_stdlv(2)   AND OCB_ADRS_in_stdlv(1);
 PAL_REGISTER_int_stdlv(8)  <=    OCB_ADRS_in_stdlv(4)   AND OCB_ADRS_B_int_stdlv(3) 
                             AND OCB_ADRS_B_int_stdlv(2) AND OCB_ADRS_B_int_stdlv(1);
 PAL_REGISTER_int_stdlv(9)  <=    OCB_ADRS_in_stdlv(4)   AND OCB_ADRS_B_int_stdlv(3) 
                              AND OCB_ADRS_B_int_stdlv(2) AND OCB_ADRS_in_stdlv(1);
 PAL_REGISTER_int_stdlv(10) <=    OCB_ADRS_in_stdlv(4)   AND OCB_ADRS_B_int_stdlv(3) 
                              AND OCB_ADRS_in_stdlv(2)   AND OCB_ADRS_B_int_stdlv(1);
 PAL_REGISTER_int_stdlv(11) <=    OCB_ADRS_in_stdlv(4)   AND OCB_ADRS_B_int_stdlv(3) 
                              AND OCB_ADRS_in_stdlv(2)   AND OCB_ADRS_in_stdlv(1);
 PAL_REGISTER_int_stdlv(12) <=    OCB_ADRS_in_stdlv(4)   AND OCB_ADRS_in_stdlv(3) 
                             AND OCB_ADRS_B_int_stdlv(2) AND OCB_ADRS_B_int_stdlv(1);
 PAL_REGISTER_int_stdlv(13) <=    OCB_ADRS_in_stdlv(4)   AND OCB_ADRS_in_stdlv(3) 
                              AND OCB_ADRS_B_int_stdlv(2) AND OCB_ADRS_in_stdlv(1);
 PAL_REGISTER_int_stdlv(14) <=    OCB_ADRS_in_stdlv(4)   AND OCB_ADRS_in_stdlv(3) 
                              AND OCB_ADRS_in_stdlv(2)   AND OCB_ADRS_B_int_stdlv(1);
 PAL_REGISTER_int_stdlv(15) <=    OCB_ADRS_in_stdlv(4)   AND OCB_ADRS_in_stdlv(3) 
                              AND OCB_ADRS_in_stdlv(2)   AND  OCB_ADRS_in_stdlv(1);
                   
                      
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--  READ_FORM_PAL 
--    This signal indicates that the current IO cycle is a read cycle to the PAL.
--    This is indicated by OCB_CHIP_SEL(2) being asserted and LTCHD_WRITE being
--    deasserted.
------------------------------------------------------------------------------------

-- new  READ_FROM_PAL_int_stdl <= OCB_CHIP_SEL_int_stdlv(2) AND LTCHD_WRITE_B_in_stdl;


--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--  SET_QUIESCENT_STATE
--    This is a latched signal that is updated on the rising edge of the PAL_BX_CLOCK
--    signal and is asserted high.  This signal represents the SET_QUIESCENT state of
--    the state machine.  It is asserted when the state machine is in the 
--    SET_QUIESCENT state and deasserted otherwise.
--
--    The SET_QUIESCENT state follows the IO_2 state when DS1 is deasserted.
-------------------------------------------------------------------------------------

  D_SET_QUIESCENT_STATE <=     IDLE_STATE_B_int_stdl    AND LATCH_1_STATE_B_int_stdl 
                     AND LATCH_2_STATE_B_int_stdl AND IO_1_STATE_B_int_stdl 
                     AND IO_2_STATE_int_stdl    AND SET_QUIESCENT_STATE_B_int_stdl
                     AND DS1_B_int_stdl ;

  SET_QUIESCENT_STATE_DFF: FDCP 
    generic map ( INIT => '0' )
    port map (    D    => D_SET_QUIESCENT_STATE,
                  PRE  => '0',
                  CLR  => SYSRESET_DEBOUNCED_int_stdl,
                  C    => PAL_BX_CLOCK_in_stdl,
                  Q    => SET_QUIESCENT_STATE_int_stdl
              );
    
    
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--  SYSRESET_DEBOUNCED
--    This signal is a debounced copy of VME_SYSRESET_B.  VME_SYSRESET_B must be
--    deasserted for 3 clock cycles for SYS_RESET_DEBOUNCED to be asserted.  There
--    is a 3 cycle latancy for assertion and deassertion of SYSRESET_DEBOUNCED.
--
--
--                   +-----+        +-----+        +-----+     
--  VME_SYSRESET_B-+-|D1 Q1|-TMP1-+-|D2 Q2|-TMP2-+-|D3 Q3|--+
--                 | |     |      | |     |      | |     | TMP3
--  PAL_BX_CLOCK-+---|>    |     +--|>    |   +----|>    |  | +---+                  
--               | | +-----+     || +-----+   |  | +-----+  +-|   |
--               +---------------+------------+  +------------|OR |-TMP4-+
--                 |              +---------------------------|   |      |           
--                 +------------------------------------------|   |      |           
--                                                            +---+      |
--                                                         +-------------+
--                                                         | +---+
--                                                         +-|NOT|-SYSRESET_DEBOUNCED
--                                                           +---+
--
------------------------------------------------------------------------------------

  SYS_RESET_DFF_1: FDCP 
    generic map ( INIT => '1' )
    port map (    D    => VME_SYSRESET_B_in_stdl,
                  PRE  => '0',
                  CLR  => '0',
                  C    => PAL_BX_CLOCK_in_stdl,
                  Q    => SYSRESET_TMP_1_int_stdl
             );

  SYS_RESET_DFF_2: FDCP 
    generic map ( INIT => '1' )
    port map (    D    => SYSRESET_TMP_1_int_stdl,
                  PRE  => '0',
                  CLR  => '0',
                  C    => PAL_BX_CLOCK_in_stdl,
                  Q    => SYSRESET_TMP_2_int_stdl
             );

  SYS_RESET_DFF_3: FDCP 
    generic map ( INIT => '1' )
    port map (    D    => SYSRESET_TMP_2_int_stdl,
                  PRE  => '0',
                  CLR  => '0',
                  C    => PAL_BX_CLOCK_in_stdl,
                  Q    => SYSRESET_TMP_3_int_stdl
             );

  SYSRESET_TMP_4_int_stdl <= VME_SYSRESET_B_in_stdl OR SYSRESET_TMP_1_int_stdl
                             OR SYSRESET_TMP_2_int_stdl OR SYSRESET_TMP_3_int_stdl;

  SYSRESET_DEBOUNCED_int_stdl <= NOT SYSRESET_TMP_4_int_stdl;


------------------------------------------------------------------------------------
--  THIS_CARD 
--    This signal is asserted when the VME_GEO signals match the OCB_ADRS(18:22)
--    signals and OCB_ADRS(23) is low.
------------------------------------------------------------------------------------
  THIS_CARD_int_stdl <= ((OCB_ADRS_in_stdlv(18) AND VME_GEO_int_stdlv(0)) 
                          OR 
                         (OCB_ADRS_B_int_stdlv(18) AND VME_GEO_B_in_stdlv(0)) 
                        )
                        AND
                        ((OCB_ADRS_in_stdlv(19) AND VME_GEO_int_stdlv(1)) 
                          OR 
                         (OCB_ADRS_B_int_stdlv(19) AND VME_GEO_B_in_stdlv(1)) 
                        )
                        AND
                        ((OCB_ADRS_in_stdlv(20) AND VME_GEO_int_stdlv(2)) 
                          OR 
                         (OCB_ADRS_B_int_stdlv(20) AND VME_GEO_B_in_stdlv(2)) 
                        )
                        AND
                        ((OCB_ADRS_in_stdlv(21) AND VME_GEO_int_stdlv(3)) 
                          OR 
                         (OCB_ADRS_B_int_stdlv(21) AND VME_GEO_B_in_stdlv(3)) 
                        )
                        AND
                        ((OCB_ADRS_in_stdlv(22) AND VME_GEO_int_stdlv(4)) 
                         OR 
                          (OCB_ADRS_B_int_stdlv(22) AND VME_GEO_B_in_stdlv(4))
                        ) 
                        AND
                           OCB_ADRS_B_int_stdlv(23);

                  
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--  VALID_AM
--    This signal is asserted when the address modifier is either Standard 
--    Non-Privileged Data Access (LTCHD_AM(0:5) = 100111) or Standard Supervisory 
--    Data Access (LTCHD_AM(0:5) = 101111).
------------------------------------------------------------------------------------
  VALID_AM_int_stdl <= (LTCHD_AM_in_stdlv(0) AND LTCHD_AM_B_int_stdlv(1) AND 
                        LTCHD_AM_B_int_stdlv(2) AND  LTCHD_AM_in_stdlv(3) AND 
                        LTCHD_AM_in_stdlv(4) AND LTCHD_AM_in_stdlv(5)) 
                      OR
                       (LTCHD_AM_in_stdlv(0) AND LTCHD_AM_B_int_stdlv(1) AND 
                        LTCHD_AM_in_stdlv(2) AND LTCHD_AM_in_stdlv(3) AND 
                        LTCHD_AM_in_stdlv(4) AND LTCHD_AM_in_stdlv(5));


--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--  VALID_CYCLE indicates that the current VME IO cycle is valid for this card. 
--  VALID_CYCLE is asserted high in the LATCH_1, LATCH_2, IO_1, IO_2 and 
--  SET_QUIESCENT states when VALID_AM, THIS_CARD and LTCHD_IACK_B are asserted.
------------------------------------------------------------------------------------

--NEW  VALID_CYCLE_int_stdl <=     VALID_AM_int_stdl 
--NEW                          AND THIS_CARD_int_stdl 
--NEW                          AND LTCHD_IACK_B_in_stdl 
--NEW                          AND 
--NEW                              (   LATCH_1_STATE_int_stdl 
--NEW                               OR LATCH_2_STATE_int_stdl 
--NEW                               OR IO_1_STATE_int_stdl 
--NEW                               OR IO_2_STATE_int_stdl 
--NEW                               OR SET_QUIESCENT_STATE_int_stdl
--NEW                              );

     VALID_CYCLE_int_stdl <= VALID_AM_int_stdl AND THIS_CARD_int_stdl AND 
                           LTCHD_IACK_B_in_stdl AND 
                           (LATCH_1_STATE_int_stdl OR LATCH_2_STATE_int_stdl OR 
                            IO_1_STATE_int_stdl OR IO_2_STATE_int_stdl OR
                            SET_QUIESCENT_STATE_int_stdl
                           );


--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--  VME_LTCH_CLK
--    This is a latched signal that is updated on the rising edge of the PAL_BX_CLOCK
--    signal and is asserted high.  The risign edge of this signal latches to capture
--    the VME_AM, VME_ADDR, VME_IACK_B, and VME_WRITE_B signals.  These signals are
--    captured when an IO cycle is initiated by the VME master.
--
--    The VME_LTCH_CLK pulses high during the LATCH_1 state.  This occurs when during
--    the IDLE state DS1 is asserted.
------------------------------------------------------------------------------------

  D_VME_LTCH_CLK <= IDLE_STATE_int_stdl AND DS1_int_stdl;

  VME_LTCH_CLK_DFF: FDCP 
    generic map ( INIT => '0' )
    port map (    D    => D_VME_LTCH_CLK,
                  CLR  => SYSRESET_DEBOUNCED_int_stdl,
                  PRE  => '0',
                  C    => PAL_BX_CLOCK_in_stdl,
                  Q    => VME_LTCH_CLK_out_stdl
             );


--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--  WRITE_TO_PAL 
--    This signal indicates that the current IO cycle is a write cycle to the PAL.
--    This is indicated by OCB_CHIP_SEL(2) being asserted and LTCHD_WRITE being
--    asserted.
------------------------------------------------------------------------------------

  WRITE_TO_PAL_int_stdl <= OCB_CHIP_SEL_int_stdlv(2) AND LTCHD_WRITE_int_stdl;




--\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\
--//////////////////////////////////////////////////////////////////////////////////
--BOARD CONTROL SECTION
--\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\
--//////////////////////////////////////////////////////////////////////////////////

--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--  ADC_ENABLE
--    This is a latched signal that is updated on the rising edge of the PAL_BX_CLOCK
--    signal.  This signal is bit 7 of the Board Control Register # 1.
--
--  D_ADC_ENBABLE
--    The first term sets the register bit to the OCB value. This occurs when the 
--    WRITE_TO_PAL is asserted, the BOARD_CONTROL_REGISTER_1_SEL is asserted and when
--    OCB_WRITE_STRB is asserted.
--    The second term keeps the current value of ADC_ENABLE when 
--    BOARD_CONTROL_REGISTER_1_SEL is asserted but WRITE_STRB_B is deasserted.
--    The third term keeps the current value of ADC_ENABLE when 
--    BOARD_CONTROL_REGISTER_1_SEL is deasserted.
------------------------------------------------------------------------------------
  D_ADC_ENABLE <= (OCB_DATA_int_stdlv(7) AND WRITE_TO_PAL_int_stdl
                   AND BOARD_CONTROL_REGISTER_1_SEL_int_stdl 
                   AND OCB_WRITE_STRB_int_stdl) 
               OR (ADC_ENABLE_reg_stdl AND OCB_WRITE_STRB_B_inout_stdl 
                   AND BOARD_CONTROL_REGISTER_1_SEL_int_stdl)
-- new                OR (ADC_ENABLE_reg_stdl AND OCB_WRITE_STRB_B_inout_stdl)
               OR (ADC_ENABLE_reg_stdl AND BOARD_CONTROL_REGISTER_1_SEL_B_int_stdl);

  ADC_ENABLE_DFF: FDCP 
    generic map ( INIT => '0' )
    port map (    D    => D_ADC_ENABLE,
                  CLR  => SYSRESET_DEBOUNCED_int_stdl,
                  PRE  => '0',
                  C    => PAL_BX_CLOCK_in_stdl,
                  Q    => ADC_ENABLE_reg_stdl
              );


--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--  BOARD_CONTROL_DATA_1(0:7)
--  -------------------------
--
--      Bit| Signal
--      ---+---------------
--       0 | SER_DESKEW_B
--       1 | SER_DC_BALANCE
--       2 | 
--       3 | CNTRL_PAL_LED_1
--       4 | ENABLE_FPGA_CONFIGURATION
--       5 | ENABLE_LOADING_DACS
--       6 | ENABLE_PAL_ACCESS_OUTPUT
--       7 | ADC_ENABLE
------------------------------------------------------------------------------------ 

  BOARD_CONTROL_1_DATA_int_stdlv(0) <= SER_DESKEW_B_reg_stdl;
  BOARD_CONTROL_1_DATA_int_stdlv(1) <= SER_DC_BALANCE_reg_stdl;
  BOARD_CONTROL_1_DATA_int_stdlv(2) <= '0';
  BOARD_CONTROL_1_DATA_int_stdlv(3) <= CNTRL_PAL_LED_1_reg_stdl;
  BOARD_CONTROL_1_DATA_int_stdlv(4) <= ENABLE_FPGA_CONFIGURATION_reg_stdl;
  BOARD_CONTROL_1_DATA_int_stdlv(5) <= ENABLE_LOADING_DACS_reg_stdl;
  BOARD_CONTROL_1_DATA_int_stdlv(6) <= ENABLE_PAL_ACCESS_OUTPUT_reg_stdl;
  BOARD_CONTROL_1_DATA_int_stdlv(7) <= ADC_ENABLE_reg_stdl;


--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--  BOARD_CONTROL_DATA_2(0:7)
--  -------------------------
--
--      Bit| Signal
--      ---+---------------
--       0 | DRV_CRATE_STATUS(0)
--       1 | DRV_CRATE_STATUS(1)
--       2 | DRV_CRATE_STATUS(2) 
--       3 | DRV_CRATE_STATUS(3) 
--       4 | DRV_CRATE_TO_SCLD(0)
--       5 | DRV_CRATE_TO_SCLD(1)
--       6 | DAC_CHIP_SELECT_B_REQ
--       7 | 
------------------------------------------------------------------------------------
      
  BOARD_CONTROL_2_DATA_int_stdlv(0) <= DRV_CRATE_STATUS_reg_stdlv(0);
  BOARD_CONTROL_2_DATA_int_stdlv(1) <= DRV_CRATE_STATUS_reg_stdlv(1);
  BOARD_CONTROL_2_DATA_int_stdlv(2) <= DRV_CRATE_STATUS_reg_stdlv(2);
  BOARD_CONTROL_2_DATA_int_stdlv(3) <= DRV_CRATE_STATUS_reg_stdlv(3);
  BOARD_CONTROL_2_DATA_int_stdlv(4) <= DRV_CRATE_TO_SCLD_reg_stdlv(0);
  BOARD_CONTROL_2_DATA_int_stdlv(5) <= DRV_CRATE_TO_SCLD_reg_stdlv(1);
  BOARD_CONTROL_2_DATA_int_stdlv(6) <= DAC_CHIP_SELECT_B_REQ_reg_stdl;
  BOARD_CONTROL_2_DATA_int_stdlv(7) <= '0';

--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--  BOARD_STATUS_DATA_1(0:7)
--  -------------------
--      
--      Bit| Signal
--      ---+---------------
--       0 | FPGA_0_STATUS(0)
--       1 | FPGA_0_STATUS(1)
--       2 | FPGA_0_STATUS(2)
--       3 | FPGA_0_STATUS(3)
--       4 | FPGA_1_STATUS(0)
--       5 | FPGA_1_STATUS(1)
--       6 | FPGA_1_STATUS(2)
--       7 | FPGA_1_STATUS(3) 
------------------------------------------------------------------------------------

  BOARD_STATUS_1_DATA_int_stdlv(0) <= FPGA_0_STATUS_in_stdlv(0);
  BOARD_STATUS_1_DATA_int_stdlv(1) <= FPGA_0_STATUS_in_stdlv(1);
  BOARD_STATUS_1_DATA_int_stdlv(2) <= FPGA_0_STATUS_in_stdlv(2);
  BOARD_STATUS_1_DATA_int_stdlv(3) <= FPGA_0_STATUS_in_stdlv(3);
  BOARD_STATUS_1_DATA_int_stdlv(4) <= FPGA_1_STATUS_in_stdlv(0);
  BOARD_STATUS_1_DATA_int_stdlv(5) <= FPGA_1_STATUS_in_stdlv(1);
  BOARD_STATUS_1_DATA_int_stdlv(6) <= FPGA_1_STATUS_in_stdlv(2);
  BOARD_STATUS_1_DATA_int_stdlv(7) <= FPGA_1_STATUS_in_stdlv(3);


--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--  BOARD_STATUS_2_DATA(0:7)
--  -------------------
--
--      Bit| Signal
--      ---+---------------
--       0 | CRATE_STATUS(0)
--       1 | CRATE_STATUS(1)
--       2 | CRATE_STATUS(2)
--       3 | CRATE_STATUS(3)
--       4 | LAST_DAC_OUTPUT_DATA
--       5 | 
--       6 |
--       7 | 
------------------------------------------------------------------------------------

  BOARD_STATUS_2_DATA_int_stdlv(0) <= CRATE_STATUS_B_in_stdlv(0);
  BOARD_STATUS_2_DATA_int_stdlv(1) <= CRATE_STATUS_B_in_stdlv(1);
  BOARD_STATUS_2_DATA_int_stdlv(2) <= CRATE_STATUS_B_in_stdlv(2);
  BOARD_STATUS_2_DATA_int_stdlv(3) <= CRATE_STATUS_B_in_stdlv(3);
  BOARD_STATUS_2_DATA_int_stdlv(4) <= LAST_DAC_OUTPUT_DATA_in_stdl;
  BOARD_STATUS_2_DATA_int_stdlv(5) <= '0';
  BOARD_STATUS_2_DATA_int_stdlv(6) <= '0';
  BOARD_STATUS_2_DATA_int_stdlv(7) <= '0';



--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--  CNTRL_PAL_LED_1
--    This is a latched signal that is updated on the rising edge of the 
--    PAL_BX_CLOCK signal.  This signal is bit 3 of the BOARD Control Register # 1.
--
--  D_CNTRL_PAL_LED_1
--    The first term sets the register bit to the OCB value. This occurs when the 
--    WRITE_TO_PAL is asserted, BOARD_CONTROL_REGISTER_1_SEL is asserted and when
--    OCB_WRITE_STRB is asserted.
--    The second term keeps the current value of CNTRL_PAL_LED_1(X) when 
--    BOARD_CONTROL_REGISTER_1_SEL is asserted but WRITE_STRB_B is deasserted.
--    The third term keeps the current value of CNTRL_PAL_LED_1(X) when 
--    BOARD_CONTROL_REGISTER_1_SEL is deasserted.
------------------------------------------------------------------------------------

  D_CNTRL_PAL_LED_1 <= (OCB_DATA_int_stdlv(3) 
                        AND WRITE_TO_PAL_int_stdl
                        AND BOARD_CONTROL_REGISTER_1_SEL_int_stdl 
                        AND OCB_WRITE_STRB_int_stdl) 
                    OR (CNTRL_PAL_LED_1_reg_stdl 
                        AND OCB_WRITE_STRB_B_inout_stdl
                        AND BOARD_CONTROL_REGISTER_1_SEL_int_stdl)
                    OR (CNTRL_PAL_LED_1_reg_stdl 
                        AND BOARD_CONTROL_REGISTER_1_SEL_B_int_stdl);

  CNTRL_PAL_LED_1_DFF: FDCP 
    generic map ( INIT => '0' )
    port map (    D    => D_CNTRL_PAL_LED_1,
                  PRE  => SYSRESET_DEBOUNCED_int_stdl,
                  CLR  => '0',
                  C    => PAL_BX_CLOCK_in_stdl,
                  Q    => CNTRL_PAL_LED_1_reg_stdl
              );

 
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--  CONFIGURE_FPGAS 
--    This signal is asserted when a write IO operation is performed on the 
--    Configuration Data Register (PAL_REGISTER(6) AND OCB_CHIP_SEL(2))and when the 
--    ENABLE_FPGA_CONFIGURATION bit is asserted.
--
-- new   This signal is asserted when a write IO operation is performed on the 
-- new   Configuration Data Register (PAL_REGISTER(6) AND WRITE_TO_PAL)and when the 
-- new   ENABLE_FPGA_CONFIGURATION bit is asserted.
------------------------------------------------------------------------------------
  CONFIGURE_FPGAS_int_stdl <=     PAL_REGISTER_int_stdlv(6)
                              AND ENABLE_FPGA_CONFIGURATION_reg_stdl
                              AND OCB_CHIP_SEL_int_stdlv(2);

-- new  CONFIGURE_FPGAS_int_stdl <=     PAL_REGISTER_int_stdlv(6)
-- new                              AND WRITE_TO_PAL_int_stdlv(2)
-- new                              AND ENABLE_FPGA_CONFIGURATION_reg_stdl;


--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--  DAC_CHIP_SELECT_B
--    This is a latched signal that is updated on the rising edge of the PAL_BX_CLOCK
--    signal and is asserted low.  This signal is asserted when ENABLE_LOADING_DACS_B
--    and DAC_CHIP_SEL_B_REQ are asserted. 
------------------------------------------------------------------------------------

  D_DAC_CHIP_SELECT_B <= ENABLE_LOADING_DACS_B_int_stdl 
                         OR DAC_CHIP_SELECT_B_REQ_reg_stdl;


  DAC_CHIP_SELECT_B_DFF: FDCP 
    generic map ( INIT => '1' )
    port map (    D    => D_DAC_CHIP_SELECT_B,
                  PRE  => SYSRESET_DEBOUNCED_int_stdl,
                  CLR  => '0',
                  C    => PAL_BX_CLOCK_in_stdl,
                  Q    => DAC_CHIP_SELECT_B_out_stdl
             );

 
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--  DAC_CHIP_SELECT_B_REQ
--    This is a latched signal that is updated on the rising edge of the PAL_BX_CLOCK
--    signal.  This signal is bit 6 of the Board Control Register # 2.
--
--  D_DAC_CHIP_SEL_B_REQ
--    The first term sets the register bit to the OCB value. This occurs when the 
--    WRITE_TO_PAL is asserted, the BOARD_CONTROL_REGISTER_2_SEL is asserted and when
--    OCB_WRITE_STRB is asserted.
--    The second term keeps the current value of DAC_CHIP_SELECT_B_REQ when 
--    BOARD_CONTROL_REGISTER_2_SEL is asserted but WRITE_STRB_B is deasserted.
--    The third term keeps the current value of DAC_CHIP_SELECT_B_REQ when 
--    BOARD_CONTROL_REGISTER_2_SEL is deasserted.
------------------------------------------------------------------------------------

  D_DAC_CHIP_SELECT_B_REQ <= (OCB_DATA_int_stdlv(6) 
                              AND WRITE_TO_PAL_int_stdl
                              AND BOARD_CONTROL_REGISTER_2_SEL_int_stdl 
                              AND OCB_WRITE_STRB_int_stdl)
                          OR (DAC_CHIP_SELECT_B_REQ_reg_stdl 
                              AND OCB_WRITE_STRB_B_inout_stdl
                              AND BOARD_CONTROL_REGISTER_2_SEL_int_stdl)
                          OR (DAC_CHIP_SELECT_B_REQ_reg_stdl 
                              AND BOARD_CONTROL_REGISTER_2_SEL_B_int_stdl);


  DAC_CHIP_SELECT_B_REQ_DFF: FDCP 
    generic map ( INIT => '1' )
    port map (    D    => D_DAC_CHIP_SELECT_B_REQ,
                  PRE  => SYSRESET_DEBOUNCED_int_stdl,
                  CLR  => '0',
                  C    => PAL_BX_CLOCK_in_stdl,
                  Q    => DAC_CHIP_SELECT_B_REQ_reg_stdl
             );

 
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--  DAC_SERIAL_DATA_CLOCK
--    This is a latched signal that is updated on the rising edge of the PAL_BX_CLOCK
--    signal and is asserted high.  It is a control signal for the DACs.  The DACs 
--    capture serial data on this signals rising edge. 
--
--    The DAC_SERIAL_DATA_CLOCK is asserted during the IO_1 state when LOAD_DACS is
--    asserted.
--  
--  D_DAC_SERIAL_DATA_CLOCK
--    The first term (NEXT_STATE_QUIESCENT) asserts DAC_SERIAL_DATA_CLOCK during the
--    IDLE and LATCH_1 states.  The second term (LATCH_2_STATE_B OR LTCHD_WRITE_B OR
--    LOAD_DACS_B) deasserts DAC_SERIAL_DATA_CLOCK during the IO_1 state when 
--    LTCHD_WRITE_B is asserted and LOAD_DACS is asserted.
--
-- new D_DAC_SERIAL_DATA_CLOCK
-- new   The first term (NEXT_STATE_QUIESCENT) deasserts DAC_SERIAL_DATA_CLOCK during 
-- new   the IDLE and LATCH_1 states.  The second term (LATCH_2_STATE AND LTCHD_WRITE 
-- new   AND LOAD_DACS) asserts DAC_SERIAL_DATA_CLOCK during the IO_1 state when 
-- new   LTCHD_WRITE_B is asserted and LOAD_DACS is asserted.
-------------------------------------------------------------------------------------

  D_DAC_SERIAL_DATA_CLOCK <= NEXT_STATE_QUIESCENT_int_stdl 
                           OR 
                             (LATCH_2_STATE_B_int_stdl 
                              OR LTCHD_WRITE_B_in_stdl OR LOAD_DACS_B_int_stdl);

-- new  D_DAC_SERIAL_DATA_CLOCK <= NEXT_STATE_QUIESCENT_int_stdl 
-- new                             AND
-- new                             (LATCH_2_STATE_int_stdl 
-- new                              AND LTCHD_WRITE_B_in_stdl 
-- new                              AND LOAD_DACS_B_int_stdl);

  DAC_SERIAL_DATA_CLOCK_DFF: FDCP 
    generic map ( INIT => '1' )
    port map (    D    => D_DAC_SERIAL_DATA_CLOCK,
                  PRE  => SYSRESET_DEBOUNCED_int_stdl,
                  CLR  => '0',
                  C    => PAL_BX_CLOCK_in_stdl,
                  Q    => DAC_SERIAL_DATA_CLOCK_out_stdl
             );

 
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--  DATA_TO_FIRST_DAC_INPUT
--    This is a latched signal that is updated on the rising edge of the PAL_BX_CLOCK
--    signal.  This signal is the serial data to the first dac in the DAC chain.
--
--    DATA_TO_FIRST_DAC_INPUT is a copy of the LSB of the OCB when a write is 
--    targeted to the DAC DATA REGISTER.
--
--  D_DATA_TO_FIRST_DAC_INPUT
--    The first term (NEXT_STATE_QUIESCENT) sets DATA_TO_FIRST_DAC_INPUT to '0' 
--    during the IDLE and LATCH_1 states.  The second term (LOAD_DACS AND 
--    OCB_DATA(0)) copies the data from the LSB of the OCB when to 
--    DATA_TO_FIRST_DAC_INPUT when LOAD_DACS is asserted.
-------------------------------------------------------------------------------------

  D_DATA_TO_FIRST_DAC_INPUT <=     NEXT_STATE_QUIESCENT_B_int_stdl 
                               AND (LOAD_DACS_int_stdl
                                    AND OCB_DATA_int_stdlv(0));

  DATA_TO_FIRST_DAC_INPUT_DFF: FDCP 
    generic map ( INIT => '0' )
    port map (    D    => D_DATA_TO_FIRST_DAC_INPUT,
                  CLR  => SYSRESET_DEBOUNCED_int_stdl,
                  PRE  => '0',
                  C    => PAL_BX_CLOCK_in_stdl,
                  Q    => DATA_TO_FIRST_DAC_INPUT_out_stdl
      );

    
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--  DRV_CRATE_TO_SCLD(0:1)
--    These are latched signals that are updated on the rising edge of the 
--    PAL_BX_CLOCK signal.  These signals are bits 4 and 5 of the BOARD Control
--    Register # 2.
--
--  D_DRV_CRASTE_TO_SCLD(X)
--    The first term sets the register bit to the OCB value. This occurs when the 
--    WRITE_TO_PAL is asserted, the BOARD_CONTROL_REGISTER_2_SEL is asserted and when
--    OCB_WRITE_STRB is asserted.
--    The second term keeps the current value of DRV_CRATE_TO_SCLD(X) when 
--    BOARD_CONTROL_REGISTER_2_SEL is asserted but WRITE_STRB_B is deasserted.
--    The third term keeps the current value of DRV_CRATE_TO_SCLD(X) when 
--    BOARD_CONTROL_REGISTER_2_SEL is deasserted.
-------------------------------------------------------------------------------------
  
  D_DRV_CRATE_TO_SCLD(0) <= (OCB_DATA_int_stdlv(4) 
                             AND WRITE_TO_PAL_int_stdl
                             AND BOARD_CONTROL_REGISTER_2_SEL_int_stdl 
                             AND OCB_WRITE_STRB_int_stdl) 
                         OR (DRV_CRATE_TO_SCLD_reg_stdlv(0) 
                             AND OCB_WRITE_STRB_B_inout_stdl
                             AND BOARD_CONTROL_REGISTER_2_SEL_int_stdl)
                         OR (DRV_CRATE_TO_SCLD_reg_stdlv(0) 
                             AND BOARD_CONTROL_REGISTER_2_SEL_B_int_stdl);

  DRV_CRATE_TO_SCLD_0_DFF: FDCP 
    generic map ( INIT => '0' )
    port map (    D    => D_DRV_CRATE_TO_SCLD(0),
                  PRE  => '0',
                  CLR  => SYSRESET_DEBOUNCED_int_stdl,
                  C    => PAL_BX_CLOCK_in_stdl,
                  Q    => DRV_CRATE_TO_SCLD_reg_stdlv(0)
             );
  
  D_DRV_CRATE_TO_SCLD(1) <= (OCB_DATA_int_stdlv(5) 
                             AND WRITE_TO_PAL_int_stdl
                             AND BOARD_CONTROL_REGISTER_2_SEL_int_stdl 
                             AND OCB_WRITE_STRB_int_stdl) 
                         OR (DRV_CRATE_TO_SCLD_reg_stdlv(1) 
                             AND OCB_WRITE_STRB_B_inout_stdl
                             AND BOARD_CONTROL_REGISTER_2_SEL_int_stdl)
                         OR (DRV_CRATE_TO_SCLD_reg_stdlv(1) 
                             AND BOARD_CONTROL_REGISTER_2_SEL_B_int_stdl);


  DRV_CRATE_TO_SCLD_1_DFF: FDCP 
    generic map ( INIT => '0' )
    port map (    D    => D_DRV_CRATE_TO_SCLD(1),
                  PRE  => '0',
                  CLR  => SYSRESET_DEBOUNCED_int_stdl,
                  C    => PAL_BX_CLOCK_in_stdl,
                  Q    => DRV_CRATE_TO_SCLD_reg_stdlv(1)
             );


--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--  DRV_CRATE_STATUS(0:3)
--    These are latched signals that are updated on the rising edge of the 
--    PAL_BX_CLOCK signal.  These signals are bits 0-3 of the BOARD Control
--    Register # 2.
--
--  D_DRV_CRASTE_STATUS(X)
--    The first term sets the register bit to the OCB value. This occurs when the 
--    WRITE_TO_PAL is asserted, the BOARD_CONTROL_REGISTER_2_SEL is asserted and when
--    OCB_WRITE_STRB is asserted.
--    The second term keeps the current value of DRV_CRATE_STATUS(X) when 
--    BOARD_CONTROL_REGISTER_2_SEL is asserted but WRITE_STRB_B is deasserted.
--    The third term keeps the current value of DRV_CRATE_STATUS(X) when 
--    BOARD_CONTROL_REGISTER_2_SEL is deasserted.
-------------------------------------------------------------------------------------

  D_DRV_CRATE_STATUS(0) <= (OCB_DATA_int_stdlv(0) AND WRITE_TO_PAL_int_stdl
                            AND BOARD_CONTROL_REGISTER_2_SEL_int_stdl 
                            AND OCB_WRITE_STRB_int_stdl) 
                        OR (DRV_CRATE_STATUS_reg_stdlv(0) 
                            AND OCB_WRITE_STRB_B_inout_stdl
                            AND BOARD_CONTROL_REGISTER_2_SEL_int_stdl)
                        OR (DRV_CRATE_STATUS_reg_stdlv(0) 
                            AND BOARD_CONTROL_REGISTER_2_SEL_B_int_stdl);

  DRV_CRATE_STATUS_0_DFF: FDCP 
    generic map ( INIT => '0' )
    port map (    D    => D_DRV_CRATE_STATUS(0),
                  PRE  => '0',
                  CLR  => SYSRESET_DEBOUNCED_int_stdl,
                  C    => PAL_BX_CLOCK_in_stdl,
                  Q    => DRV_CRATE_STATUS_reg_stdlv(0)
             );

  D_DRV_CRATE_STATUS(1) <= (OCB_DATA_int_stdlv(1) AND WRITE_TO_PAL_int_stdl
                            AND BOARD_CONTROL_REGISTER_2_SEL_int_stdl 
                            AND OCB_WRITE_STRB_int_stdl) 
                        OR (DRV_CRATE_STATUS_reg_stdlv(1) 
                            AND OCB_WRITE_STRB_B_inout_stdl
                            AND BOARD_CONTROL_REGISTER_2_SEL_int_stdl)
                        OR (DRV_CRATE_STATUS_reg_stdlv(1) 
                            AND BOARD_CONTROL_REGISTER_2_SEL_B_int_stdl);

  DRV_CRATE_STATUS_1_DFF: FDCP 
    generic map ( INIT => '0' )
    port map (    D    => D_DRV_CRATE_STATUS(1),
                  PRE  => '0',
                  CLR  => SYSRESET_DEBOUNCED_int_stdl,
                  C    => PAL_BX_CLOCK_in_stdl,
                  Q    => DRV_CRATE_STATUS_reg_stdlv(1)
             );

  D_DRV_CRATE_STATUS(2) <= (OCB_DATA_int_stdlv(2) AND WRITE_TO_PAL_int_stdl
                            AND BOARD_CONTROL_REGISTER_2_SEL_int_stdl 
                            AND OCB_WRITE_STRB_int_stdl) 
                        OR (DRV_CRATE_STATUS_reg_stdlv(2) 
                            AND OCB_WRITE_STRB_B_inout_stdl
                            AND BOARD_CONTROL_REGISTER_2_SEL_int_stdl)
                        OR (DRV_CRATE_STATUS_reg_stdlv(2) 
                            AND BOARD_CONTROL_REGISTER_2_SEL_B_int_stdl);
 
  DRV_CRATE_STATUS_2_DFF: FDCP 
    generic map ( INIT => '0' )
    port map (    D    => D_DRV_CRATE_STATUS(2),
                  PRE  => '0',
                  CLR  => SYSRESET_DEBOUNCED_int_stdl,
                  C    => PAL_BX_CLOCK_in_stdl,
                  Q    => DRV_CRATE_STATUS_reg_stdlv(2)
             );

  D_DRV_CRATE_STATUS(3) <= (OCB_DATA_int_stdlv(3) AND WRITE_TO_PAL_int_stdl
                            AND BOARD_CONTROL_REGISTER_2_SEL_int_stdl 
                            AND OCB_WRITE_STRB_int_stdl) 
                        OR (DRV_CRATE_STATUS_reg_stdlv(3) 
                            AND OCB_WRITE_STRB_B_inout_stdl
                            AND BOARD_CONTROL_REGISTER_2_SEL_int_stdl)
                        OR (DRV_CRATE_STATUS_reg_stdlv(3) 
                            AND BOARD_CONTROL_REGISTER_2_SEL_B_int_stdl);

  DRV_CRATE_STATUS_3_DFF: FDCP 
    generic map ( INIT => '0' )
    port map (    D    => D_DRV_CRATE_STATUS(3),
                  PRE  => '0',
                  CLR  => SYSRESET_DEBOUNCED_int_stdl,
                  C    => PAL_BX_CLOCK_in_stdl,
                  Q    => DRV_CRATE_STATUS_reg_stdlv(3)
              );


--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--  DRV_PAL_LED(1)
--    This is a latched signal that is updated on the rising edge of the PAL_BX_CLOCK
--    signal and it is asserted low.  This signal controls a front panel LED.
--
--    The LED is on when DRV_PAL_LED is low.  The input to the flip flops is
--    CNTRL_PAL_LED_1_B so that when a '1' is written in the register bit
--    CNTRL_PAL_LED_1 the LED is turned on.
------------------------------------------------------------------------------------
  DRV_PAL_LED_1_DFF: FDCP 
    generic map ( INIT => '1' )
    port map (    D    => CNTRL_PAL_LED_1_B_reg_stdl,
                  PRE  => SYSRESET_DEBOUNCED_int_stdl,
                  CLR  => '0',
                  C    => PAL_BX_CLOCK_in_stdl,
                  Q    => DRV_PAL_LED_out_stdlv(1)
             );

 
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--  ENABLE_FPGA_CONFIGURATION
--    This is a latched signal that is updated on the rising edge of the PAL_BX_CLOCK
--    signal.  This signal is bit 4 of the Board Control Register # 1.
--
--  D_ENABLE_FPGA_CONFIGURATION
--    The first term sets the register bit to the OCB value. This occurs when the 
--    WRITE_TO_PAL is asserted, the BOARD_CONTROL_REGISTER_1_SEL is asserted and when
--    OCB_WRITE_STRB is asserted.
--    The second term keeps the current value of ENABLE_FPGA_CONFIGURATION when 
--    BOARD_CONTROL_REGISTER_1_SEL is asserted but WRITE_STRB_B is deasserted.
--    The third term keeps the current value of ENABLE_FPGA_CONFIGURATION when 
--    BOARD_CONTROL_REGISTER_1_SEL is deasserted.
------------------------------------------------------------------------------------

  D_ENABLE_FPGA_CONFIGURATION <= (OCB_DATA_int_stdlv(4) AND WRITE_TO_PAL_int_stdl
                                  AND BOARD_CONTROL_REGISTER_1_SEL_int_stdl 
                                  AND OCB_WRITE_STRB_int_stdl) 
                              OR (ENABLE_FPGA_CONFIGURATION_reg_stdl 
                                  AND OCB_WRITE_STRB_B_inout_stdl
                                  AND BOARD_CONTROL_REGISTER_1_SEL_int_stdl)
                              OR (ENABLE_FPGA_CONFIGURATION_reg_stdl 
                                  AND BOARD_CONTROL_REGISTER_1_SEL_B_int_stdl);

  ENABLE_FPGA_CONFIGURATION_DFF: FDCP 
    generic map ( INIT => '0' )
    port map (    D    => D_ENABLE_FPGA_CONFIGURATION,
                  PRE  => '0',
                  CLR  => SYSRESET_DEBOUNCED_int_stdl,
                  C    => PAL_BX_CLOCK_in_stdl,
                  Q    => ENABLE_FPGA_CONFIGURATION_reg_stdl
              );

 
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--  ENABLE_LOADING_DACS
--    This is a latched signal that is updated on the rising edge of the PAL_BX_CLOCK
--    signal.  This signal is bit 5 of the Board Control Register # 1.
--
--  D_ENABLE_LOADING_DACS
--    The first term sets the register bit to the OCB value. This occurs when the 
--    WRITE_TO_PAL is asserted, the BOARD_CONTROL_REGISTER_1_SEL is asserted and when
--    OCB_WRITE_STRB is asserted.
--    The second term keeps the current value of ENABLE_LOADING_DACS when 
--    BOARD_CONTROL_REGISTER_1_SEL is asserted but WRITE_STRB_B is deasserted.
--    The third term keeps the current value of ENABLE_LOADING_DACS when 
--    BOARD_CONTROL_REGISTER_1_SEL is deasserted.
------------------------------------------------------------------------------------

  D_ENABLE_LOADING_DACS <= (OCB_DATA_int_stdlv(5) AND WRITE_TO_PAL_int_stdl
                            AND BOARD_CONTROL_REGISTER_1_SEL_int_stdl 
                            AND OCB_WRITE_STRB_int_stdl) 
                        OR (ENABLE_LOADING_DACS_reg_stdl 
                            AND OCB_WRITE_STRB_B_inout_stdl
                            AND BOARD_CONTROL_REGISTER_1_SEL_int_stdl)
                        OR (ENABLE_LOADING_DACS_reg_stdl 
                            AND BOARD_CONTROL_REGISTER_1_SEL_B_int_stdl);

  ENABLE_FPGA_LOADING_DACS_DFF: FDCP 
    generic map ( INIT => '0' )
    port map (    D    => D_ENABLE_LOADING_DACS,
                  PRE  => '0',
                  CLR  => SYSRESET_DEBOUNCED_int_stdl,
                  C    => PAL_BX_CLOCK_in_stdl,
                  Q    => ENABLE_LOADING_DACS_reg_stdl
              );


--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--  ENABLE_PAL_ACCESS_OUTPUT
--    This is a latched signal that is updated on the rising edge of the PAL_BX_CLOCK
--    signal.  This signal is bit 6 of the Board Control Register # 1.
--
--  D_ENABLE_PAL_ACCESS_OUTPUT
--    The first term sets the register bit to the OCB value. This occurs when the 
--    WRITE_TO_PAL is asserted, the BOARD_CONTROL_REGISTER_1_SEL is asserted and when
--    OCB_WRITE_STRB is asserted.
--    The second term keeps the current value of ENABLE_PAL_ACCESS_OUTPUT when 
--    BOARD_CONTROL_REGISTER_1_SEL is asserted but WRITE_STRB_B is deasserted.
--    The third term keeps the current value of ENABLE_PAL_ACCESS_OUTPUT when 
--    BOARD_CONTROL_REGISTER_1_SEL is deasserted.
------------------------------------------------------------------------------------

  D_ENABLE_PAL_ACCESS_OUTPUT <= (OCB_DATA_int_stdlv(6) AND WRITE_TO_PAL_int_stdl
                                 AND BOARD_CONTROL_REGISTER_1_SEL_int_stdl 
                                 AND OCB_WRITE_STRB_int_stdl) 
                             OR (ENABLE_PAL_ACCESS_OUTPUT_reg_stdl 
                                 AND OCB_WRITE_STRB_B_inout_stdl
                                 AND BOARD_CONTROL_REGISTER_1_SEL_int_stdl)
                             OR (ENABLE_PAL_ACCESS_OUTPUT_reg_stdl 
                                 AND BOARD_CONTROL_REGISTER_1_SEL_B_int_stdl);

  ENABLE_PAL_ACCESS_OUTPUT_DFF: FDCP 
    generic map ( INIT => '1' )
    port map (    D    => D_ENABLE_PAL_ACCESS_OUTPUT,
                  PRE  => '0', 
                  CLR  => SYSRESET_DEBOUNCED_int_stdl, 
                  C    => PAL_BX_CLOCK_in_stdl,
                  Q    => ENABLE_PAL_ACCESS_OUTPUT_reg_stdl
              );


--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--  LOAD_DACS 
--    This signal is asserted high when ENABLE_LOADING_DACS is asserted and when
--    data is written to the DAC DATA REGISTER (PAL_REGISTER(4)).
------------------------------------------------------------------------------------
    LOAD_DACS_int_stdl <=     PAL_REGISTER_int_stdlv(4)
                          AND ENABLE_LOADING_DACS_reg_stdl
                          AND OCB_CHIP_SEL_int_stdlv(2);

-- new    LOAD_DACS_int_stdl <=     PAL_REGISTER_int_stdlv(4)
-- new                          AND WRITE_TO_PAL
-- new                          AND ENABLE_LOADING_DACS_reg_stdl;


--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--  SER_DC_BALANCE
--    This is a latched signal that is updated on the rising edge of the PAL_BX_CLOCK
--    signal.  This signal is bit 1 of the Board Control Register # 1.
--
--  D_SER_DC_BALANCE
--    The first term sets the register bit to the OCB value. This occurs when the 
--    WRITE_TO_PAL is asserted, the BOARD_CONTROL_REGISTER_1_SEL is asserted and when
--    OCB_WRITE_STRB is asserted.
--    The second term keeps the current value of SER_DC_BALANCE when 
--    BOARD_CONTROL_REGISTER_1_SEL is asserted but WRITE_STRB_B is deasserted.
--    The third term keeps the current value of SER_DC_BALANCE when 
--    BOARD_CONTROL_REGISTER_1_SEL is deasserted.
------------------------------------------------------------------------------------

  D_SER_DC_BALANCE <= (OCB_DATA_int_stdlv(1) 
                       AND WRITE_TO_PAL_int_stdl
                       AND BOARD_CONTROL_REGISTER_1_SEL_int_stdl 
                       AND OCB_WRITE_STRB_int_stdl) 
                   OR (SER_DC_BALANCE_reg_stdl 
                       AND OCB_WRITE_STRB_B_inout_stdl
                       AND BOARD_CONTROL_REGISTER_1_SEL_int_stdl)
                   OR (SER_DC_BALANCE_reg_stdl 
                       AND BOARD_CONTROL_REGISTER_1_SEL_B_int_stdl);

  SER_DC_BALANCE_DFF: FDCP 
    generic map ( INIT => '0' )
    port map (    D    => D_SER_DC_BALANCE,
                  CLR  => SYSRESET_DEBOUNCED_int_stdl,
                  PRE  => '0',
                  C    => PAL_BX_CLOCK_in_stdl,
                  Q    => SER_DC_BALANCE_reg_stdl
             );
 

--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--  SER_DESKEW_B
--    This is a latched signal that is updated on the rising edge of the PAL_BX_CLOCK
--    signal.  This signal is bit 0 of the Board Control Register # 1.
--
--  D_SER_DESKEW_B
--    The first term sets the register bit to the OCB value. This occurs when the 
--    WRITE_TO_PAL is asserted, the BOARD_CONTROL_REGISTER_1_SEL is asserted and when
--    OCB_WRITE_STRB is asserted.
--    The second term keeps the current value of SER_DESKEW_B when 
--    BOARD_CONTROL_REGISTER_1_SEL is asserted but WRITE_STRB_B is deasserted.
--    The third term keeps the current value of SER_DESKEW_B when 
--    BOARD_CONTROL_REGISTER_1_SEL is deasserted.
-------------------------------------------------------------------------------------

  D_SER_DESKEW_B <= (OCB_DATA_int_stdlv(0) 
                     AND WRITE_TO_PAL_int_stdl
                     AND BOARD_CONTROL_REGISTER_1_SEL_int_stdl 
                     AND OCB_WRITE_STRB_int_stdl) 
                 OR (SER_DESKEW_B_reg_stdl 
                     AND OCB_WRITE_STRB_B_inout_stdl
                     AND BOARD_CONTROL_REGISTER_1_SEL_int_stdl)
                 OR (SER_DESKEW_B_reg_stdl 
                     AND BOARD_CONTROL_REGISTER_1_SEL_B_int_stdl);

  SER_DESKEW_B_DFF: FDCP 
    generic map ( INIT => '1' )
    port map (    D    => D_SER_DESKEW_B,
                  PRE  => SYSRESET_DEBOUNCED_int_stdl,
                  CLR  => '0',
                  C    => PAL_BX_CLOCK_in_stdl,
                  Q    => SER_DESKEW_B_reg_stdl
             );


--\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\
--FPGA CONFIGURATION SECTION
--//////////////////////////////////////////////////////////////////////////////////

--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--  CNFG_CCLK
--    This is a latched signal that updates on the rising edge of the PAL_BX_CLOCK
--    signal.  This is a control signal for FPGA configuration.  Configuration
--    data is ingested by the FPGAs on the rising edge of this signal.
--
--    CNFG_CCLK is asserted in the IO_1 state when CONFIGURE_FPGAS is asserted.
--
--  D_CNFG_CCLK
--    The NEXT_STATE_QUIESCENT term deasserts CNFG_CCLK in the IDLE and LATCH_1 
--    states.  The LATCH_2 term deasserts CNFG_CCLK in the all states but the IO_1 
--    state.  The CONFIGURE_FPGAS term allows CNFG_CCLK to be asserted only if 
--    data is writen to the Configuration Data Register in the PAL and if 
--    ENABLE_FPGA_CONFIGURATION is asserted.
--
-- new D_CNFG_CCLK
-- new   The LATCH_2 term deasserts CNFG_CCLK in the all states but the IO_1 state.  The
-- new   CONFIGURE_FPGAS term allows CNFG_CCLK to be asserted only if data is writen to 
-- new   the Configuration Data Register in the PAL and if ENABLE_FPGA_CONFIGURATION is 
-- new   asserted.
------------------------------------------------------------------------------------
  D_CNFG_CCLK <= NEXT_STATE_QUIESCENT_B_int_stdl 
                 AND LATCH_2_STATE_int_stdl 
                 AND OCB_CHIP_SEL_int_stdlv(2) 
                 AND LTCHD_WRITE_int_stdl 
                 AND CONFIGURE_FPGAS_int_stdl;

-- new  D_CNFG_CCLK <= LATCH_2_STATE_int_stdl  
-- new                 AND CONFIGURE_FPGAS_int_stdl;

  CNFG_CCLK_DFF: FDCP 
    generic map ( INIT => '0' )
    port map (    D    => D_CNFG_CCLK,
                  PRE  => '0',
                  CLR  => SYSRESET_DEBOUNCED_int_stdl,
                  C    => PAL_BX_CLOCK_in_stdl,
                  Q    => CNFG_CCLK_out_stdl
              );


--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--  CNFG_CONTROL_DATA(0:7)
--  ----------------------
--
--      Bit| Signal
--      ---+---------------
--       0 | CNFG_PROG_B_REQ(0)
--       1 | CNFG_PROG_B_REQ(1)
--       2 | CNFG_CS_B(0)
--       3 | CNFG_CS_B(1)
--       4 | CNFG_RDWR_B
--       5 | 
--       6 |
--       7 | 
------------------------------------------------------------------------------------

  CNFG_CONTROL_DATA_int_stdlv(0) <= CNFG_PROG_B_REQ_reg_stdlv(0);
  CNFG_CONTROL_DATA_int_stdlv(1) <= CNFG_PROG_B_REQ_reg_stdlv(1);
  CNFG_CONTROL_DATA_int_stdlv(2) <= CNFG_CS_B_reg_stdlv(0);
  CNFG_CONTROL_DATA_int_stdlv(3) <= CNFG_CS_B_reg_stdlv(1);
  CNFG_CONTROL_DATA_int_stdlv(4) <= CNFG_RDWR_B_reg_stdl;
  CNFG_CONTROL_DATA_int_stdlv(5) <= '0';
  CNFG_CONTROL_DATA_int_stdlv(6) <= '0';
  CNFG_CONTROL_DATA_int_stdlv(7) <= '0';


--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--  CNFG_CS_B(0:1)
--    These are latched signals that are updated on the rising edge of the 
--    PAL_BX_CLOCK signal.  These signals are bits 2 and 3 of the Configuration
--    Control Register.
--
--  D_CNFG_CS_B_REQ(X)
--    The first term sets the register bit to the OCB value. This occurs when the 
--    WRITE_TO_PAL is asserted, the CNFG_CONTROL_REGISTER_SEL is asserted and when
--    OCB_WRITE_STRB is asserted.
--    The second term keeps the current value of CNFG_CS_B(X) when 
--    CNFG_CONTROL_REGISTER_SEL is asserted but WRITE_STRB_B is deasserted.
--    The third term keeps the current value of CNFG_CS_B(X) when 
--    CNFG_CONTROL_REGISTER_SEL is deasserted.
------------------------------------------------------------------------------------
  D_CNFG_CS_B(0) <= (OCB_DATA_int_stdlv(2) 
                     AND WRITE_TO_PAL_int_stdl
                     AND CNFG_CONTROL_REGISTER_SEL_int_stdl 
                     AND OCB_WRITE_STRB_int_stdl) 
                 OR (CNFG_CS_B_reg_stdlv(0) 
                     AND OCB_WRITE_STRB_B_inout_stdl
                     AND CNFG_CONTROL_REGISTER_SEL_int_stdl)
                 OR (CNFG_CS_B_reg_stdlv(0) 
                     AND CNFG_CONTROL_REGISTER_SEL_B_int_stdl);


  CNFG_CS_B_0_DFF: FDCP 
    generic map ( INIT => '1' )
    port map (    D    => D_CNFG_CS_B(0),
                  PRE  => SYSRESET_DEBOUNCED_int_stdl,
                  CLR  => '0',
                  C    => PAL_BX_CLOCK_in_stdl,
                  Q    => CNFG_CS_B_reg_stdlv(0)
              );


  D_CNFG_CS_B(1) <= (OCB_DATA_int_stdlv(3) 
                     AND WRITE_TO_PAL_int_stdl
                     AND CNFG_CONTROL_REGISTER_SEL_int_stdl 
                     AND OCB_WRITE_STRB_int_stdl) 
                 OR (CNFG_CS_B_reg_stdlv(1) 
                     AND OCB_WRITE_STRB_B_inout_stdl
                     AND CNFG_CONTROL_REGISTER_SEL_int_stdl)
                 OR (CNFG_CS_B_reg_stdlv(1) 
                     AND CNFG_CONTROL_REGISTER_SEL_B_int_stdl);


  CNFG_CS_B_1_DFF: FDCP 
    generic map ( INIT => '1' )
    port map (    D    => D_CNFG_CS_B(1),
                  PRE  => SYSRESET_DEBOUNCED_int_stdl,
                  CLR  => '0',
                  C    => PAL_BX_CLOCK_in_stdl,
                  Q    => CNFG_CS_B_reg_stdlv(1)
             );


--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--  CNFG_PROG_B(0:1)
--    These are latched signals that are updated on the rising edge of the 
--    PAL_BX_CLOCK signal.  These signals are bits 0 and 1 of the Configuration
--    Control Register.
--
--  D_CNFG_PROG_B(X)
--    The first term sets the register bit to the OCB value. This occurs when the 
--    WRITE_TO_PAL is asserted, the CNFG_CONTROL_REGISTER_SEL is asserted and when
--    OCB_WRITE_STRB is asserted.
--    The second term keeps the current value of CNFG_PROG_B(X) when 
--    CNFG_CONTROL_REGISTER_SEL is asserted but WRITE_STRB_B is deasserted.
--    The third term keeps the current value of CNFG_PROG_B(X) when 
--    CNFG_CONTROL_REGISTER_SEL is deasserted.
------------------------------------------------------------------------------------
  D_CNFG_PROG_B(0) <= ENABLE_FPGA_CONFIGURATION_B_int_stdl 
                  OR CNFG_PROG_B_REQ_reg_stdlv(0);


  CNFG_PROG_B_0_DFF: FDCP 
    generic map ( INIT => '1' )
    port map (    D    => D_CNFG_PROG_B(0),
                  PRE  => SYSRESET_DEBOUNCED_int_stdl,
                  CLR  => '0',
                  C    => PAL_BX_CLOCK_in_stdl,
                  Q    => CNFG_PROG_B_out_stdlv(0)
              );


  D_CNFG_PROG_B(1) <= ENABLE_FPGA_CONFIGURATION_B_int_stdl 
                  OR CNFG_PROG_B_REQ_reg_stdlv(1);

  CNFG_PROG_B_1_DFF: FDCP 
    generic map ( INIT => '1' )
    port map (    D    => D_CNFG_PROG_B(1),
                  PRE  => SYSRESET_DEBOUNCED_int_stdl,
                  CLR  => '0',
                  C    => PAL_BX_CLOCK_in_stdl,
                  Q    => CNFG_PROG_B_out_stdlv(1)
             );


--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--  CNFG_PROG_B_REQ(0:1)
--    These are latched signals that are updated on the rising edge of the 
--    PAL_BX_CLOCK signal.  These signals are bits 0 and 1 of the Configuration
--    Control Register.
--
--  D_CFNG_PROG_B_REQ(X)
--    The first term sets the register bit to the OCB value. This occurs when the 
--    WRITE_TO_PAL is asserted, the CNFG_CONTROL_REGISTER_SEL is asserted and when
--    OCB_WRITE_STRB is asserted.
--    The second term keeps the current value of CNFG_PROG_B_REQ(X) when 
--    CNFG_CONTROL_REGISTER_SEL is asserted but WRITE_STRB_B is deasserted.
--    The third term keeps the current value of CNFG_PROG_B_REQ(X) when 
--    CNFG_CONTROL_REGISTER_SEL is deasserted.
------------------------------------------------------------------------------------
  D_CNFG_PROG_B_REQ(0) <= (OCB_DATA_int_stdlv(0) AND WRITE_TO_PAL_int_stdl
                           AND CNFG_CONTROL_REGISTER_SEL_int_stdl 
                           AND OCB_WRITE_STRB_int_stdl) 
                       OR (CNFG_PROG_B_REQ_reg_stdlv(0) 
                           AND OCB_WRITE_STRB_B_inout_stdl
                           AND CNFG_CONTROL_REGISTER_SEL_int_stdl)
                       OR (CNFG_PROG_B_REQ_reg_stdlv(0) 
                           AND CNFG_CONTROL_REGISTER_SEL_B_int_stdl);


  CNFG_PROG_B_REQ_0_DFF: FDCP 
    generic map ( INIT => '1' )
    port map (    D    => D_CNFG_PROG_B_REQ(0),
                  PRE  => SYSRESET_DEBOUNCED_int_stdl,
                  CLR  => '0',
                  C    => PAL_BX_CLOCK_in_stdl,
                  Q    => CNFG_PROG_B_REQ_reg_stdlv(0)
              );


  D_CNFG_PROG_B_REQ(1) <= (OCB_DATA_int_stdlv(1) 
                           AND WRITE_TO_PAL_int_stdl
                           AND CNFG_CONTROL_REGISTER_SEL_int_stdl 
                           AND OCB_WRITE_STRB_int_stdl) 
                       OR (CNFG_PROG_B_REQ_reg_stdlv(1) 
                           AND OCB_WRITE_STRB_B_inout_stdl
                           AND CNFG_CONTROL_REGISTER_SEL_int_stdl)
                       OR (CNFG_PROG_B_REQ_reg_stdlv(1) 
                           AND CNFG_CONTROL_REGISTER_SEL_B_int_stdl);

  CNFG_PROG_B_REQ_1_DFF: FDCP 
    generic map ( INIT => '1' )
    port map (    D    => D_CNFG_PROG_B_REQ(1),
                  PRE  => SYSRESET_DEBOUNCED_int_stdl,
                  CLR  => '0',
                  C    => PAL_BX_CLOCK_in_stdl,
                  Q    => CNFG_PROG_B_REQ_reg_stdlv(1)
             );


--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--  CNFG_RDWR_B
--    This is a latched signal that is updated on the rising edge of the PAL_BX_CLOCK
--    signal.  This signal is bit 4 of the Configuration Control Register.
--
--  D_CNFG_RDWR_B
--    The first term sets the register bit to the OCB value. This occurs when the 
--    WRITE_TO_PAL is asserted, the CNFG_CONTROL_REGISTER_1_SEL is asserted and when 
--    OCB_WRITE_STRB is asserted.
--    The second term keeps the current value of CNFG_RDWR_B when 
--    CNFG_CONTROL_SEL is asserted but WRITE_STRB_B is deasserted.
--    The third term keeps the current value of CNFG_RDWR_B when 
--    CNFG_CONTROL_SEL is deasserted.
------------------------------------------------------------------------------------
  D_CNFG_RDWR_B <= (OCB_DATA_int_stdlv(4) 
                    AND WRITE_TO_PAL_int_stdl
                    AND CNFG_CONTROL_REGISTER_SEL_int_stdl 
                    AND OCB_WRITE_STRB_int_stdl) 
                OR (CNFG_RDWR_B_reg_stdl 
                    AND OCB_WRITE_STRB_B_inout_stdl
                    AND CNFG_CONTROL_REGISTER_SEL_int_stdl)
                OR (CNFG_RDWR_B_reg_stdl 
                    AND CNFG_CONTROL_REGISTER_SEL_B_int_stdl);

  CNFG_RDWR_B_DFF: FDCP 
    generic map ( INIT => '1' )
    port map (    D    => D_CNFG_RDWR_B,
                  PRE  => SYSRESET_DEBOUNCED_int_stdl,
                  CLR  => '0',
                  C    => PAL_BX_CLOCK_in_stdl,
                  Q    => CNFG_RDWR_B_reg_stdl
             );

--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--  CNFG_STATUS_DATA(0:7)
--  ----------------
--
--      Bit| Signal
--      ---+---------------
--       0 | CNFG_INIT_B(0)
--       1 | CNFG_INIT_B(1)
--       2 | CNFG_BUSY(0)
--       3 | CNFG_BUSY(1)
--       4 | CNFG_DONE(0)
--       5 | CNFG_DONE(1) 
--       6 |
--       7 | 
------------------------------------------------------------------------------------

  CNFG_STATUS_DATA_int_stdlv(0) <= CNFG_INIT_B_in_stdlv(0);
  CNFG_STATUS_DATA_int_stdlv(1) <= CNFG_INIT_B_in_stdlv(1);
  CNFG_STATUS_DATA_int_stdlv(2) <= CNFG_BUSY_in_stdlv(0);
  CNFG_STATUS_DATA_int_stdlv(3) <= CNFG_BUSY_in_stdlv(1);
  CNFG_STATUS_DATA_int_stdlv(4) <= CNFG_DONE_in_stdlv(0);
  CNFG_STATUS_DATA_int_stdlv(5) <= CNFG_DONE_in_stdlv(1);
  CNFG_STATUS_DATA_int_stdlv(6) <= '0';
  CNFG_STATUS_DATA_int_stdlv(7) <= '0';



--\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\
--ON CARD BUS OUTPUT SECTION
--//////////////////////////////////////////////////////////////////////////////////

--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--  OCB_DATA(0:7)
--    This is a vector of latched signals that update on the rising edge of the 
--    PAL_BX_CLOCK.  The input is the multiplexed OUPUT_DATA.  The outputs go to 
--    enablable IO buffers.  The IO buffers are enabled with the 
--    OCB_DATA_OUTPUT_ENABLE signal.
--
------------------------------------------------------------------------------------

  OCB_DATA: for i in 0 to 7 generate
  begin
        
        OCB_DATA_DFF: FDCP 
          generic map ( INIT => '0' )
          port map ( D   => OUTPUT_DATA_int_stdlv(i),
                     CLR => '0',
                     PRE => SYSRESET_DEBOUNCED_int_stdl,
                     C   => PAL_BX_CLOCK_in_stdl,
                     Q   => Q_OCB_DATA(i)
                   );

        OCB_DATA_IOBUF : IOBUFE 
          port map ( IO => OCB_DATA_inout_stdlv(i),
                      I => Q_OCB_DATA(i), 
                      O => OCB_DATA_int_stdlv(i),
                      E => OCB_DATA_OUTPUT_ENABLE_int_stdl
                    );
        
  end generate OCB_DATA;
 

--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--  OCB_DATA_OUTPUT_ENABLE
--    This is a latched signal that updates on the rising edge of the PAL_BX_CLOCK
--    and is asserted high.  It enables the IO buffers that drive the OCB_DATA
--    signals to the outputs.
-- 
--    OCB_DATA_OUTPUT_ENABLE is asserted during the LATCH_2, IO_1, IO_2 and 
--    SET_QUIESCENT states when OCB_CHIP_SEL(2) is asserted and LTCHD_WRITE_B is
--    high.
--
-- new   OCB_DATA_OUTPUT_ENABLE is asserted during the LATCH_2, IO_1, IO_2 and 
-- new   SET_QUIESCENT states when READ_FROM_PAL is asserted.
------------------------------------------------------------------------------------

  D_OCB_DATA_OUTPUT_ENABLE <=     NEXT_STATE_QUIESCENT_B_int_stdl 
                             AND OCB_CHIP_SEL_int_stdlv(2) 
                             AND LTCHD_WRITE_B_in_stdl;

-- new  D_OCB_DATA_OUTPUT_ENABLE <=     NEXT_STATE_QUIESCENT_B_int_stdl 
-- new                             AND READ_FROM_PAL_int_stdl;

  OCB_DATA_OUTPUT_ENABLE_DFF: FDCP 
    generic map ( INIT => '0' )
    port map (    D    => D_OCB_DATA_OUTPUT_ENABLE,
                  PRE  => '0',
                  CLR  => SYSRESET_DEBOUNCED_int_stdl,
                  C    => PAL_BX_CLOCK_in_stdl,
                  Q    => OCB_DATA_OUTPUT_ENABLE_int_stdl
             );

    
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--  OUTPUT_DATA(0:7)
--    This is a muliplexed vector that selects between BOARD_STATUS_1_DATA,
--    BOARD_STATUS_2_DATA, CNFG_STATUS_DATA, BOARD_CONTROL_1_DATA, 
--    BOARD_CONTROL_2_DATA, and CNFG_CONTROL_DATA. 
-------------------------------------------------------------------------------------

  OUTPUT_DATA: for i in 0 to 7 generate
  begin
    OUTPUT_DATA_int_stdlv(i) <=      ( BOARD_STATUS_1_DATA_int_stdlv(i) 
                                   AND BOARD_STATUS_REGISTER_1_SEL_int_stdl )
                                OR   ( BOARD_STATUS_2_DATA_int_stdlv(i)  
                                   AND BOARD_STATUS_REGISTER_2_SEL_int_stdl )
                                OR   ( CNFG_STATUS_DATA_int_stdlv(i)
                                   AND CNFG_STATUS_REGISTER_SEL_int_stdl )
                                OR   ( BOARD_CONTROL_1_DATA_int_stdlv(i) 
                                   AND BOARD_CONTROL_REGISTER_1_SEL_int_stdl )
                                OR (   BOARD_CONTROL_2_DATA_int_stdlv(i) 
                                   AND BOARD_CONTROL_REGISTER_2_SEL_int_stdl )
                                OR (   CNFG_CONTROL_DATA_int_stdlv(i)    
                                   AND CNFG_CONTROL_REGISTER_SEL_int_stdl );
  end generate OUTPUT_DATA;
  

--\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\
--PAL ACCESS SECTION
--//////////////////////////////////////////////////////////////////////////////////

--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- PAL_ACCESS(0:16)
--
--      Index| Signal
--      -----+------------
--        0  | PAL_BX_CLOCK
--        1  | DS1
--        2  | DRV_DTACK
--        3  | VALID_CYCLE
--        4  | VME_LTCH_CLK
--        5  | DATA_BUF_ENB_B
--        6  | DATA_BUF_DIR
--        7  | OCB_DIRECTION
--        8  | OCB_CHIP_SEL(2)
--        9  | OCB_DATA_OUTPUT_ENABLE
--        10 | OCB_WRITE_STRB_B
--        11 | OCB_DATA(0)
--        12 | OCB_ADRS(1)
--        13 | WRITE_TO_PAL
--        14 | BOARD_CONTROL_REGISTER_1_SEL
--        15 | SER_DESKEW_B
--        16 | DRV_CRATE_STATUS(0)
--
-------------------------------------------------------------------------------------

  PAL_ACCESS_OBUF : for i in 0 to 16 generate
  begin
  PAL_ACCESS_IOBUF : OBUFE 
    port map ( O => PAL_ACCESS_out_stdlv(i),
               I => PAL_ACCESS_int_stdlv(i),
               E => ENABLE_PAL_ACCESS_OUTPUT_reg_stdl
              );
  end generate PAL_ACCESS_OBUF;

--Initial PAL_ACCESS assignments  bcp_1.jed
--PAL_ACCESS_int_stdlv(0)  <= PAL_BX_CLOCK_in_stdl;
--PAL_ACCESS_int_stdlv(1)  <= DS1_int_stdl;
--PAL_ACCESS_int_stdlv(2)  <= DRV_DTACK_out_stdl;
--PAL_ACCESS_int_stdlv(3)  <= VALID_CYCLE_int_stdl;
--PAL_ACCESS_int_stdlv(4)  <= VME_LTCH_CLK_out_stdl;
--PAL_ACCESS_int_stdlv(5)  <= DATA_BUF_ENB_B_out_stdl;
--PAL_ACCESS_int_stdlv(6)  <= DATA_BUF_DIR_out_stdl;
--PAL_ACCESS_int_stdlv(7)  <= OCB_DIRECTION_out_stdl;
--PAL_ACCESS_int_stdlv(8)  <= OCB_CHIP_SEL_int_stdlv(2);
--PAL_ACCESS_int_stdlv(9)  <= OCB_DATA_OUTPUT_ENABLE_int_stdl;
--PAL_ACCESS_int_stdlv(10) <= OCB_WRITE_STRB_B_inout_stdl;
--PAL_ACCESS_int_stdlv(11) <= OCB_DATA_int_stdlv(0);
--PAL_ACCESS_int_stdlv(12) <= OCB_ADRS_in_stdlv(1);
--PAL_ACCESS_int_stdlv(13) <= WRITE_TO_PAL_int_stdl;
--PAL_ACCESS_int_stdlv(14) <= BOARD_CONTROL_1_sel_int_stdl;
--PAL_ACCESS_int_stdlv(15) <= SER_DESKEW_B_reg_stdl;
--PAL_ACCESS_int_stdlv(16) <= DRV_CRATE_STATUS_reg_stdlv(0);

--Look into THIS_CARD  bcp_2.jed
--PAL_ACCESS_int_stdlv(0)  <= PAL_BX_CLOCK_in_stdl;
--PAL_ACCESS_int_stdlv(1)  <= DS1_int_stdl;
--PAL_ACCESS_int_stdlv(2)  <= VALID_CYCLE_int_stdl;
--PAL_ACCESS_int_stdlv(3)  <= THIS_CARD_int_stdl;
--PAL_ACCESS_int_stdlv(4)  <= VME_GEO_int_stdlv(0); 
--PAL_ACCESS_int_stdlv(5)  <= OCB_ADRS_in_stdlv(18); 
--PAL_ACCESS_int_stdlv(6)  <= VME_GEO_int_stdlv(1); 
--PAL_ACCESS_int_stdlv(7)  <= OCB_ADRS_in_stdlv(19);  
--PAL_ACCESS_int_stdlv(8)  <= VME_GEO_int_stdlv(2);  
--PAL_ACCESS_int_stdlv(9)  <= OCB_ADRS_in_stdlv(20);  
--PAL_ACCESS_int_stdlv(10) <= VME_GEO_int_stdlv(3);  
--PAL_ACCESS_int_stdlv(11) <= OCB_ADRS_in_stdlv(21);  
--PAL_ACCESS_int_stdlv(12) <= VME_GEO_int_stdlv(4);  
--PAL_ACCESS_int_stdlv(13) <= OCB_ADRS_in_stdlv(22);
--PAL_ACCESS_int_stdlv(14) <= OCB_ADRS_in_stdlv(23);  
--PAL_ACCESS_int_stdlv(15) <= VALID_CYCLE_int_stdl;   
--PAL_ACCESS_int_stdlv(16) <= '0';   

--OCB singal Timing  bcp_3.jed
--PAL_ACCESS_int_stdlv(0)  <= PAL_BX_CLOCK_in_stdl;
--PAL_ACCESS_int_stdlv(1)  <= DS1_int_stdl;
--PAL_ACCESS_int_stdlv(2)  <= DRV_DTACK_out_stdl;
--PAL_ACCESS_int_stdlv(3)  <= IDLE_STATE_int_stdl;            
--PAL_ACCESS_int_stdlv(4)  <= LATCH_1_STATE_int_stdl;
--PAL_ACCESS_int_stdlv(5)  <= LATCH_2_STATE_int_stdl;
--PAL_ACCESS_int_stdlv(6)  <= IO_1_STATE_int_stdl;
--PAL_ACCESS_int_stdlv(7)  <= IO_2_STATE_int_stdl;
--PAL_ACCESS_int_stdlv(8)  <= SET_QUIESCENT_STATE_int_stdl;
--PAL_ACCESS_int_stdlv(9)  <= OCB_DIRECTION_out_stdl;
--PAL_ACCESS_int_stdlv(10) <= OCB_WRITE_STRB_B_inout_stdl;
--PAL_ACCESS_int_stdlv(11) <= OCB_CHIP_SEL_B_out_stdlv(0); 
--PAL_ACCESS_int_stdlv(12) <= OCB_CHIP_SEL_B_int_stdlv(2); 
--PAL_ACCESS_int_stdlv(13) <= OCB_DATA_OUTPUT_ENABLE_int_stdl; 
--PAL_ACCESS_int_stdlv(14) <= DATA_BUF_DIR_out_stdl;
--PAL_ACCESS_int_stdlv(15) <= DATA_BUF_ENB_B_out_stdl;
--PAL_ACCESS_int_stdlv(16) <= '0';

--Enable and dependent signals for FPGA Configuration, DAC programming and ADC operation.
--bcp_4.jed
--PAL_ACCESS_int_stdlv(0)  <= PAL_BX_CLOCK_in_stdl;
--PAL_ACCESS_int_stdlv(1)  <= DS1_int_stdl;
--PAL_ACCESS_int_stdlv(2)  <= DRV_DTACK_out_stdl;
--PAL_ACCESS_int_stdlv(3)  <= VALID_CYCLE_int_stdl;
--PAL_ACCESS_int_stdlv(4)  <= '0';  
--PAL_ACCESS_int_stdlv(5)  <= '0'; 
--PAL_ACCESS_int_stdlv(6)  <= '0'; 
--PAL_ACCESS_int_stdlv(7)  <= ENABLE_LOADING_DACS_reg_stdl;    
--PAL_ACCESS_int_stdlv(8)  <= DAC_SERIAL_DATA_CLOCK_out_stdl;  
--PAL_ACCESS_int_stdlv(9)  <= DAC_CHIP_SELECT_B_out_stdl;      
--PAL_ACCESS_int_stdlv(10) <= '0'; 
--PAL_ACCESS_int_stdlv(11) <= '0'; 
--PAL_ACCESS_int_stdlv(12) <= ENABLE_FPGA_CONFIGURATION_reg_stdl; 
--PAL_ACCESS_int_stdlv(13) <= CNFG_PROG_B_out_stdlv(0); 
--PAL_ACCESS_int_stdlv(14) <= CNFG_PROG_B_out_stdlv(1);
--PAL_ACCESS_int_stdlv(15) <= CNFG_CCLK_out_stdl;
--PAL_ACCESS_int_stdlv(16) <= '0';

--LED_STRECHTER counter Q ouputs.
--bcp_5.jed
PAL_ACCESS_int_stdlv(0)  <= LED_STRETCHER_Q_int_stdlv(0); 
PAL_ACCESS_int_stdlv(1)  <= LED_STRETCHER_Q_int_stdlv(1);   
PAL_ACCESS_int_stdlv(2)  <= LED_STRETCHER_Q_int_stdlv(2);  
PAL_ACCESS_int_stdlv(3)  <= LED_STRETCHER_Q_int_stdlv(3);   
PAL_ACCESS_int_stdlv(4)  <= LED_STRETCHER_Q_int_stdlv(4);  
PAL_ACCESS_int_stdlv(5)  <= LED_STRETCHER_Q_int_stdlv(5);  
PAL_ACCESS_int_stdlv(6)  <= LED_STRETCHER_Q_int_stdlv(6);  
PAL_ACCESS_int_stdlv(7)  <= LED_STRETCHER_Q_int_stdlv(7);  
PAL_ACCESS_int_stdlv(8)  <= LED_STRETCHER_Q_int_stdlv(8);   
PAL_ACCESS_int_stdlv(9)  <= LED_STRETCHER_Q_int_stdlv(9);   
PAL_ACCESS_int_stdlv(10) <= LED_STRETCHER_Q_int_stdlv(10);   
PAL_ACCESS_int_stdlv(11) <= LED_STRETCHER_Q_int_stdlv(11);   
PAL_ACCESS_int_stdlv(12) <= LED_STRETCHER_Q_int_stdlv(12);   
PAL_ACCESS_int_stdlv(13) <= LED_STRETCHER_Q_int_stdlv(13);   
PAL_ACCESS_int_stdlv(14) <= VALID_CYCLE_int_stdl; 
--New PAL_ACCESS_int_stdlv(15) <= TURN_ON_LED_B_int_stdl;
PAL_ACCESS_int_stdlv(15) <= LED_STRETCHER_COUNTER_IS_ZERO_int_stdl;
PAL_ACCESS_int_stdlv(16) <= '0';

--\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\
--BX X8 CLOCK GENERATION SECTION
--//////////////////////////////////////////////////////////////////////////////////


--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--  CNT_BIT_VAL_1
------------------------------------------------------------------------------------
  D_CNT_BIT_VAL_1 <= (CNT_BIT_VAL_4_B_int_stdl AND CNT_BIT_VAL_2_B_int_stdl
                      AND CNT_BIT_VAL_1_B_int_stdl) 
                   OR 
                     (CNT_BIT_VAL_4_inout_stdl AND CNT_BIT_VAL_2_int_stdl 
                      AND CNT_BIT_VAL_1_B_int_stdl) 
                   OR
                     (CNT_BIT_VAL_4_inout_stdl AND CNT_BIT_VAL_2_B_int_stdl 
                      AND CNT_BIT_VAL_1_B_int_stdl) 
                   OR
                     (CNT_BIT_VAL_4_B_int_stdl AND CNT_BIT_VAL_2_int_stdl 
                      AND CNT_BIT_VAL_1_B_int_stdl); 

  CNT_BIT_VAL_1_DFF: FDCP 
    generic map ( INIT => '0' )
    port map (    D    => D_CNT_BIT_VAL_1,
                  PRE  => '0',
                  CLR  => '0',
                  C    => PAL_BX_X8_CLOCK_in_stdl,
                  Q    => CNT_BIT_VAL_1_int_stdl
             );


--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--  CNT_BIT_VAL_2
------------------------------------------------------------------------------------
  D_CNT_BIT_VAL_2 <= (CNT_BIT_VAL_4_B_int_stdl 
                      AND CNT_BIT_VAL_2_B_int_stdl
                      AND CNT_BIT_VAL_1_B_int_stdl) 
                   OR 
                     (CNT_BIT_VAL_4_inout_stdl 
                      AND CNT_BIT_VAL_2_int_stdl 
                      AND CNT_BIT_VAL_1_int_stdl) 
                   OR
                     (CNT_BIT_VAL_4_inout_stdl 
                      AND CNT_BIT_VAL_2_B_int_stdl 
                      AND CNT_BIT_VAL_1_B_int_stdl) 
                   OR
                     (CNT_BIT_VAL_4_B_int_stdl 
                      AND CNT_BIT_VAL_2_int_stdl 
                      AND CNT_BIT_VAL_1_int_stdl); 

  CNT_BIT_VAL_2_DFF: FDCP 
    generic map ( INIT => '0' )
    port map (    D    => D_CNT_BIT_VAL_2,
                  PRE  => '0',
                  CLR  => '0',
                  C    => PAL_BX_X8_CLOCK_in_stdl,
                  Q    => CNT_BIT_VAL_2_int_stdl
             );


--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--  CNT_BIT_VAL_4
------------------------------------------------------------------------------------
  D_CNT_BIT_VAL_4 <= (CNT_BIT_VAL_4_B_int_stdl 
                      AND CNT_BIT_VAL_2_B_int_stdl
                      AND CNT_BIT_VAL_1_B_int_stdl) 
                   OR 
                     (CNT_BIT_VAL_4_inout_stdl 
                      AND CNT_BIT_VAL_2_int_stdl 
                      AND CNT_BIT_VAL_1_int_stdl) 
                   OR
                     (CNT_BIT_VAL_4_inout_stdl 
                      AND CNT_BIT_VAL_2_int_stdl 
                      AND CNT_BIT_VAL_1_B_int_stdl) 
                   OR
                     (CNT_BIT_VAL_4_inout_stdl 
                      AND CNT_BIT_VAL_2_B_int_stdl 
                      AND CNT_BIT_VAL_1_int_stdl); 

  CNT_BIT_VAL_4_DFF: FDCP 
    generic map ( INIT => '0' )
    port map (    D    => D_CNT_BIT_VAL_4,
                  PRE  => '0',
                  CLR  => SYSRESET_DEBOUNCED_int_stdl,
                  C    => PAL_BX_X8_CLOCK_in_stdl,
                  Q    => CNT_BIT_VAL_4_inout_stdl
             );

 
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--  LOOP_FILTER_REF
------------------------------------------------------------------------------------

  LOOP_FILTER_REF_DFF: FDCP 
    generic map ( INIT => '0' )
    port map (    D    => LOOP_FILTER_REF_B_int_stdl,
                  PRE  => '0',
                  CLR  => SYSRESET_DEBOUNCED_int_stdl,
                  C    => PAL_BX_CLOCK_in_stdl,
                  Q    => LOOP_FILTER_REF_inout_stdl
              );


--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--  PAL_FIRST_X8_EDGE
-------------------------------------------------------------------------------------

  D_PAL_FIRST_X8_EDGE <=     CNT_BIT_VAL_4_B_int_stdl 
                         AND CNT_BIT_VAL_2_B_int_stdl
                         AND CNT_BIT_VAL_1_int_stdl; 

  PAL_FIRST_X8_EDGE_DFF: FDCP 
    generic map ( INIT => '0' )
    port map (    D    => D_PAL_FIRST_X8_EDGE,
                  PRE  => '0',
                  CLR  => SYSRESET_DEBOUNCED_int_stdl,
                  C    => PAL_BX_X8_CLOCK_in_stdl,
                  Q    => PAL_FIRST_X8_EDGE_out_stdl
             );

    

--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--  PHASE_DET_OUT 
------------------------------------------------------------------------------------

  PHASE_DET_OUT_out_stdl <= RCVD_BX_CLOCK_DIV2_stdl  XOR  LOOP_FILTER_REF_inout_stdl;


--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--  RCVD_BX_CLOCK
------------------------------------------------------------------------------------

  RCVD_BX_CLOCK_DFF: FDCP 
    generic map ( INIT => '0' )
    port map (    D    => RCVD_BX_CLOCK_DIV2_B_stdl,
                  PRE  => '0',
                  CLR  => SYSRESET_DEBOUNCED_int_stdl,
                  C    => RCVD_BX_CLOCK_inout_stdl,
                  Q    => RCVD_BX_CLOCK_DIV2_stdl
             );

--//////////////////////////////////////////////////////////////////////////////////
--//////////////////////////////////////////////////////////////////////////////////



end bcp_structural;