-- Xilinx_Components.vhd
-- created:       12-Aug-2004
-- last modified: 28-Sep-2004

------------------------------------------------------------------------------------
-- My Xilinx library
-- This library contains counters obtained from the Xilinx Libraries Guide.  These
-- are components that must be infered and not instantiated.
-- 
-- This library contains the following Packages
--  Counters
--
------------------------------------------------------------------------------------

library IEEE;        
use IEEE.STD_LOGIC_1164.all; 
use IEEE.std_logic_arith.all;

package Counters is


------------------------------------------------------------------------------------
--  CBCE
--
--  This is the 2-, 4-, 8-,16-Bit Cascadable Binary Counters with Clock Enable and 
--  Asynchronous Clear (CB2CE, CB4CE, CB8CE, CB16CE) 
------------------------------------------------------------------------------------


  --This component definition is modeled after FDCE code in Library Guide.

  component CBCE          
    generic (WIDTH:INTEGER :=  2 ); 
    port (
           C  : in std_logic; 
           CE : in std_logic;
           CLR :in  std_logic;
           Q : inout std_logic_vector (0 to WIDTH-1);
           TC : inout std_logic;
           CEO : out std_logic
         );
  end component;

end Counters;

library IEEE;
use IEEE.STD_LOGIC_1164.all;  
use IEEE.std_logic_arith.all;         
use IEEE.std_logic_unsigned.all;

entity CBCE is
  generic (WIDTH:INTEGER :=  2 ); -- synthesis translate_on 
  port (
         signal C  : in STD_LOGIC; 
         signal CE : in std_logic; 
         signal CLR : in std_logic; 
         signal Q : inout std_logic_vector (0 to WIDTH-1); 
         signal TC : inout std_logic;
         signal CEO : out std_logic
       );
end CBCE;




--The code for this architecture was taken from CBXXCE entry in Library Guide.

architecture Behavioral of cbce is

  constant TERMINAL_COUNT : std_logic_vector(0 to WIDTH-1) := (others =>  '1' ); 

  begin

     process(C,CLR)
      begin 
        if(CLR='1') then
          Q   <= (others => '0');
        elsif (C'event and C='1') then
            if (CE='1') then  
              Q   <= Q   + '1'; 
            end if;           
        end if;                 
      end process;
   
      process(Q)
      begin
        if (Q = TERMINAL_COUNT) then
          TC <= '1';
        else   
          TC <= '0';
        end if;
      end process;

      CEO <= TC and CE;

end Behavioral;