Description of the Data Path FPGA TEST Firmwares -------------------------------------------------- Original Rev. 23-DEC-2004 Most Recent Rev. 16-AUG-2006 TEST #1 ------- The original DP Test #1 Firmware was just a single "AND" gate with IBUF's and an OBUF and PADs. Its purpose was just to test building Virtex II on DESMO using the 4.1i Libraries. It was built with gui driven 4.1i. Details of this work are in the file: description_of_building_t1.txt The current (23-MAY-2005) DP Test #1 firmware is designed to provied the BX_Number as the Et data on all 32 output channels from the ADF-2 card. The purpose of this is to allow easy verification in the TAB card that proper alignment of Et data has been accomplished. Note that multiple ADF-2 cards all running DP Test #1 firmware will all be in sync via their common connection to the SCLD. DP Test #1 firmware was derived from the DP Test #7 Phy firmware. It is just a slight modification so that the BX_Number is presented to an input of the TT_Cell output multiplexer and the output multiplexer is hardwired to select that input. TEST #2 ------- Test #2 DP Firmware provides 8 16 bit Read/Write "Control Registers". The purpose of this version of DP Test was to provide an exo file to test Configuring the Data Path FPGA's and to provide register targets to test the connection from TCC over VME and OCB into the DP FPGAs. The 8 Control Registers in this design are numbered 0:7. These 8 registers are located in the first 8 addresses of the "FPGA Global Register" address space. These are consecutive "VME Word Addresses". +-------+---+---+---+---+---+---+---+---+---+---+---+---+---+---+-------------+ | A A A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | | | 1 1 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | | 6 5 4 | 3 | 2 | 1 | 0 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | | +-------+---+---+---+---+---+---+---+---+---+---+---+---+---+---+-------------+ +-------+---+---+---+---+---+---+---+---+---+---+---+---+---+---+-------------+ | 0 0 0 | 0 0 0 1 0 0 0 0 0 | X X X X | 0 |FPGA Glob Reg| +-------+---+---+---+---+---+---+---+---+---+---+---+---+---+---+-------------+ That is at even VME Addresses: $0400 through $040e If the ADF-2 card is in slot #8 then this becomes even VME Addresses: $200400 through $20040e None of the bits from these 8 Control Registers do anything except readback. In the special case of the 4 LSBits in the Control Register #7 they control the 4 front panel LED's that are associated with each Data Path FPGA. Control Register #7 Bit 0 is Front Panel LED_0, Bit 1 is LED_1, Bit 2 is LED_2, and Bit 3 is LED_3. Setting the bit Low will cause the LED to light up. TEST #3 ------- Test #3 provides 16 16 bit Read Only "Status Registers" which give an on the fly view of what is coming out of the 16 ADC's that feed a given Data Path FPGA. The data from the ADC's is properly "double buffered" so that in a given VME read all of the bits will come from a given ADC sample. The Test #3 design drives the ADC Clock lines at their normal 4x the BX rate, i.e. about 30.345 MHz 32.95 nsec period. The 16 Status Registers to read the ADC output data are located as the first register in each TT's EM CSR and HD CSR address space. +-------+---+---+---+---+---+---+---+---+---+---+---+---+---+---+-------------+ | A A A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | | | 1 1 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | | 6 5 4 | 3 | 2 | 1 | 0 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | | +-------+---+---+---+---+---+---+---+---+---+---+---+---+---+---+-------------+ +-------+---+---+---+---+---+---+---+---+---+---+---+---+---+---+-------------+ |TrgTwr#| 0 0 0 1 1 0 0 0 0 | X X X X | 0 |EM Chan CSR | | 0:7 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+-------------+ | T T T | 0 0 0 1 1 1 0 0 0 | X X X X | 0 |HD Chan CSR | +-------+---+---+---+---+---+---+---+---+---+---+---+---+---+---+-------------+ That is, Test #3 is doing TT based address decoding. In detail the register addresses are: Channel 0 EM ADC $ 0600 Channel 1 EM ADC $ 4600 Channel 2 EM ADC $ 8600 Channel 3 EM ADC $ c600 Channel 4 EM ADC $10600 Channel 5 EM ADC $14600 Channel 6 EM ADC $18600 Channel 7 EM ADC $1c600 Channel 0 HD ADC $ 0700 Channel 1 HD ADC $ 4700 Channel 2 HD ADC $ 8700 Channel 3 HD ADC $ c700 Channel 4 HD ADC $10700 Channel 5 HD ADC $14700 Channel 6 HD ADC $18700 Channel 7 HD ADC $1c700 | Note that this | address nibble contains bits from the TT address and from the card slot address. Using a slot like slot #8 keeps things simple for the humans because the base address of the ADF-2 card in slot #8 is $200000. The 10 bit wide data from the ADC's is packed into the lower 10 bits of the 16 bit wide words that are read from these Status registers. The data that you readout is from the ADC conversion cycle that just completed right before the OCB Read cycle began. The upper 6 bits that you read from these registers are tied Low. The DP Test #3 design has no Control Registers. TEST #4 ------- The purpose of the DP Test #4 design is to provide readout of a long series of consecutive ADC samples. The Test #4 design can provide readout of up to 4096 consecutive ADC samples. The storage area for this ADC data in the DP Test #4 design is provided by Virtex II Block SelectRAM Memory. ADC data is written into the "A" port of this memory and the On-Card-Bus connection is to the "B" port of this memory. The OCB connection is full Read/Write. The DP Test #4 design needs one Control Register to setup how it operates. This Control Register is located at the first address in the "FPGA Global Register" space. The is Regester Address $0200. The layout of this one Control Register is the following: D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 -----------+--- ----------+-- --+-------- --------+-- No St No La N Chan No EM Connect ore Connect ble C 0:7 Connect HD Description of the Control Register #0 bits: Reg Adrs $0200 Bit D0 This controls whether the EM or HD half of the Channel selected by bits D6:D4 of this control register feeds its ADC data to the storage memory. D0 Low selects EM. D4 High selects HD. Bits D3:D1 have no connection but they do readback. Bits D6:D4 These bits control which Channel is feeding data to the memory port "A" input. D6 is the MSBit. D4 is the LSBit. Bit D7 has no connection but does readback. Bit D8 This bit controls whether or not the "channel label" is stored in the upper 5 bits of the memory. If D8 is set HIGH then the channel label will be written in the upper 5 bits of memory. When D8 is LOW then the upper 5 bits of memory data are all "0's". See the memory data format below. Bits D11:D9 have no connection but they do readback. Bit D12 This bit controls writing ADC data into the "A" port of the storage memory. A "0" to "1" transition of D12 causes writing of ADC data into the memory to begin. Writing data into the memory continues for 4096 writes and then automatically stops. Writing begins at memory location $000 and ends at location $fff. Bits D15:D13 have no connection but they do readback. Note that with an ADC conversion and memory write once every 33 nsec it takes only 135 usec to write into all 4096 memory locations. Because this is fully dual ported memory and because the first new ADC data will be stored before the first VME read from the memory can possibly begin, it is OK to begin reading right away after you initiate a write sequence. The 10 bit ADC data is located in the low order 10 bits of the 16 bit words that TCC can readout from the "B" Port of the memory. The format of this readout data uses the upper bits to indicate which Channel this data came from. The format of the readout data is: Bits D15:D12 Indicate the Channel that was selected to provide input to the memory when this data was written. Bit D11 Indicates whether the EM or HD half of the selected channel was providing ADC data when this memory data was written. Low --> this is EM data and High --> this is HD data. Bits D10 Is tied Low. Bits D9:D0 Are the 10 bits of ADC output data, D9 is the MSBit. Note that to work with ADF-2 Channels 0:7 you must use DP FPGA F0. For ADF-2 Channels 8:15 you must use DP FPGA F1. The On-Card-Bus connection to the "B" Port of the memory is a full Read/Write connection and operates independently of the "A" Port. From the VME the base address of the ADF-2 card this 4096 word memory block is offset up by VME Adrs: $8000. In terms of its Register Address this memory block occupies Regester Addresses $4000 : $4fff. TEST #5 ------- The purpose of the DP Test #5 design is to provide and initial first check of the Channel Link section of the ADF-2 Card. In this design the inputs to the Channel Link Transmitters on the ADF-2 card are driven by the Q outputs from a set of 8 bit counters. This is just an easy way to supply "data" to the Channel Link Transmitters that can easily be checked for "rationality" at the output of a Channel Link Receiver. To make this test we use Denis Calvet's Channel Link Test Receiver Mezzanine card and just probe its "Received Data Monitor Connector" with a scope. You can tell which signal is which by the rate of the square wave pattern. The T5 design allows you to, one at a time, hold the various 8 bit counters in it at zero - so there is no ambiguity about what signal is what. The T5 design does drive all signals to the Channel Link Transmitters from BX_X8_Clock'd FD's in the I/O Blocks (as all designs will). So even this simple design is testing the final timing layout for data sent to the Channel Link Transmitters. The 3 counters that generate the test data are connected to the Channel Link chip data inputs in the following way. Counter Bit Counter #0 Counter #1 Counter #2 ------- ---------------- ---------------- ---------------- 0 TX_0 Ch_0_EM TX_8 Ch_4_EM TX_34 BX_Count 1 TX_1 Ch_0_HD TX_9 Ch_4_EM TX_36 Frame 2 TX_2 Ch_1_EM TX_10 Ch_5_EM TX_37 Parity 3 TX_3 Ch_1_HD TX_11 Ch_5_EM n.c. 4 TX_4 Ch_2_EM TX_12 Ch_6_EM n.c. 5 TX_5 Ch_2_HD TX_13 Ch_6_EM n.c. 6 TX_6 Ch_3_EM TX_14 Ch_7_EM n.c. 7 TX_7 Ch_3_HD TX_15 Ch_7_EM n.c. TX_# is the name of the data input line to the Channel Link Transmitter chip. The 4 reserved signals are tied to GND. TX_35 RSVD_0, TX_40 RSVD_1, TX_41 RSVD_2, TX_42 RSVD_3 all GND. The T5 design includes the same 8 control registers as the T2 design. Like the T2 design these 8 16 bit control registers are located at Register Address $0200 : $0207. The 3 low order bits in the control register at $0207 are used to hold the counters in their reset state (all zero's). When one of these bits is written High it forces the corresponding counter to hold at all zero's (and lights the corresponding LED). Bit in Control Reg #7 Register Address $0207 Function ---------------------- ----------------------------------------- 0 Hold Counter #0 in Reset and Light LED #0 1 Hold Counter #1 in Reset and Light LED #1 2 Hold Counter #2 in Reset and Light LED #2 3 Light LED #3 15:4 Just Read Write Bits with no function. When using this test, note that on Denis Channel Link Tester card he has named the received data signals "RX_DATA(35:0). This labeling skips over the Channel Link signals that are not used in the ADF to TAB applications, i.e. RX_OUT_30 and RX_OUT_31. Specifically: Channel Link Chip Labeling Chan Lnk Test Card Labeling Function -------------------------- --------------------------- -------- RX_OUT_0 : RX_OUT_29 = RX_DATA_0 : RX_DATA_29 ADC Data RX_OUT_32 = RX_DATA_30 ADC Data RX_OUT_33 = RX_DATA_31 ADC Data RX_OUT_34 = RX_DATA_32 BX_Count RX_OUT_35 = RX_DATA_33 RSVD_0 RX_OUT_36 = RX_DATA_34 Frame RX_OUT_37 = RX_DATA_35 Parity TEST #6 ------- The purpose of the DP Test #6 design is to provide a test source that can be used with Denis Calvet's Test Receiver. T6 will provide: Pseudo Random data sequences on the 16 data lines the correctly incrementing and aligned Beam Crossing Number the correctly aligned Frame signal the correctly generated and aligned Parity signal With the ADF-2 operating from the SCLD, the T6 design should work without any changes for the ADF to TAB tests. The basic building blocks for the T6 design should work without any changes in the Data Path FPGA design for Physics running. The T6 design has the "chalange" that both D.P. FPGA's must, under TCC control, start up their Pseudo Random Noise Data Generators and thus start sending out non-fixed data to the Saclay Channel Link Test Receiver. This synchronous startup is accomplished by re-using the CNFG_RDWR_B line from the Board Control PAL that runs to both D.P. FPGA's. When this line is Voltage Hi the Pseudo Random Noise Data Generators will be allowed to Shift (and the BX Number counter will be allowed to increment). When CNFG_RDWR_B is Voltage Low the PRN Generators will be disabled from Shifting (and the BX Number counter locked at a value of 1). CNFG_RDWR_B is set Voltage Hi by writting a "1" to bit D4 of the Board Control PAL's FPGA Configuration Control Regiseter, Register Address 5. CNFG_RDWR_B is set Voltage Low by writting a "0". The T6 design has 16 registers for loading in the seed values for the Pseudo Random Noise data generators. These are located starting at Register Address $0200 in the DP FPGA Global Register Address space. It makes sense to stop the PRN Generators from Shifting while the seeds are loaded. The seeds may be readback from the same register addresses. The content of the 16 bit shift registers in the PRN Generators may be read at anytime by reading these 16 Register Addresses. You must stop the PRN Gen's from Shifting if you want meaningful readback data of their shift register contents. T6 Reg Loads the Seed T6 Reg Loads the Seed Address for the PRN Gen for Address for the PRN Gen for ------- ------------------- ------- ------------------- $0200 TX_0 Ch_0_EM $0208 TX_8 Ch_4_EM $0201 TX_1 Ch_0_HD $0209 TX_9 Ch_4_HD $0202 TX_2 Ch_1_EM $020a TX_10 Ch_5_EM $0203 TX_3 Ch_1_HD $020b TX_11 Ch_5_HD $0204 TX_4 Ch_2_EM $020c TX_12 Ch_6_EM $0205 TX_5 Ch_2_HD $020d TX_13 Ch_6_HD $0206 TX_6 Ch_3_EM $020e TX_14 Ch_7_EM $0207 TX_7 Ch_3_HD $020f TX_15 Ch_7_HD ============================================================================ TEST T7_PHY Current Rev. 16-AUG-2006 ----------- The purpose of the DP Test T7_PHY design is to move another step closer to the real Production Physics design. The main differences between T7_PHY and a Production Physics design are: - The "filter" is not implement but rather is just replaced by a D-Register to give the same number of timing steps. - T7_PHY contains the PRN Generators for Channel Link testing. Production Physics designs may or may not include the PRN data option. The intent is that T7_PHY design, except for the parts that are specific to the Filters, should look exactly the same to the TCC control software as the Production Physics Data Path firmware. If necessary T7_PHY will continue to be maintanced so that it presents the standard interface to the TCC control software. An additional use of the T7_PHY design is to replace the T2:T6 designs in the Production ADF-2 Card Testing setup. T7_PHY can replace all functions except for the 4096 ADC samples that can be captured by T6 firmware. T7_PHY can only capture 1024 consecutive ADC samples. In the description below the words, 1 and Hi and asserted are used somewhat interchanably. For the T7_Phy 1 or Hi always causes the asserted state of a signal or function. There are no "Low active" signals within the T7_Phy design. Memory Blocks ------------- The T7_PHY design contains all 3 types of memory blocks which are located at their planned register address locations. All 3 types of memory blocks were implemented in a common way. Specifically in all cases TCC has VME read/write access via the B-Port of the memory block while the A-Port is connected to the trigger signal data flow path. Because of this common implementation, after this initial description, for sake of brevity, explicit declaration that reference is being made to either the A-Port or B-Port will be dropped. All TCC VME access is via the B-Port. All trigger signal hardware access, e.g. writing monitor data or playing back simulation data, is via the A-Port. Raw ADC Data Memory Block - There are separate Raw ADC Memory Blocks for the EM and for the HD sections of each Trigger Tower. - This is a 1 k register address long memory block. - The B-Port of this memory block presents a full 16 bit Read/Write interface to TCC. - The A-Port of this memory block can be used to either record Raw ADC samples or to playback Raw ADC simulation data. - The "raw" ADC monitor data that is written into this memory block is captured after the ADC data delay section of the signal processing. Thus adjustments of the delay value will effect where the BLS signals appear in this memory block. - When TCC reads data from the Raw ADC Memory Block that was written via its A_Port: the 10 bit ADC samples are read in bits 9:0 Bit 12 shows the state of the Live_BX signal. Bit #13 shows the state of the Begin_of_Turn signal. Bits #10, 11, 14, 15 are always be written by the A-Port as Low. - When using A_Port playback to send simulation data to the Filters, it is only bits 9:0 that are sent to the Filters. I.E. TCC needs to write the Raw ADC simulation data into bits 9:0. - The Raw ADC Mem Blk A-Ports are controlled globally by the Raw ADC Mem Blk A-Port Address Generator and individually by control registers that are associated with each channel. Et Look-Up Memory Block - There are separate Et Look-Up Memory Blocks for the EM and for the HD sections of each Trigger Tower. - This is a 2 k register address long memory. - The B-Port of this memory block presents an 8 bit Read/Write interface to TCC. TCC accesses the 2k locations in this memory block is on sequential Register Addresses. The Et value that TCC wants to store at a given address in this memory block must be written to it on data bits 7:0. When TCC reads from this memory block the upper 8 bits of the 16 bit reads will always be all zeros. - The 11 bit Address for the A-Port of this memory block comes from the output of the Filter. The 8 bit wide A-Port output data is sent to the Channel Link shifter output section of the Data Path FPGA. The A-Port data input is not used in the Et Look-Up memory blocks. Final Output Data Memory Block - There is one common Final Output Memory Block that services both the EM and for the HD sections of a Trigger Tower. - This is a 1 k register address long memory. - The B-Port of this memory block presents a full 16 bit Read/Write interface to TCC. - In this memory the Final Output EM data is stored in bits 15:8 and the Final Output HD data is stores in bits 7:0. - The A-Port of this memory block can be used to either record Final Output data or to playback simulated Final Output data. - The Final Output Mem Blk A-Ports are controlled globally by the Final Output Mem Blk A-Port Address Generator and individually by control registers that are associated with each channel. Near the end the description of the T7_PHY firmware there are tables which show the memory addresses that are used to store the Simulation data and Monitor data in the Raw ADC Data Memroy Block and in the Final Output Data Memory Block. Address Generator Description ----------------------------- The Data Path FPGA contains two Address Generators for the memory block A-Ports. One Address Generator services the Raw ADC Memory Blocks for all 8 TTs and the othe Address Generator services the Final Output Data Memory Blocks for all 8 TTs. Each of the two Address Generators also produce the "global" Write Enable signal for the type of memory blocks that it services. The length of the sequence that the Address Generator makes is programmable. Typical values to use are either: 159 to make an address sequence that repeats each turn, or 1024 to capture a maximum length record. The length of the sequence that is generated is controlled by the value that TCC writes into a Control register that is associated with each Address Generator. Starting the Address Generators is triggered by TCC writing to a control register. There is no other way to start either of the Address Generators. Once triggered to start by TCC, the Address Generator waits for the Begin_of_Turn marker before acutally starting. The Address Generator always starts from address zero. There are 3 ways for the Address Generator to stop. Which mode is actually in use is controlled by the value that TCC writes into a Control register that are associated with each Address Generator. The 3 modes of stopping are: - Play only a single cycle of the Address Sequence and then automatically stop. The corresponding Global Write Enable signal goes Low at the same time as the Address Generator stops. The generator stops at the end of its Address Sequence cycle which can be set to match one full turn. - Continue playing the Address Sequence until TCC tells you to stop at the next end of your Address Sequence cycle. The corresponding Global Write Enable signal goes Low at the same time as the Address Generator stops. The generator stops at the end of its Address Sequence cycle. - Continue playing the Address Sequence until the SCLD_SAVE_MONIT_DATA signal arrives. When the SCLD_SAVE_MONITOR_DATA signal arrives then immediately stop. Do not wait for the end of the Address Sequence cycle before stopping. The corresponding Global Write Enable signal goes Low at the same time as the Address Generator stops. No matter what causes the Address Generator to stop, the address that it stopped at is saved in a Status register that TCC can read. This is the address of the last location in the memory block that was just written to (or played back from). The Global Write Enable signal from the Address Generator typically goes Hi while the Address Generator is running. This write enable needs to be block from going active Hi when the Address Generator is started to playback simulation data. There is a bit in the a control register for each Address Generator that blocks its Global Write Enable signal from going Hi when the Address Generator is started. Per Channel Raw ADC Mem Blk Write Enable ----------------------------------------- On a per channel basis TCC can setup bits in a TT Control register that change how that channel's Raw ADC Mem Blk Write Enable signal operates. - The per channel Raw ADC Mem Blk Write Enable signal goes Hi when the Raw ADC Mem Blk Global Write Enable signal goes Hi. This always happens synchronous with the Begin of Turn marker. The Raw ADC Mem Blk Global Write Enable signal comes from the Address Generator for the Raw ADC Mem Blk. - If TCC wants to capture a single sweep of Raw ADC data then it sets a per channel control register so that the individual channel's Raw ADC Mem Block Write Enable will just follow the Raw ADC Mem Blk Global Write Enable signal. In this way the channel's Write Enable will return Low at the same time as the Raw ADC Mem Blk Global Write Enable signal returns Low. - If TCC wants the individual channel to keep writing Raw ADC monitor data until it sees a BLS signal above a programmable threshold and then to stop writing at the end of the Turn that contained the interesting BLS signal bump, it can set up this mode of operation via bits in a per TT Control register. If the channel's Raw ADC Mem Blk is in this "wait for an interesting signal and then stop writting" mode, then its Raw ADC Mem Blk Write Enable signal will go back low synchronous with the next occurance of the Begin of Turn marker after a minimum value pulse has been seen in that channel's ADC OR it returns low when the Raw ADC Mem Blk Global Write Enable goes back low. Per TT Final Output Mem Blk Write Enable ----------------------------------------- On a per TT basis TCC can setup bits in that TT's EM and HD Control Registers that change how that TT's Final Output Mem Blk Write Enable signal operates. Recall that there is a single Final Output Mem Blk to service both the EM and HD sections of a Trigger Tower. - The TT's Final Output Mem Blk Write Enable signal goes Hi when the Final Output Mem Blk Global Write Enable signal goes Hi. This always happens synchronous with the Begin of Turn marker. The Final Output Mem Blk Global Write Enable signal comes from the Address Generator for the Final Output Mem Blk's. - If TCC wants to capture a single sweep of Final Output data then it sets per TT EM and HD control registers so that that TT's Final Output Mem Block Write Enable will just follow the Final Output Mem Blk Global Write Enable signal. In this way that TT's Final Output Mem Blk Write Enable will return Low at the same time as the Final Ouput Mem Blk Global Write Enable signal returns Low. - If TCC wants an individual TT to keep writing Final Output monitor data until it sees a BLS signal above a programmable threshold and then to stop writing at the end of the Turn that contained the interesting BLS signal, it can set up this mode of operation via bits in that TT's EM and HD Control Registers. The T7_Phy design allows for an interestingly big BLS signal in either the EM or HD side of a TT to stop the writing of monitor data to that TT's Final Output Mem Blk. Setting up for this mode of operation just requires setting a bit in that TT's EM or HD Output Control Register and setting additional bits in the register which control the amplitude threshold of the BLS signal that is required to stop the writting of monitor data. Note that stopping the writing of Final Output data requires that that channel also be setup to stop writing Raw ADC monitor data based on seeing an interesting BLS signal. Because this same "stop writing" function is available for the both the Raw ADC Mem Blk and the Final Output Mem Blk this enables TCC to easily capture the corresponding Raw ADC data and the Final Output data from real BLS energy deposits. If the TT's Final Output Mem Blk is in this "wait for a interesting signal and then stop writting" mode, then its Final Output Mem Blk Write Enable signal will go back low synchronous with the next occurance of the Begin of Turn marker after a minimum value pulse has been seen in either that channel's EM or HD ADC data (as setup by TCC) or else it will return low when the Final Output Mem Blk Global Write Enable goes back low. Register Description -------------------- Global Registers ---------------- There are 9 Global Registers in the T7_Phy design. They begin at the beginning of the Global Register section of address space. Glb_Reg 0 This is part of the control of the A-Port Address Generator for the Raw ADC Memory Block. Note that a single Address Generator services the EM and HD Raw ADC memories of all 8 Trigger Towers that are handled by this Data Path FPGA. This is a full 16 bit read/write Control Register. Bit #0 Moving bit #0 from Low to Hi triggers the Address Generator to start generating its Address Sequence and to set the Raw ADC Mem Blk Global Write Enable signal Hi. When TCC asynchronously moves bit #0 from Low to Hi the hardware then waits for the next Begin_of_Turn marker before actual starting any of these actions. The Address Sequence always starts at memory address zero. Bit #1 When bit #1 is set Low, and then the Address Generator is triggered to start, it will play for just one pass through its Address Sequence and then stop. When it stops the Raw ADC Mem Blk Global Write Enable will go Low. The last memory address to be written will be the highest number in its Address Sequence. When bit #1 is set Hi, and then the Address Generator is triggered to start, it will continue to play through its Address Sequence for as long as bit #1 remains Hi. Once bit #1 is set back Low, the Address Generator will complete the current cycle of its Sequence and then stop. When it stops the Raw ADC Mem Blk Global Write Enable will go back Low. Bit #2 Bit #2 is used to enable the SCLD_SAVE_MONIT_ DATA signal to cause the Address Generator to stop running. When the Address Generator is stopped by the SCLD_SAVE_MONIT_DATA signal it stops immediately. When bit #2 is set Low, and then the Address Generator is triggered to start, it will behave as described in the section about bit #1 above. When both bits #1 and #2 are set Hi, and then the Address Generator is triggered to start, it will continue to play through its Address Sequence until the SCLD_SAVE_MONIT_DATA signal is asserted. Once SCLD_SAVE_MONIT_DATA signal is asserted the Address Generator will immediately stop running and the the Raw ADC Mem Blk Global Write Enable will go Low. In this mode, when stopped by the SCLD_SAVE_ MONIT_DATA signal, the Address Generator will not complete the current cycle of the Address Sequence before stopping. When in this SCLD_SAVE_MONIT_DATA signal stop mode, TCC can still cause the Address Generator to stop and the end of its next Address Sequence by setting both bits #1 and #2 Low. Operation with bit #1 set Low and bit set #2 Hi is not defined. Bit #3 This control bit is used to lock the Raw ADC Mem Blk Global Write Enable signal Low, i.e. inactive. This is used when TCC wants to start the Address Generator to playback simulation data that TCC has previously written into the Raw ADC Mem Blk over VME. When playing back simulation data TCC must not allow writes via the mem blk A-Port because they would overwrite the simulation data. Setting Bit #3 Low tells the Address Generator NOT to assert its Raw ADC Mem Blk Global Write Enable signal when it is started. Setting Bit #3 Hi will cause the Raw ADC Mem Blk Global Write Enable signal to be asserted or not asserted depending upon whether or not the Raw ADC Mem Block Address Generator is running or not. Bits 15:4 are not used. They do readback as written. Glb_Reg 1 This is part of the control of the A-Port Address Generator for the Raw ADC Data Memory Block. Note that a single Address Generator services the EM and HD Raw ADC memories of all 8 Trigger Towers. This is a full 16 bit read/write Control register. Bits 15:0 Control the highest address that is in the Address Sequence from this Address Generator. The value that TCC should put in this register is one less than the highest memory address that it wants written to. E.G. For working with full turns of data this register should be set to 634. This is 4 x 159 - 2. The 4x is because the raw ADC samples are at 4x the tick rate. The ticks are numbered 1:159. This 4x raw ADC data is stored in memory locations 0:635. One of the -1's is to shift down by one to the memory locations. The second -1 is because this register needs to be loaded with a value 1 less than maximum desired address. In the next section about the Final Output Mem Blk the analogous register in its Address Generator should be loaded with 157 to capture a full turn. For working with 1024 samples of data set this register to 1022. The memory locations used (i.e. memory addresses generated) will be 0:1023. Glb_Reg 2 This is part of the control of the A-Port Address Generator for the Raw ADC Data Memory Block. This is a full 16 bit read only Status register. Bits 15:0 read back the current value of the address that is being sent out from the Address Generator. The value read from this register is not protected against skewing across the period of a VME read cycle. The real purpose of this register is that it captures the value of the last address that was written to in the memory block when the Address Generator stops. This is useful when the Address Generator is stopped by the SCLD_ SAVE_MONIT_DATA signal. Glb_Reg 3 ,4 ,5 These are exactly the same as above except that Glb Reg 4, 5, 6 control the Final Output Memory Block A-Port Address Generator. These is a single A-Port Address Generator for the Final Output Memory Block of all 8 Trigger Towers that are serviced by this Data Path FPGA. Glb_Reg 6 This is a 16 bit read only Status Register. It allows TCC to read the status of many signals in the Timing and Control section of the T7_Phy design. The data in this register is not "double buffered" and thus it could change state during the period of a VME read cycle. The bit assignments in this register are: Bit #0 Raw ADC Mem Blk Address Generator is Running Bit #1 Raw ADC Mem Blk Global Write Enable is Asserted Bit #2 Gnd Bit #3 Gnd Bit #4 Final Output Mem Blk Address Generator is Running Bit #5 Final Output Mem Blk Global Write Enb is Asserted Bit #6 Gnd Bit #7 Gnd Bit #8 Begin_Turn Bit #9 Live_BX Bit #10 Save_Monitor_Data Bit #11 SCL_Init Bit #12 SCLD_Spare Bit #13 Gnd Bit #14 Data Path FPGA ID Number 0 or 1 Bit #15 Pseudo Random Number Generators are Shifting Glb_Reg 7 This is a 16 bit read only Status Register. It allows TCC, with a single read, to determine the state of the Raw ADC Memory A-Port Write Enable signals of all 16 channels that are serviced by this Data Path FPGA. When the Raw ADC Memory A-Port Write Enables have been set to independently go low at the end of a turn during which each channel saw a BLS signal that was above its specified threshold, then reading this register can be used to quickly determine which channels have recorded an interesting BLS signal. When a given bit in this register is a 1 then the Raw ADC Memory A-Port Write Enable of the corresponding channel is asserted. Bit #0 Channel 0 EM 0,0 EM Bit #1 Channel 0 HD 0,0 HD Bit #2 Channel 1 EM 0,1 EM Bit #3 Channel 1 HD 0,1 HD ...... ............ ...... Bit #14 Channel 7 EM 1,3 EM Bit #15 Channel 7 HD 1,3 HD Glb_Reg 16 This is a 16 bit read only Status Register. This register allows TCC to simultaniously read the 8 bit Et value of channel 0 (0,0 EM) that was just sent to the Channel Link Shifter Output Section and the 8 bit BX Number that was sent to the Channel Link Shifter Output Section along with this Et Data. That is it allows you to see an actual Et Data plus BX Number "pair" that was sent to the TAB. The purpose of this register is to allow TCC to verify the correspondence between the address of data in the Raw ADC Mem Blk, the address of data in the Final Output Mem Blk, and the actual Et Data plus BX Number that is sent to the TAB. The general procedure for using this register to verify the correspondence between: Raw ADC Mem Block address, Final Output Data Mem Blk address, and the BX Number that is attached to the Et Data that is sent to the TAB is to: Load the Raw ADC Mem Blk with simulation data that will make a unique output from the Filter for each tick. Start the Raw ADC Mem Blk playing this simulation data with an address sequence cycle of 0:158. Start the Final Output Mem Block recording data with an address sequence cycle of 0:158. Read this register a number of times to capture 0,0 EM Et Data plus BX Number pairs. Stop the Final Output Mem Block from recording data and read it out. In this Final Output Mem Block readout data look for 0,0 EM Et values that you had noted earlier in the readout of this register. Compare the address where these specific Et values were recorded in the Final Output Mem Block with the corresponding BX Number that was sent to the TAB along with this Et value. This verifies the correspondence between the Final Output Mem Blk address with the BX Number that was sent with that data to the TAB. Look at what RAW ADC Mem Block addresses contained the data to make this Et value come out of the Filter to verify the correspondence between the Raw ADC Mem Blk address and the BX Number sent to the TAB. The memory block addresses that you are verifying in this way are the: Final Output Mem Blk address as used with Monitor data and the Raw ADC Mem Blk address as used with Simulation data This is a "double buffered register". It will not skew data across the period of a VME read cycle. At the beginning of the VME read cycle it captures the most recent 0,0 EM Et data - BX Number pair that was sent to the Channel Link Shifter Output Section. The VME read cycle returns the following: Bits 15:8 BX Number Bits 7:0 0.0 EM Et value for this crossing Per TT Registers ---------------- All of the per TT registers are located in the register address space that was originally planned for the EM TT registers. To the extent possible, all the per TT registers are setup so that the Even Register Addresses are for the EM channels and the Odd Register Addresses are for the HD channels. The T7_Phy design contains 8 registers per TT. TT_Reg 0 Read the 10 bit EM raw ADC data "on the fly". High order 6 bits are tied to ground. Read Only This register is "double buffered" so the data will not skew across the period of a VME read cycle. TT_Reg 1 Read the 10 bit HD raw ADC data "on the fly". High order 6 bits are tied to ground. Read Only This register is "double buffered" so the data will not skew across the period of a VME read cycle. TT_Reg 2 Control Reg for the EM Input section of this TT. This is a full 16 bit read/write Control register. Bits 7:0 Stop Comparator's Reference Threshold These bits set the threshold value for stopping monitor data writes to the Raw ADC Memory Blk (and optionally stopping writes to this TT's Final Output Mem Blk). This is an 8 bit comparison on the 8 High order bits of the 10 bits of raw ADC data. If TCC wants to set the "Stop Writting Threshold" in terms of Et it will need to take a number of things into consideration. Bits 11:8 Set the amount of ADC Data Delay which is used to compensate for BLS signal skew. This is in steps of 33 nsec. The bigger the number the longer the ADC data is delayed before it enters the filter. The full range 0:F is available. Bit 12 Controls the Input Multiplexer Low --> Time aligned ADC data is sent to the Filter. Hi --> Simulation data from the Raw ADC Memory Block is sent to the filter. Bit 13 Not currently used - it does read back. Bit 14 Controls the mode of stopping Raw ADC monitor data writing to this channel's Raw ADC Mem Blk. Low --> The Write Enable to this Raw ADC Mem Blk directly follows the Raw ADC Mem Blk Global Write Enable signal from the Address Generator. This is the correct Mode for capturing a single turn or 1024 samples of raw ADC data. Hi --> The Write Enable to this Raw ADC Mem Blk goes Hi when the Raw ADC Mem Blk Global Write Enable signal from the Address Generator goes Hi. This channel's Raw ADC Write Enabe returns Low either: at the end of a turn in which an ADC sample was greater than the Stop Comparator's Reference Threshold or else when the Raw ADC Mem Blk Global Write Enable signal returns Low. This is the correct Mode for collecting one turn samples that contain a BLS signal showing an interesting energy deposit. Bit 15 Not currently used - it does read back. TT_Reg 3 Control Reg for the HD Input section of this TT. The bit layout of this register is the same as that of the EM section. This is a full 16 bit read/write Control register. TT_Reg 4 Control Reg for the EM Output section of this TT. This is a full 16 bit read/write Control register. Bits 7:0 Set the value of the "Constant Et Data" for this channel. The Output Multiplexer can be set to seleect the "Constant Et Data" as the Final Output from this channel. Bits 8,9,10 control the Output Multiplexer 10 9 8 Multiplexer Selects -- -- -- --------------------------------------- 0 0 0 Filter Output data is always selected as the Final Output data. 0 0 1 The "Constant Et Data" value is always selected as the Final Output data. 0 1 0 Data from the Pseudo Random Number Generator is always selected as the Final Output data. 0 1 1 Simulation data from the Output Memory Block is always selected as the Final Output data. 1 x y For ticks that are NOT marked as Live_BX the "Constant Et Data" is selected as the Final Output data. For ticks that are marked as Live_BX the Final Output data is selected by bits 8 and 9 as shown above. Bit 11 Not currently used - it does read back. Bit 12 Selects the mode for stopping monitor data writing to this TT's Final Output Memory Block. Low --> The Write Enable to this Final Output Mem Blk directly follows the Final Output Mem Blk Global Write Enable signal from the Address Generator. This is the correct Mode for capturing a single turn or 1024 samples of Final Output data. Hi --> The Write Enable to this Final Output Mem Blk goes Hi when the Final Output Mem Blk Global Write Enable signal from the Address Generator goes Hi. This TT's Final Output Write Enabe returns Low either: at the end of a turn in which an ADC sample was greater than the Stop Comparator's Reference Threshold or else when the Final Output Mem Blk Global Write Enable signal returns Low. This is the correct Mode for collecting a one turn sample that contains the Final Output data from a BLS signal showing an interesting energy deposit. Note that for this mode of stopping writes to this TT's Final Output Mem Blk to work properly, TCC must have also setup this TT's EM and HD Raw ADC Mem Blk's to stop writing when a BLS signal over threshold is seen. Note that you can not have both the EM and HD selected at the same time to stop the Final Output Data Mem Blk writting. Bits 13:15 Not currently used - they do read back. TT_Reg 5 Control Reg for the HD Output section of this TT. The bit layout of this register is the same as that of the EM section. This is a full 16 bit read/write Control register. TT_Reg 6 Control Register to load the EM PRN Generator Seed. This is a full 16 bit read/write Control register. TT_Reg 7 Control Register to load the HD PRN Generator Seed. This is a full 16 bit read/write Control register. T7_PHY Data Path FPGA LED Display --------------------------------- LED 0 Upper Left is iluminated when any of the Raw ADC Memory Block A-Port Write Enable signals are asserted. LED 1 Upper Right is iluminated when the Raw ADC Memory Block A-Port Address Generator is running. LED 2 Lower Left is iluminated when the Final Output Memory Block A-Port Address Generator is running. LED 3 Lower Right is iluminated when the PRN Generators are running. Location in Address Space of Registers and Memory Blocks -------------------------------------------------------- The full description of the VME memory map of the ADF-2 card is presented in the document: www.pa.msu.edu/hep/d0/ftp/run2b/l1cal/hardware/adf_2/general/ adf_2_vme_addressing.txt The information here is just a quick review / reminder of the address locations with respect to the base address of a given ADF-2 card. Everything here is listed in terms of "Regester Addresses". Global Registers start at: 512 aka $200 Per TT Registers base addresses: TT=0 TT=1 TT=2 TT=3 TT=4 TT=5 TT=6 TT=7 ----- ----- ----- ----- ----- ----- ----- ----- 768 8960 17152 25344 33536 41728 49920 58112 $300 $2300 $4300 $6300 $8300 $A300 $C300 $E300 EM Raw ADC Memory Blocks base addresses: TT=0 TT=1 TT=2 TT=3 TT=4 TT=5 TT=6 TT=7 ----- ----- ----- ----- ----- ----- ----- ----- 2048 10240 18432 26624 34816 43008 51200 59392 $800 $2800 $4800 $6800 $8800 $A800 $C800 $E800 HD Raw ADC Memory Blocks base addresses: TT=0 TT=1 TT=2 TT=3 TT=4 TT=5 TT=6 TT=7 ----- ----- ----- ----- ----- ----- ----- ----- 3072 11264 19456 27648 35840 44032 52224 60416 $C00 $2C00 $4C00 $6C00 $8C00 $AC00 $CC00 $EC00 EM Et Lookup Memory Blocks base addresses: TT=0 TT=1 TT=2 TT=3 TT=4 TT=5 TT=6 TT=7 ----- ----- ----- ----- ----- ----- ----- ----- 4096 12288 20480 28672 36864 45056 53248 61440 $1000 $3000 $5000 $7000 $9000 $B000 $D000 $F000 HD Et Lookup Memory Blocks base addresses: TT=0 TT=1 TT=2 TT=3 TT=4 TT=5 TT=6 TT=7 ----- ----- ----- ----- ----- ----- ----- ----- 6144 14336 22528 30720 38912 47104 55296 63488 $1800 $3800 $5800 $7800 $9800 $B800 $D800 $F800 Final Output Memory Blocks base addresses: TT=0 TT=1 TT=2 TT=3 TT=4 TT=5 TT=6 TT=7 ----- ----- ----- ----- ----- ----- ----- ----- 1024 9216 17408 25600 33792 41984 50176 58368 $400 $2400 $4400 $6400 $8400 $A400 $C400 $E400 Location of Simulation and Monitor Data in the Raw ADC and Final Output Memory Blocks --------------------------------------------- Review of the SCL Frame "Tick" Numbering: The is from the 24:28-APR-2001 Log Book entry SCL Frame L1 Accept Tick Number of the 36x36 Accelerator Live Crossings --------------------------------------- First Second Third Super Super Super Bunch Bunch Bunch --------- --------- --------- BX dec hex dec hex dec hex ---- --- --- --- --- --- --- 1st 7 07 60 3c 113 71 2nd 10 0a 63 3f 116 74 3rd 13 0d 66 42 119 77 4th 16 10 69 45 122 7a 5th 19 13 72 48 125 7d 6th 22 16 75 4b 128 80 7th 25 19 78 4e 131 83 8th 28 1c 81 51 134 86 9th 31 1f 84 54 137 89 10th 34 22 87 57 140 8c 11th 37 25 90 5a 143 8f 12th 40 28 93 5d 146 92 Memory Block Addresses for Simulation and for Monitoring Data Different memory block addresses are used to hold the Monitor data and the Simulation data for a given "Tick" or ADC sample. If the Monitor data for a given BX is held at memory address "N" then the Simulation data for that same BX is held at memory addres "N-1" If the Simulation data for a given BX is held at memory address "N" then the Monitor data for that same BX is held at memory address "N+1" I have only checked the alignment of the data in the Memory Blocks for ADF channel 0,0 EM. The other 31 channels should follow this pattern or something is very wrong with the firmware. For 0,0 EM the Raw ADC Data Memory Block starts at adrs 2048 For 0,0 EM the Final Output Data Memory Block starts at adrs 1024 Raw ADC Data Memory Block Simulation Data ------------------------------------------- The following are the addresses in the channel 0,0 EM Raw ADC Data Memory Block that hold the Simulation data that controls the Et data sent to the TAB on Live BXs. 1st Super Bunch 2nd Super Bunch 3rd Super Bunch --------------- --------------- --------------- Tick Mem Blk Tick Mem Blk Tick Mem Blk BX Number Address Number Address Number Address ---- ------ ------- ------ ------- ------ ------- 1st 7 2072 60 2284 113 2496 2nd 10 2084 63 2296 116 2508 3rd 13 2096 66 2308 119 2520 4th 16 2108 69 2320 122 2532 5th 19 2120 72 2332 125 2544 6th 22 2132 75 2344 128 2556 7th 25 2144 78 2356 131 2568 8th 28 2156 81 2368 134 2580 9th 31 2168 84 2380 137 2592 10th 34 2180 87 2392 140 2604 11th 37 2192 90 2404 143 2616 12th 40 2204 93 2416 146 2628 Raw ADC Data Memory Block Monitor Data ---------------------------------------- The following are the addresses in the channel 0,0 EM Raw ADC Data Memory Block that hold the Monitor data from the ADC sample that control the Et data sent to the TAB on Live BXs. 1st Super Bunch 2nd Super Bunch 3rd Super Bunch --------------- --------------- --------------- Tick Mem Blk Tick Mem Blk Tick Mem Blk BX Number Address Number Address Number Address ---- ------ ------- ------ ------- ------ ------- 1st 7 2073 60 2285 113 2497 2nd 10 2085 63 2297 116 2509 3rd 13 2097 66 2309 119 2521 4th 16 2109 69 2321 122 2533 5th 19 2121 72 2333 125 2545 6th 22 2133 75 2345 128 2557 7th 25 2145 78 2357 131 2569 8th 28 2157 81 2369 134 2581 9th 31 2169 84 2381 137 2593 10th 34 2181 87 2393 140 2605 11th 37 2193 90 2405 143 2617 12th 40 2205 93 2417 146 2629 Final Output Data Memory Block Simulation Data ------------------------------------------------ The following are the addresses in the channel 0,0 EM Final Output Data Memory Block that hold the Simulation data that controls the Et data sent to the TAB on Live BXs. 1st Super Bunch 2nd Super Bunch 3rd Super Bunch --------------- --------------- --------------- Tick Mem Blk Tick Mem Blk Tick Mem Blk BX Number Address Number Address Number Address ---- ------ ------- ------ ------- ------ ------- 1st 7 1029 60 1082 113 1135 2nd 10 1032 63 1085 116 1138 3rd 13 1035 66 1088 119 1141 4th 16 1038 69 1091 122 1144 5th 19 1041 72 1094 125 1147 6th 22 1044 75 1097 128 1150 7th 25 1047 78 1100 131 1153 8th 28 1050 81 1103 134 1156 9th 31 1053 84 1106 137 1159 10th 34 1056 87 1109 140 1162 11th 37 1059 90 1112 143 1165 12th 40 1062 93 1115 146 1168 Final Output Data Memory Block Monitor Data --------------------------------------------- The following are the addresses in the channel 0,0 EM Final Output Data Memory Block that hold the Monitor data of the Et values actually sent to the TAB on Live BXs. 1st Super Bunch 2nd Super Bunch 3rd Super Bunch --------------- --------------- --------------- Tick Mem Blk Tick Mem Blk Tick Mem Blk BX Number Address Number Address Number Address ---- ------ ------- ------ ------- ------ ------- 1st 7 1030 60 1083 113 1136 2nd 10 1033 63 1086 116 1139 3rd 13 1036 66 1089 119 1142 4th 16 1039 69 1092 122 1145 5th 19 1042 72 1095 125 1148 6th 22 1045 75 1098 128 1151 7th 25 1048 78 1101 131 1154 8th 28 1051 81 1104 134 1157 9th 31 1054 84 1107 137 1160 10th 34 1057 87 1110 140 1163 11th 37 1060 90 1113 143 1166 12th 40 1063 93 1116 146 1169 T7_Phy Mentor Design Layout ---------------------------- Pages in the T7 OCB_I/F Page Function ---- -------------------------------------------------- 1 Connection to OCB, Data Bus, Valid Reg Adrs Bus, Valid Read, Valid Write and Strobe 2 Decode 16 Raw ADC Memory Blocks Rd & Wrt 3 Decode 32 Global Registers Rd & Wrt 4 Decode Read 8 CSR's for each of 8 TT's 5 Decode 8 Final Output Memory Blocks Rd & Wrt 6 Decode Write 8 CSR's for each of 8 TT's 7 Decode 16 Et Look-Up Memory Blocks Rd & Wrt Pages in the T7 TT_Cell Page Function ---- -------------------------------------------------- 1 ADC Data Receivers, ADC Data Delay Adjust, Stop Comparator for ADC Monitor Data Writing 2 ADC Memory Block, Input Multiplexer 3 Output Memory Block, Output Multiplexer 4 TT_CSR: Constant Et Value, Output Mux Control 5 TT_CSR: ADC Data Delay Control, Input Mux Control Stop ADC Monitor Data Writing Comparator Reference, Stop ADC Monitor Data Writing Mode 6 Filter 7 Et Look-Up Memory 8 Pseudo Random Noise Generators 9 Stop ADC Monitor Data Writing Control Logic Pages in the T7 Timing_Generator Page Function ---- -------------------------------------------------- 1 Clock Receiver Distributor, SCLD Receiver Distributor, ADC Clock Driver, BX Number Generator, ADC Mem Blk Adrs Gen, Output Mem Blk Adrs Gen, Double Buffer Update Control, PRN Shift Control 2 Read ADC Mem A Port Write Enable Register, LED Driver, Status to BC PAL Driver, DP FPGA Access Connector, Read status of signals in Timing and Control. Pages in the T7 Channel Link Driver Page Function ---- -------------------------------------------------- 1 Serial Et for EM and HD of Channels 3:0, Serial BX Number, Frame Marker, Parity 2 Serial Et for EM and HD of Channels 7:4, Serial Reserved Signals 3:0 Pages in the T7 Chan_Lnk_Output_Shifter Page Function ---- -------------------------------------------------- 1 All of the data paths through the Channel Link Output Shifter. 2 Status Register to read back the 0,0 EM Et BX_Number data pair that is sent to the TAB. Pages in the T7 Mem_A_Port_Adrs_Ctrl Page Function ---- -------------------------------------------------- 1 Address generator and its control. Ctrl Reg 0 and 1. 2 Readback of the Last Address. Single Sheet Components in T7_Phy: T7_Top, Data_Path, Frame_Shift_and_Chan_Lnk, Shifter_for_One_Lane, PRN_Shift_Control, SCLD_Rec_Dist, Clock_Rec_Dist, Drive_ADC_Clock, Double_Buf_Update_Enable, BX_Number_Gen, LED_Driver, Status_to_BC_PAL, Access_Connector, ADC_Data_Receiver, Align_ADC_Data, PRN_Generator, Mem_Blk_1k_10, Mem_Blk_2k_8, Mem_Blk_1k_16, Control_Reg, Status_Reg ============================================================================ ============================================================================ Below here is general information about designing firmware for the Data Path FPGAs. Recall the Address Space Layout: Register Address Decimal Function ---=======-- --------------------------------------------- 0:15 Board Control PAL 16 Registers 512:527 FPGA Global Registers 16 Registers 768:783 TT #0 EM Channel Registers 16 Registers 896:911 TT #0 HD Channel Registers 16 Registers 1024:2047 TT #0 EM and HD Filter Output Et Data Memory 1k 2048:3071 TT #0 EM Raw ADC Data Memory 1k 3072:4095 TT #0 HD Raw ADC Data Memory 1k 4096:6143 TT #0 EM Et Lookup Memory 2k 6144:8191 TT #0 HD Et Lookup Memory 2k TT #1 starts at Register Address 8192 TT #2 starts at Register Address 16384 TT #3 starts at Register Address 24576 TT #4 starts at Register Address 32768 TT #5 starts at Register Address 40960 TT #6 starts at Register Address 49152 TT #7 starts at Register Address 57344 Recall the Address Space Layout: Register Address Hex Function -----===---- --------------------------------------------- 0:F Board Control PAL 16 Registers 200:20F FPGA Global Registers 16 Registers 300:30F TT #0 EM Channel Registers 16 Registers 380:38F TT #0 HD Channel Registers 16 Registers 400:7FF TT #0 EM and HD Filter Output Et Data Memory 1k 800:BFF TT #0 EM Raw ADC Data Memory 1k C00:FFF TT #0 HD Raw ADC Data Memory 1k 1000:17FF TT #0 EM Et Lookup Memory 2k 1800:1FFF TT #0 HD Et Lookup Memory 2k TT #1 starts at Register Address 2000 TT #2 starts at Register Address 4000 TT #3 starts at Register Address 6000 TT #4 starts at Register Address 8000 TT #5 starts at Register Address A000 TT #6 starts at Register Address C000 TT #7 starts at Register Address E000