Description of the SCLD FPGA Test Firmwares -------------------------------------------------- Original Rev. 24-OCT-2005 Most Recent Rev. 25-OCT-2005 TEST #3 TEST #5 ------- SCLD T5 Firmware ---------------------- Move of the Sidewalk ADF Crate Timing wrt the BX -------------------------------------------------- Org Rev. 19-OCT-2005 Cur Rev. 9-JAN-2006 The sections in this note are: Intent of the Move Options for the Move Review the Sidewalk ADF Crate Timing in place since 18-MAY-2005 Review of the ADF Data Path T7 Latency Review of the Monitor Data and Simulation Data Addresses Definition of what will be implemented for this Timing Change Intent of the Move ------------------ The intent of the October 2005 move of the timing of the Sidewalk ADF Crate is to put it at its advertised timing wrt the real BX. The sole purpose of this is to allow others to study the overall latency of the Run 2B L1 Cal Trig with the ADF Crate running at its advertized timing (even though it receives the BLS signals late). Making this change in ADF Crate timing requires a new version of SCLD firmware (we are currently at SCLD Rev T3) and optionally new ADF Data Path FPGA firmware. Options for the Move -------------------- The main consideration here is how much of the design changes in the T7 moving to T8 Data Path FPGA that have taken place since 16-MAY-2005 should be issued to the Sidewalk Test-stand along with this timing change. A full range of options is available from including all changes to including absolutely none of the integrated T7 to T8 changes. Review the Sidewalk ADF Crate Timing in place since 18-MAY-2005 --------------------------------------------------------------- All numbers here that state timing wrt real BX are the timing wrt the leading edge of the real BX marker at the panel on the front of CMC rack M100, i.e. signal delays on cables have been removed from these numbers. Real BX to leading edge of LvBX signal on the ADF Crate backplane: 1203 nsec First Real BX of the turn to the leading edge of the Begin_of_Turn signal on the ADF Crate backplane: 412 nsec Leading edge of the backplane LvBX or BOT marker to the leading edge of the First_X8_Edge_Enb signal on the ADF pcb is: 64:73 nsec BLS signal peak at the Patch Panel Monitor Point to the leading edge of the backplane LvBX marker signal: 360 nsec Putting this together implies that the peak of the BLS signal arrives on the sidewalk 1203 nsec - 360 nsec = 843 nsec after the real BX as given by the marker output from the panel on the CMC rack. That is a long MCH to Sidewalk delay. Review of the ADF Data Path T7 Latency -------------------------------------- These number are for the T7 that has been in use on the Sidewalk since 18-MAY-2005. An interesting path to follow is: start from the backplane LvBX marker and work forward until the end of the Et data output from the Channel Link chips. 1. Leading edge of backplane LvBX marker to ADF pcb First_X8_Edge_Enb is 68 nsec. First_X8_Edge_Enb to leading edge of the X8_Clk is 12 nsec. This means that the Data Path FPGA I/O Block FDE ingests the LvBX signal 80 nsec after it appears on the backplane. 2. Once ingested by the Data Path FPGA I/O Block FDE the Live_BX_Enb is delayed by a full tick before being sent out from the Timing Generator section of the Data Path FPGA. Recall that Live_BX_Enb is a clock enable signal and thus makes its transitions shortly after positive edges of the X8_Clock that have been selected by the First_X8_Edge_Enb signal. 3. The asserted Live_BX_Enb signal immediately causes the Data Path Cell Output Multiplexer to switch to selecting Filtered Et data. 4. The next positive edge of the X8_Clock that has been selected by the First_X8_Edge_Enb causes the Filtered Et data to be parallel loaded into the Shifter for One Lane and thus the LSB data to appear at the output of the shifter. 5. The Output Shifter then uses two cycles of the X8_Clock while it synchronously generates the Parity across both Data Path FPGAs. 6. The next X8_Clock positive edge clocks the Data Path FPGA I/O Block FD outputs and thus sends the LSB of this Et data to the Channel Link chips. 7. The next X8_Clock positive edge clocks the LSB of the Et data into the Channel Link chip. 8. The Propigation Delay of the Channel Link Transmitter is: 1.5 clock periods + 4.4 nsec which is 1.5 x 16.5 nsec + 4.4 nsec = 29 nsec where the 16.5 is just 132 / 8. 9. This beam crossings Et data will have completely left the ADF card 132 nsec later. By that time the Channel Link will have finished sending the MSB of the Et data and will have actuall been handed the next beam crossing's data. Adding up the 9 steps above says that the end of the frame of Et data leaves the ADF card 570 nsec after the leading edge of the backplane LvBX signal. The real BX to leading edge of LvBX signal on the backplane is 1203 nsec. Thus, right now, the end of the Et data output for a given BX happens 570 nsec + 1203 nsec = 1773 nsec after the that BX. We want this to be 1458 nsec so the ADF Crate must move earlier by 1773 nsec - 1458 nsec = 315 nsec. This is 16.7 RF Buckets We are currently delaying the digitized BLS signals by: 8 x 33 nsec = 264 nsec. This implies that if we shift the Sidewalk ADF Crate 315 nsec earlier than its current timing and set zero delay of the digitized BLS signals we will be sampling the BLS signals 51 nsec early then now. 16 RF Buckets is 16 x 18.83 nsec = 301 nsec 17 RF Buckets is 17 x 18.83 nsec = 320 nsec SCLD T3 is delaying the LvBX and BOT signals by 15 ticks = 1975 nsec. One should also be able to work forward through the ADF-2 card design and the T7 design and calculate how long it takes to get from receiving the peak of the BLS analog signal from a live BX to step #4 in the table above. Note that the sum of the delay from step #4 through step #9 in the table above is: 227 nsec. 1. Delay in the analog signal processing: 66 nsec 2. Delay in the ADC from analog sample to digital data output: 165 nsec 3. Delay to the output of the Data Path FPGA ADC Data I/O Block FDE: 33 nsec 4. Dealy to the output of the ADC Data Alignment Shift Register when set for minimum delay: 33 nsec (Data Alignment steps are 33 nsec with the range of steps 1:16 ) 5. Delay to output of the Filter delay: 33 nsec 6. Delay to clocking the address into the Et Lookup Menory: 33 nsec 7. Delay doing the lookup and delivering the Et value to the ouput shifter, i.e. delay until the Et data has been clocked into the output shift register: 132 nsec (in T7 this is where things come back to once per tick) Total of steps #1 through #7 495 nsec BLS signal peak to clocking Et data into the ouput shifter Thus we currently expect the total processing time from BLS signal peak to ADF finishing its output to be: 495 nsec + 227 nsec = 722 nsec Now does the current mode of operation all check ? i.e. do the number all add up and cross check ? We calculate that the ADF currently finishes its output at 570 nsec after the leading edge of the backplane LvBX signal. We know that the peak of the BLS signal is currently at 360 nsec before the leading edge of the backplane LvBX signal. Thus as currently running we have a BLS signal peak to ADF finishing its output of 570 nsec + 360 nsec = 930 nsec. We calculate above that this should be 722 nsec. 930 nsec - 722 nsec is 208 nsec. Where are the 208 nsec ? Well currently we are holding onto the digitized BLS data for 8 x 33 nsec = 264 nsec. Thus the total ADF processing time from BLS signal peak to ADF finishing outputing Et data to be: 722 nsec + 264 nsec = 986 nsec. This would say that this setup is fine if the BLS signal peak were at 416 nsec before the leading edge of the backplane LvBX signal. Pg 155 29-July-2005 shows the peak of the Raw ADC signal at Reg Adrs 2072 where it ideally would be at 2073, i.e. 33 nsec later. i.e. the BLS signal was already starting to fall a little bit by the time the sample was taken that determined the Et output value. Thus things would be better if either the BLS signal were delayed by 33 nsec or the ADF Crate moved 33 nsec earlier. Review of the Monitor Data and Simulation Data Addresses -------------------------------------------------------- Recall how the fully synchronous dual port memory blocks work: To write, setup the write data and memory address and then on the next enabled clock edge the write operation takes place. To read, setup the memory address and then on the next enabled clock edge the address is latched into the memory block and the read data is delivered to the data output lines. The general understanding is that the Memory Block Address that holds Monitor Data for BX Number "N" must be used to hold the Simulation Data for BX Number "N+1". This is because a on a given clock edge (i.e. a given memory block address) the ADF-2 card will both clock the Monitor data into the memory block and into the next processing step, for example clock raw ADC data into the memory block and into the filter. But, when playing back Simulation data that same clock edge will cause the memory block to retrieve the Simulation data from that memory address and then on the next clock edge this simulation data will be clocked into the the next processing step. To state the effect of this from all directions: A given memory address holds the Monitor data for BX "N" and holds the Simulation data for BX "N+1". If the Monitor data for a given BX is held at memory address "N" then the Simulation data for that same BX is held at memory addres "N-1" If the Simulation data for a given BX is held at memory address "N" then the Monitor data for that same BX is held at memory address "N+1" What was studied and proven about T7 is the following (all of this was done by studying 0,0 EM): The Final Output Memory Block starts at Reg Adrs 1024. It was verified that the Final Output Monitor Data for Tick #1 is at Reg Adrs 1024. Thus, the current understanding says that the Simulation data for Tick #2 must be stored at Reg Adrs 1024. The Raw ADC Memory Block starts at Reg Adrs 2048. It was verified that the Raw ADC Simulation Data that determines the ADF-2 card's Et output value (with Data Path version T7 firmware) for the first Live BX, i.e. Tick #7, must be stored at Reg Adrs 2072. The current understanding is that this implies that the Raw ADC Monitor Data for the ADC sample that controls the ADF-2 card's Et output for the first Live BX, i.e. Tick #7, is stored at Reg Adrs 2073. Definition of what will be implemented for this Timing Change ------------------------------------------------------------- - Retain using the 16-MAY-2005 T7 firmware on the Sidewalk. - SCLD Firmware will move to version T5. - Move the ADF Crate control signals from the SCLD 17 RF Buckets earlier. - Add control of the Save Monitor Data signal to the functions performed by the SCLD Firmare with the following definition: ADF to SCLD ADF ADF ADF ADF Signal Crate 0 Crate 1 Crate 2 Crate 3 -------------- -------------- ------- ------- ------- Assert ADF Crate to Save Monitor Spare Spare Spare SCLD Signal #0 Data on next L1_Accept with L1_Qual "CollectStatus" Asserted ADF Crate to Immediately Spare Spare Spare SCLD Signal #1 Assert Save Monitor Data - Note: The 4 ADF Crates are Named (numbered) by their Virtical Interconnect number. - Recall the Hardware Qualifiers for L1 Accepts L1_Qual_7 is "Hardware" type and is controlled by a signal that indicates whether or not the Trigger Framework captured Monitoring data when the L1_accept for this event was issued. Coming out of the SCL Receiver, L1_Qual_7 is on the same pin as the L3_Transfer_Number_7. - Recall the LEDs on the front of the SCLD pcb Loc Ref Col T5 SCLD Usage Saclay Usage --- --- --- ---------------------------------- ---------------- Top D2 Red +5 Volt Power +5 Volt Power D3 Grn FPGA Configuration DONE FPGA Config DONE D4 Grn -nc- Clock Locked D5 Grn -nc- Delays Loaded D6 Yel Save_Monit_Data stretched 10 msec Cable 0 Plugged D7 Yel ADF Crt 0 Sig 0 Enb Trig Save Monit Cable 1 Plugged D8 Yel ADF Crt 0 Sig 1 Force Save Monit Cable 2 Plugged D9 Yel SCL_SYNCERROR signal from SCLR Cable 3 Plugged D10 Yel SCL_READY signal from SCLR Cable 4 Plugged Bot D11 Grn SCL_ACK signal to SCL Rcvr User LED SCLD T5 Firmware ---------------------- Mentor Graphics Design Layout --------------------------------- Cur Rev. 1-MAY-2006 Mentor Layout of the SCLD T5 Design Design Top SCLD_T5_TOP Sheet 1 Symbols for: Receiver Clock and Control Signals Control Signal Delay SCL Receiver Control SCLD_T5_TOP Sheet 2 Symbols for: 5x ADF Crate Signal Receivers Generate Save Monitor Data Signal SCLD_T5_TOP Sheet 3 Symbols for: 6x Output Drivers: SCL_Init, BX_Clock, Spare_SCLD_to_ADF, Live_BX, Begin_Turn, Save_Monitor_Data Receiver for the Clock and Control Signals from the SCL Receiver Instanced on Sheet #1 of the TOP T5_SCL_Rec_Input Sheet 1 Logic for receiving: 53MHz_Clock, BX_Clock, Begin_Turn, SCL_Init, Live_BX This logic includes the RF Bucket delay. T5_SCL_Rec_Input Sheet 2 Logic for receiving: L1_Period, L1_Accept, L1_Qualifier_7 This logic includes the RF Bucket delay. Control Signal Delay Instanced on Sheet #1 of the TOP T5_Control_Delay Sheet 1 Logic for aligning the Live_BX and Begin_Turn signals in steps of the BX_Clock, i.e. steps of 132 nsec. Control of the SCL Receiver Instanced on Sheet #1 of the TOP SCL_Rec_Control Sheet 1 Logic for controlling the SCL Receiver Push Button 01 LEDs D9, D10, D11 Receive signals from the ADF Maestro card Instanced on Sheet #2 of the TOP T5_ADF_Input Sheet 1 Logic for receiving the 2 signals from one of the ADF Maestro cards. Generate the Save Monitor Data Signal Instanced on Sheet #2 of the TOP T5_Gen_Save_Monit Sheet 1 Logic for generating the Save Monitor Data signal. LEDs D6, D7, D8 Drivers for signals from the SCLD card to the ADF Maestro Instanced on Sheet #3 of the TOP SCLD_Output_Drivers Sheet 1 Logic for driving the signals from the SCLD card to the ADF Meastro card.