Description of the ADF-2 Circuit Board --------------------- Initial Rev: 13-MAY-2004 Current Rev: 28-MAY-2004 This file provides an overall description of the ADF-2 circuit board. Details about most of the ADF-2 circuit board functions are presented here including information about how these functions were implemented. The details about the Data Path FPGA and the Board Control PAL are presented in other files. The purpose of the ADF-2 is to receive the analog BLS signals from the platform, digitize and filter these signals, and then send out the resulting Et energy values to the TAB cards, i.e. the next card in the Run IIB L1 Calorimeter Trigger signal processing chain. To assist in accomplishing this function the ADF-2 receives timing and control information from the SCLD card and communicates via the VME bus with the Trigger Control Computer (TCC). TCC communicates with the ADF-2 in order to: configure firmware into its 2 FPGAs, load control parameters into the ADF-2's various functional blocks (Analog-ADC, Filter, serial output), and to collect monitoring information. The full ADF system consists of 80 ADF cards located in 4 crates. The crates themselves are commercial VME-64X crates. During normal Physics operation all 80 ADF-2 cards work together in lock step. Timing and control signals from the single SCLD card are delivered isochronously to all 80 ADF-2 cards. During special operations, e.g. testing under control of TCC, individual ADF-2 cards may be performing different operations at a given time. A block diagram view of the ADF-2 card is presented in: www.pa.msu.edu/hep/d0/ftp/run2b/l1cal/hardware/adf_2/drawings/ adf_2_card_block_diagram.pdf The rest of the ADF description is provided in the following sections: - Analog Input Signals from the BLS - Analog Signal Processing and ADC Circuit - Data Path FPGAs - High Speed Serial Output Data to the TAB - Timing and Control from the SCLD - On Card Distribution of SCLD Timing and Control - Maestro ADF - Crate Wide Signals - Status Signals from the FPGAs - FPGA Configuration - JTAG String - VME Interface - Power Entry and Power On Card Power Supplies - Front Panel Indicators - Board Control PAL Analog Input Signals from the BLS --------------------------------- The ADF-2 card processes 32 BLS signals. These signals are the EM and Hadronic (HD) sections of 16 Trigger Towers (TT's). The 16 TT's serviced by a given ADF-2 card are a 4x4 array of TT's from the full 40 in eta by 32 in phi array of TT's that make up the L1 Cal Trigger eta,phi coverage. Each BLS signal is received differentially, i.e. each input signal consists of "direct" and "complement" components. Use of differential signaling is standard practice when sending precision analog signals a long distance. The input signals, that result from energy deposition in the Calorimeter are pulses that last for about 750 nsec. They have a rise time of about 150 nsec, remain at 90 to 95% of their peak amplitude for about 100 nsec, and fall back to zero in about 500 nsec. The "Physics Information" is carried in the peak amplitude of the signal. Examples of these signals can be seen in the directory: www.pa.msu.edu/hep/d0/ftp/l1/cal_trig/pictures/trig_pickoff/ A good scope picture to look at to get a good general idea of the waveform is: tek00900.pdf The frequency components of interest start at about 1 MHz and go up to about 15 or 20 MHz. Anything outside of that range is noise i.e. not Physics signal. The peak input differential signal amplitude that the ADF-2 must linearly process is about 6 Volts. It is OK if it saturates at that input signal amplitude just so long as: it can recover by the next beam crossing, and that during saturation its digital output indicates a full scale energy signal. The official definition of the input signal amplitude is presented at the beginning of: www.pa.msu.edu/hep/d0/ftp/l1/cal_trig/hardware/ctfe/run_ii_ctfe_analog.txt The analog input signals (64 total counting the direct and complement sides of the 32 BLS signals) arrive at the ADF-2 card's "P2" connector. The pinout of that connector is presented in the following table. ADF-2 Analog Signal Input P2 Connector Pinout ------------------------------------------------------------ Row Column "C" Column "A" Column "Z" --- --------------- --------------- ----------- 1 Ch_00_EM_P Ch_00_HD_P 2 Ch_00_EM_N Ch_00_HD_N VME_64X_GND 3 Ch_04_EM_P Ch_04_HD_P 4 Ch_04_EM_N Ch_04_HD_N VME_64X_GND 5 Ch_08_EM_P Ch_08_HD_P 6 Ch_08_EM_N Ch_08_HD_N VME_64X_GND 7 Ch_12_EM_P Ch_12_HD_P 8 Ch_12_EM_N Ch_12_HD_N VME_64X_GND 9 Ch_01_EM_P Ch_01_HD_P 10 Ch_01_EM_N Ch_01_HD_N VME_64X_GND 11 Ch_05_EM_P Ch_05_HD_P 12 Ch_05_EM_N Ch_05_HD_N VME_64X_GND 13 Ch_09_EM_P Ch_09_HD_P 14 Ch_09_EM_N Ch_09_HD_N VME_64X_GND 15 Ch_13_EM_P Ch_13_HD_P 16 Ch_13_EM_N Ch_13_HD_N VME_64X_GND 17 Ch_02_EM_P Ch_02_HD_P 18 Ch_02_EM_N Ch_02_HD_N VME_64X_GND 19 Ch_06_EM_P Ch_06_HD_P 20 Ch_06_EM_N Ch_06_HD_N VME_64X_GND 21 Ch_10_EM_P Ch_10_HD_P 22 Ch_10_EM_N Ch_10_HD_N VME_64X_GND 23 Ch_14_EM_P Ch_14_HD_P 24 Ch_14_EM_N Ch_14_HD_N VME_64X_GND 25 Ch_03_EM_P Ch_03_HD_P 26 Ch_03_EM_N Ch_03_HD_N VME_64X_GND 27 Ch_07_EM_P Ch_07_HD_P 28 Ch_07_EM_N Ch_07_HD_N VME_64X_GND 29 Ch_11_EM_P Ch_11_HD_P 30 Ch_11_EM_N Ch_11_HD_N VME_64X_GND 31 Ch_15_EM_P Ch_15_HD_P 32 Ch_15_EM_N Ch_15_HD_N VME_64X_GND VME-64X labels the pins on the P2 connector in the following way: +-------------------------+ | | | D1 C1 B1 A1 Z1 | | D2 C2 B2 A2 Z2 | | D3 C3 B3 A3 Z3 | . . . . . . . . . . . . . . . . . . . . . | D30 C30 B30 A30 Z30 | | D31 C31 B31 A31 Z31 | | D32 C32 B32 A32 Z32 | | | +-------------------------+ View looking from the back of the backplane In this table and in all of the ADF-2 documentation these signals are numbered: Channel 0 through 15 and EM and HD. As plugged into the full eta,phi map these 16 TT's will be arranged in the following way: ADF-2 Relative Ch (15:0) eta,phi ------------- ----------- 0 EM,HD 0,0 EM,HD 1 0,1 2 0,2 3 0,3 4 1,0 5 1,1 6 1,2 7 1,3 8 2,0 9 2,1 10 2,2 11 2,3 12 3,0 13 3,1 14 3,2 15 3,3 Analog Signal Processing and ADC Circuit ---------------------------------------- The analog input signals to the ADF-2 card arrive after traveling on about 140 feet of cable from the BLS cards in the platform. Upon reception these signals are terminated (to prevent reflection and waveform distortion), pass through a differential amplifier where the frequency response has been controlled and the common-mode signal can be rejected, and then pass into a 10 bit sampling ADC which digitizes these signals at four times the BX_Clock rate. The BX_Clock frequency is exactly one 7th of the Tevatron RF frequency or about 7.57 MHz. This results in sampling (i.e. digitizing) the ADF-2 analog input signals about once every 33 nsec. A diagram of the input termination and differential amplifier circuit is presented in: www.pa.msu.edu/hep/d0/ftp/run2b/l1cal/hardware/adf_2/drawings/ adf_2_differential_amp.pdf The termination circuit is designed to match the 78 or 80 Ohm characteristic impedance of the long BLS cables. The 1 meg Ohm resistors at the input, labeled R1 and R2, are just used to drain the DC component from the BLS output (and thus prevent signal distortion due to charge on the Z5U dielectric used in the coupling capacitors. Termination resistors R3 and R4 in parallel with the input resistance to the differential amplifier (which is basically set by R5 and R6) provide the cable termination. Capacitors C1 and C2 are matched with capacitors at the driving end of the cable (i.e. there is symmetric series RC at both ends of the cable) to provide a termination network with better undershoot performance. This circuit is from Paulo Franzini. The differential gain of the amplifier is about 1/3. This is set by the ratio of R5 (R6) to R7 (R8). The gain is set so that a full scale input signal just drives the ADC input to full scale which is 2 Volt swing. The frequency response of the differential amplifier is controlled by a number of capacitors. The low frequency cutoff is set by C1 (C2) working into 80 Ohms. This sets a low frequency cutoff at about 38 usec. The high frequency cutoff is set by C3 vs R7 (C4 vs R8) at about 9.0 nsec and again by R9, R10, C5, C6, C7 at about 8.5 nsec. The reason for full network of R9, R10, C5, C6, C7 it to explicitly filter on both the normal mode and common mode high frequency input to the ADC. The concern here is the very wide full power analog input bandwidth of the ADC. This full network reduces the effect of the parasitic series resistance in these capacitors. Resistors R9 and R10 were scaled so that they also control the maximum input current to the ADC under fault conditions, for example if the VEE power supply to the differential amplifier should fail. Zero energy deposited in the Calorimeter is represented by an input signal to the ADF-2 of zero Volts differential. The zero to full scale differential input to the ADC must swing from -1.0 Volts to +1.0 Volts. To accomplish this the differential amplifier must translate a zero Volt differential input to a -1.0 Volt differential output. That is, the differential amplifier provides an offset of -1.0 Volts while providing a gain of +1/3 to the normal mode signal. This -1.0 Volt offset is controlled by the Pedestal DAC. The resistors have all be scaled so that the Pedestal DAC can swing the differential input to the ADC from a little bit under -1.0 Volts up to 0.0 Volts. This represents a swing from a little bit under the ADC's "zero" up to the ADC's mid scale. There are a number of reasons for providing this relatively large range in pedestal control. - During normal Physics operation the pedestal is adjusted so that with zero energy deposited in the Calorimeter the ADC will have an output of 8 counts (or whatever the uniform pedestal target is that is picked for all channels in the system). This allows the L1 Cal Trig system to correctly handle both positive and negative noise (and not just "rectify" the input noise signal). - The Pedestal DAC is a 12 bit device which can swing the 10 bit ADC through just a little more than 1/2 of full scale. Thus the Pedestal DAC can set the ADC's pedestal within a fraction of a count. - During production testing the Pedestal DAC can set the ADC to mid scale so that, with the ADF's AC coupled input network, a sin wave generator can be used to test the full Analog-ADC circuit. These tests include response as a function of frequency (looking for missing or incorrect parts) and FFT of a sin wave input at about 1/5 of the sampling frequency (looking for spurs i.e. distortion). - In stand alone, after the full system is assembled, this wide accurate pedestal swing can be used to check the gain and linearity of the Analog-ADC section of the ADF-2 card. It can do this because the BLS input signal is AC coupled. This is an important feature in real life for quickly diagnosing the source of the problem when some TT signal does not look correct in the readout data. That is, you can quickly test whether or not the problem is most likely in the ADF-2 card or most likely a problem with the signal that is being sent to the ADF-2 card. The Pedestal DAC's receive their digital control over a 3 line serial data system. They are controlled from the Board Control PAL (which will be described later). The 3 line serial data system is nice because it minimizes the number of traces that are needed to control the Pedestal DAC's. During normal operation these control lines are static and do not add any noise to the system. The serial data setup is fast enough so that in just a second or two the TCC can program all the Pedestals in the full system. The Pedestal DAC are located below the Differential Amplifier - ADC section is a part of the card that does not run the full width because of the front panel mounting area. From this location there are clear routing channels to connect the DAC outputs to the Differential Amplifiers. All 4 octal DAC's share a common external reference supply that is located with them. A drawing of the Pedestal DAC's is shown in: www.pa.msu.edu/hep/d0/ftp/run2b/l1cal/hardware/adf_2/drawings/ adf_2_ped_dacs_1.pdf The correct common mode output Voltage from the differential amplifier is an important parameter for the accurate operation of the ADC. The common mode Voltage going into the ADC must be within 150 mV of VDD/3 for it to meet specified accuracy. The circuit used to control the differential amplifier's common mode output consists of R41, R42, and C8. This circuit is shared by the EM and HD sections of each TT. When selecting these resistor values you must keep in mind the internal dividers inside the THS4141 differential amplifiers. The intent of this circuit it to track the VDD supply. E.G. if the VDD supply is 50 mV low then the Vocm pin on the THS4141 will track accordingly and thus the common mode input voltage to the ADC's will continue to be in the center of its operating range. The ADC chips themselves are shown in the drawing at: www.pa.msu.edu/hep/d0/ftp/run2b/l1cal/hardware/adf_2/drawings/ adf_2_adc_10_bit.pdf The intent is to clock all 32 ADC's on the ADF-2 circuit board at the same time. The reason for this is to lower the digital noise in the Analog-ADC section of the card (or at least confine it to narrow windows in time). In any case there is very little to be gained by adjusting the timing of the ADC samples any closer than 16 nsec of the optimum point in time. This can be seen by looking at the BLS signal waveform in the files presented above. The internal noise of the ADF-2 itself must be low enough so that with no input signal the ADC output is always the same count or at the most two adjacent counts. The ADC's on the card can be powered down. This feature is used so that when power is first applied the the ADF-2 card the ADC's do not all start up at once, nor do they drive their digital outputs to the Data Path FPGAs which will not have powered up at this time. Once the crate power supplies have stabilized and the DC/DC Converters are running on the ADF-2 cards, the Trigger Control Computer (TCC) will enable the ADC to operate by setting a bit in a Board Control Register. Turning them on one ADF-2 card at a time will also limit the "shock" of the 76 Amps of power required by the 640 ADC's in a crate. The reference Voltage used to set the scale for the ADC's is generated internally in each ADC. It is filtered externally as recommended in the data sheet. There are no other distributed reference Voltages used in the Analog-ADC section. The digital outputs from the ADC's pass through 100 Ohm resistor packs that are located immediately adjacent to each ADC. The intent of this is not to series terminate these lines but rather to limit the peak switching currents that will be pulled by the ADC's when switching these 320 lines on each ADF-2 card. For some reason the designer of the selected ADC chose to make the digital outputs switch in 1 nsec and be capable of driving 20 ma of current. Without doing something to limit these digital output switching currents (as is now common practice in high speed ADC circuit design and as they do on their own demo board for this part) the entire Analog-ADC section of the ADF-2 card could become just another shock excited VHF resonator. The digital output from the ADC's is straight 10 bit binary, i.e. not 2's complement. The following table shows the approximate scales as the signal flows through the ADF-2. Energy Differential Differential ADC Deposited in Volts into Volts into Digital the Calorimeter the ADF-2 the ADC Output --------------- ------------ ------------ ------- zero GeV 0 V - 1 V 0x 000 mid GeV 3 0 0x 1ff max GeV 6 + 1 0x 3ff The Analog-ADC section of the ADF-2 card is layed out in a regular 4x4 array. The individual differential amplifier ADC "unit cells" have been arranged to eliminate the criss-cross in both the traces brining the analog signals into these circuits and the digital lines carrying the ADC output to the Data Path FPGAs. The analog components are on the top side of the circuit board. The ADC's and other digital parts are on the back of the circuit board. The analog traces such as the Pedestal DAC output levels have been kept isolated from the digital circuits. In the Analog-ADC section of the ADF-2, bypass capacitors are used on every chip in the recommended in the data sheets and in the way consistent with good high frequency analog design. The circuit board components have been arranged to keep circulating currents out of the power and ground planes in this section of the card. The one corner where the analog circuits get close to the digital Channel Link components contains a slit in the ground planes to isolate these sections. The power supplies for the Pedestal DAC's, differential amplifiers, and ADC's are separate from the power supplies used by the digital parts of the ADF-2 card. That aspect of the ADF-2 design is covered in a later section of this document. Data Path FPGAs ---------------- The next logical step in the signal processing on the ADF-2 card is the digital filtering that will take place in the Data Path FPGAs. As such that topic will not be covered in this document. That topic is not covered here because the details about the filtering that is done by the Data Path FPGAs is a property of the firmware that is configured into them. This document covers the ADF-2 circuit board. What is presented here are the details of the signals that connect to the the Data Path FPGAs on the ADF-2 circuit board. It is the connection of these signals that set the "ground rules" for what it is possible to design in the Data Path FPGA firmware. These FPGAs have been given the name "Data Path" because their purpose is to process the data that flows through the ADF-2 card and not to control the operation of the ADF-2 card. In the design of the ADF-2 there is a strong attempt to keep separate the ideas and functions that are involved with board control from those that are involved with the processing of the data that flows through the board. The ADF-2 card uses 2 Data Path FPGAs which in the documentation are referred to by their Reference Designators U800 and U900 or more often by the shorthand "F0" and "F1". Data Path FPGA F0 services input channels 0:7 EM and HD while F1 services input channels 8:15 EM and HD. Thus each of the FPGAs receives the digital output from 16 ADC's or 160 signals in total. The Data Path FPGAs must process their input data in synchronized steps of 132 nsec. This is because the ADF-2 is responsible for sending out Et data to the TAB cards once every 132 nsec. In much of the D-Zero documentation these steps of 132 nsec are referred to as "ticks" and the clock signals that carry this "tick rate" timing are referred to as BX_Clock. To synchronize their operation the FPGAs receive 2 clock signals from the support logic on the ADF-2 card. One clock signal is at 8 times the tick rate and has the net name BX_x8_Clk in the ADF-2 design. This clock is locked to, i.e. is in a stable phase relationship with, the D-Zero Master Clock. That is accomplished through the SCL to SCLD connection to the ADF crate which will be covered later in this document. The BX_x8_Clk is stable and has very low jitter so it is safe to use it as a reference for applications that must multiply it up to a high frequency (e.g. as in the High Speed Serial Data Output Section). This BX_x8_Clk is the fundamental clock signal for the operation of the ADF-2 card. It is at 8 times the tick rate because there are a number of activities in the ADF-2 design that must happen at this rate. Inside of each Data Path FPGA the BX_x8_Clk is distributed over a "Global Clock Net". The Global Clock Net provides isochronous distribution of the BX_x8_Clk to all parts of the FPGA with an accurate predictable delay with respect to the external BX_x8_Clk. It is this isochronous distribution of the clock signal that is the key to modern synchronous logic design. With very few exception the logic in the FPGA will use the leading edge (the rising edge) of the BX_x8_Clk to initiate actions. The periods when the clock signal is at a high or low logic level are not used to control the logic. It is only the position in time of the rising edge that is important and it is only this edge that is used to by the logic in the FPGA. This idea of edge triggered flip-flops, i.e. D flip-flops, is the second key to modern synchronous logic design. The second clock signal that is delivered to the Data Path FPGAs is not actually a clock signal, rather it is a "clock enable" signal. Its purpose is not to directly provide timing information to the FPGAs but rather to select one of the rising edges of the BX_x8_Clk out of 8 to mark as the edge of the BX_x8_Clk that will be used to initiate activities that must happen at the BX rate. Because this signal is an clock enable signal it is generated so that it is at the active "enabling" level comfortable before the rising edge of the BX_x8_Clk that it wants to identify as the edge to be used for timing BX rate functions and so that it has returned to the disabling level well before the next rising edge of the BX_x8_Clk. In the ADF-2 design this clock enable signal is named BX_EDGE_ID and it is also distributed within the FPGA on a Global Clock Net. The use of clock enable signals and thus limiting the number of actual "clocks" in a design (i.e. limiting the number of clock domains) are the third and fourth keys to modern reliable synchronous logic design. Modern FPGAs facilitate this design technique by providing all their synchronous elements (i.e. fundamental clocked building blocks) with clock enable inputs. Besides the clock inputs, the ADF-2 circuit board provides the Data Path FPGAs with 5 control signals that come from the SCLD. These control signals update each tick and can be used to control what processing is done by the Data Path FPGA during that tick. These control signals come from the SCLD so that they can be distributed isochronously to all 80 ADF-2 cards in the full system. 4 of the 5 control signals have assigned tasks for use during Physics Beam running. The details about these Data Path FPGA control signals are presented in a later section of this file. The ADF-2 circuit board provides 4 status lines that run from each of the Data Path FPGAs back to the Board Control PAL. At this time we do not have an assigned task for any of these status lines. In the initial version the Board Control PAL will just make these signals visible in a VME register. The reason that these Data Path FPGA status signals are brought back to the Board Control PAL is because from there they can be driven onto the backplane crate wide status lines. From the backplane crate wide status lines this information can be sent back to the SCLD and from there it could cause an isochronous action to take place in all cards in all 4 crates. The point of all of this is that, if needed, the ADF-2 design can support things like "local triggering", i.e. one channel can see a signal over threshold and that can causes all ADF-2 cards to capture readout information about that beam crossing. The ADF-2 circuit board provides a connection from the On_Card_Bus to each Data Path FPGA. The On_Card_Bus provides the connection that allows VME assess to registers and memory that you might want to design into the FPGAs logic. The On_Card_Bus is design to make the connection to it very simple and easy to implement in the Data Path FPGA. The On_Card_Bus is documented in the file: www.pa.msu.edu/hep/d0/ftp/run2b/l1cal/hardware/adf_2/general/ on_card_bus_description.txt The On_Card_Bus provides a 16 bit wide data path to the FPGA. Up to 64k word wide address may be accessed within the FPGA. The layout of the addresses has be preassigned to organize the TCC software that must work with these parts and to minimize the resources that are used for address decoding. This layout of VME address is covered in the document: www.pa.msu.edu/hep/d0/ftp/run2b/l1cal/hardware/adf_2/general/ adf_2_vme_addressing.txt Note that just like all other aspects of the FPGA design the timing of the On_Card_Bus access to internal registers and memory must be constrained. The files that specifies the On_Card_Bus includes the information to accomplish this. The final connection that the ADF-2 circuit board makes with the Data Path FPGAs are the traces necessary to bring the data out of these FPGAs once every tick so that it can be sent to the TAB cards. This part of the ADF-2 is covered in detail in the next section. All data that is sent from the ADF-2 to the TAB card (except for some unused "fixed" bits) comes out of the Data Path FPGAs. High Speed Serial Output Data to the TAB ---------------------------------------- Before looking at the details of the High Speed Serial Output it is useful just to list the data that is transfered from the ADF-2 to the TAB once every tick. The data that is transfered is: 32 Et energy values each one is an 8 bit value 1 BX_Number this is also an 8 bit value Parity information 8 bits of parity per tick a Frame marker 1 asserted bit and 7 not asserted per tick An important point to notice is that all of these items are really 8 bit quantities. In addition to the listed items there are a few "unused Reserved" bits that are transfered on this link. These unused bits are held static, i.e. they do not change from one tick to the next. The significant point about the unused bits is that there is some spare capacity in the ADF-2 to TAB connection. A complete set of ADF-2 to TAB data is called a Frame. One Frame is all of the bits for all of the data items that are transfered from the ADF-2 to the TAB's. A complete Frame is transfered once very tick, i.e. once every period of the BX_Clk. Each ADF-2 card generates 3 identical copies of its output. This allows each ADF-2 card to send its output data to 3 TAB cards. This is a standard technique to eliminate the cracks from a trigger system, i.e. replicate the data so that each piece of the trigger logic that is responsible analyzing the trigger signals within some region also has the trigger signals that surround that region. A major concept in the ADF-2 to TAB connection, that it is easy to get confused about, is that there are TWO stages of serialization of the data. - The 8 bit data quantities that come out of the Data Path FPGAs are serialized by logic in the FPGA, i.e. these data quantities come out of the Data Path FPGA one bit at a time. - Then during Channel Link transmission this "serial data" is serialized again, by the Channel Link chip set, so that 42 bits can by transmitted over 7 differential signal pairs plus a differential clock pair (8 signals total). All of the data quantities that need to be transfered once per tick are 8 bit quantities. It is easy to bring each of these quantities out of the Data Path FPGAs one bit at a time. The data is transfered this way to control the number of FPGA pins that are needed to send this data out. To accomplish the data transfer in this way you just need to move the data out of the FPGAs in 8 steps per tick and then cycle the Channel Link at 8 times the tick rate. Moving the data at 8 times the tick rate is the reason why the fundamental clock in the ADF-2 is the BX_x8_Clk. A drawing that shows how the data is brought out of the Data Path FPGAs is presented in: www.pa.msu.edu/hep/d0/ftp/run2b/l1cal/hardware/adf_2/drawings/ data_path_fpga_output_to_channel_link.pdf The part played by the Channel Link chips in this data transfer is easy to understand. Unless you care about the bit level details you can just think of the Channel Link as two boxes. You hand the transmitter side 42 bits in parallel and give it a clock edge to tell is that it has another set of 42 bits to transfer. At the receiver your 42 bit come out, all in parallel, along with a clock edge to tell your receiving circuitry that a fresh set of 42 bits has arrived. This transfer takes place with only 8 signals between the Channel Link transmitter and receiver. The nice part about the small number of signals is that it makes the ADF-2 to TAB cabling easier to implement. The Channel Link chip set can transfer these sets of 42 bits at 8 times the BX_Clk rate or even faster. The details about how the Channel Link chip set does this are covered in: www.pa.msu.edu/hep/d0/ftp/run2b/l1cal/hardware/component_information/ national_ds90cr48x_data_sheet.pdf The thing to note is that, as used in the ADF-2 to TAB application, the 8th data line between the Channel Link transmitter and receiver is not used. Instead just 7 data lines (The Channel Link signals TxOut 0:6) and the clock line (i.e. 8 lines total are used). This allows the Channel Link chip set to transfer only 42 bits instead of its normal 48 bit (but makes the cabling a lot more convenient). To complete the specification of the ADF-2 to TAB data transfer a number of details need to be filed in. That information is provided in the following sections. The signals going into the Channel Link transmitter or coming out of the Channel Link receiver are numbered 0:47. Because this document is about the ADF-2 these 48 signals will be refered to by the Channel Link transmitter signals names. The receiver output with the same number is the same piece of information. Channel Link Channel Link Transmitter ADF to TAB Transmitter ADF to TAB Signal Name Data Item Signal Name Data Item ------------ ---------------- ------------ ---------------- TxIn_0 Channel 0 EM Et TxIn_24 Channel 12 EM Et TxIn_1 Channel 0 HD Et TxIn_25 Channel 12 HD Et TxIn_2 Channel 1 EM Et TxIn_26 Channel 13 EM Et TxIn_3 Channel 1 HD Et TxIn_27 Channel 13 HD Et TxIn_4 Channel 2 EM Et TxIn_28 Channel 14 EM Et TxIn_5 Channel 2 HD Et TxIn_29 Channel 14 HD Et TxIn_6 Channel 3 EM Et TxIn_30 not transported TxIn_7 Channel 3 HD Et TxIn_31 not transported TxIn_8 Channel 4 EM Et TxIn_32 Channel 15 EM Et TxIn_9 Channel 4 HD Et TxIn_33 Channel 15 HD Et TxIn_10 Channel 5 EM Et TxIn_34 BX_Number TxIn_11 Channel 5 HD Et TxIn_35 Reserved F0(3) TxIn_12 Channel 6 EM Et TxIn_36 Frame Marker TxIn_13 Channel 6 HD Et TxIn_37 Parity TxIn_14 Channel 7 EM Et TxIn_38 not transported TxIn_15 Channel 7 HD Et TxIn_39 not transported TxIn_16 Channel 8 EM Et TxIn_40 Reserved F0(0) TxIn_17 Channel 8 HD Et TxIn_41 Reserved F0(1) TxIn_18 Channel 9 EM Et TxIn_42 Reserved F0(2) TxIn_19 Channel 9 HD Et TxIn_43 Reserved F1(0) TxIn_20 Channel 10 EM Et TxIn_44 Reserved F1(1) TxIn_21 Channel 10 HD Et TxIn_45 Reserved F1(2) TxIn_22 Channel 11 EM Et TxIn_46 not transported TxIn_23 Channel 11 HD Et TxIn_47 not transported The Channel 0:7 Et signals come from Data Path FPGA F0. The Channel 8:15 Et signals come from the Data Path FPGA F1. The items labeled "not transported" are those items that are not transported across the Channel Link because as used for the ADF-2 to TAB connection the 8th transmitter to receiver data line is not connected. These inputs to the Channel Link transmitter chip are grounded. The BX_Number in a given ADF-2 to TAB data Frame is the official D-Zero BX_Number of the Accelerator Beam Crossing that caused the Channel Et data that is carried in that Frame. This is a number in the range 1:159 as defined in the SCL documentation which is available at: www.pa.msu.edu/hep/d0/l1/scl.html Frame Marker is a signal that identifies the beginning of each Frame of ADF-2 to TAB data. This bit is asserted for just the first Channel Link transfer of the 8 Channel Link transfers that make up a Frame of ADF-2 to Tab data. Note that all of the data items are sent Least Significant Bit first. This means that the Frame Marker is asserted in the same Channel Link transfer that carries the Least Significant Bit of each data item. The state of the Parity bit in a given Channel Link transfer is defined as the XOR across the Channel Et bits, the BX_Number bit, and the Frame bit that are contained in that Channel Link transfer. The logic for generating the Parity bit is shown in the figure about the serial data output section of the Data Path FPGA that was referenced above. The BX_Number, Frame Marker, and Parity bit all come out of Data Path FPGA F0. Logic in both Data Path FPGAs is used to generate the Parity bit as shown in the figure. In each Channel Link transfer there are currently 7 unused Reserved bits. As implemented in the Data Path FPGA, the state of these bits is controlled by the data in TCC controlled registers. For each unused Reserved signal, the table above show which Data Path FPGA this Channel Link bit comes from and which position in the register controls that bit. Data Path FPGA F0 controls 4 of the unused Reserved bits and Data Path FPGA F1 controls 3 of the unused Reserved bits. The intent is to set all of these bits Low for all Channel Link transfers. Timing and Control from the SCLD -------------------------------- The Timing and Control signals that come from the SCLD card to the ADF-2 cards are important because: they provide system timing that is locked to the SCL clock (D-Zero Master Clock) and they provide system control that can isochronously initiate activities on all 80 ADF-2 cards in the system. A description of the SCLD --> ADF-2 signals is provided in the following reference. This file will focus on how these signals are processed on the ADF-2 card. www.pa.msu.edu/hep/d0/ftp/run2b/l1cal/hardware/adf_2/general/ scld_adf_crate_control.txt The distribution of the SCLD timing and control signals is done in two steps. The SCLD sends timing and control signals to only 1 ADF-2 card in each of the 4 ADF Crates in the full system. The ADF-2 card that connects directly with the SCLD is called the "Maestro" ADF-2. The Maestro ADF-2 does not directly use the timing and control signals that it receives from the SCLD. Instead, the Maestro ADF-2 card just receives the timing and control signals from the SCLD and drives these signals onto VME-64X Reserved Bused backplane lines. Then the Maestro ADF-2 card, along with the other 19 ADF-2 cards in the crate, receives these timing and control signals from the VME-64X Reserved Bused backplane lines and uses them to control its operation. A block diagram of the SCLD timing and control signal distribution is available at: www.pa.msu.edu/hep/d0/ftp/run2b/l1cal/hardware/adf_2/drawings/ scld_control_signal_distribution.pdf The SCLD timing and control signals are sent to the Maestro ADF-2 card as LVDS level signals. On the ADF-2 card these LVDS signals are terminated and received with LVDS to 3.3V CMOS receivers U1051 and U1052. 6 of the 8 LVDS receivers in these 2 chips are used to receive the signals from the SCLD. The output from these receivers goes to the inputs of non-inverting open collector drivers (U1021) that are used to driver the VME-64X Reserved Bused backplane lines. These backplane lines are terminated at each end of the backplane with a 196 Ohm resistor to 2.94 Volts. To properly handle these terminations these signals require 48 ma drivers. As is the standard for open collector bus signals the asserted state of these control signals is the lower Voltage state. Because the drivers are non-inverting this "asserted equals low Voltage" is achieved by using the differential LVDS receiver to invert the signals as they are received from the SCLD. As will be noted later the only place where these SCLD timing and control signals are implemented as "low Voltage equals asserted" is on the open collector backplane. Each ADF-2 card receives these signals from the backplane with inverting receivers. By the time these SCLD timing and control signals are used on the ADF-2 card they are back in the "positive logic" setup. The distribution of BX_Clock timing signal from the SCLD is a slight exception to the above description. The BX_Clock timing signal is carried on the open collector backplane as a differential signal. It is received by U1051 (just like the other signals from the SCLD) and then it passes through two drivers: U1021 a non-inverting driver, and U1031 an inverting driver. The output from each of these drivers is connected to its own backplane line. The VME-64X Reserved Bus signals 4 and 5 were picked to carry the BX_Clock signal because they appear to be the quietest of the VME-64X Reserved Bus lines. The BX_Clock signal is received from the backplane on each of the 20 ADF-2 cards using a differential receivers as will be explained later. This special handling of the BX_Clock signal is necessary to deliver a clean stable clock to each of the ADF-2 cards in the crate. The scheme used to distribute the BX_Clock within the crate is described in more detail and shown in a schematic diagram in the following files: www.pa.msu.edu/hep/d0/ftp/run2b/l1cal/hardware/adf_2/general/ adf_crate_bx_clk_distribution.txt www.pa.msu.edu/hep/d0/ftp/run2b/l1cal/hardware/adf_2/drawings/ adf_crate_bx_clk_distribution.pdf All ADF-2 cards carry the components to receive the timing and control signals from the SCLD and drive them onto the backplane but only the drivers on the Maestro ADF-2 card are actually connected to the backplane. The isolation of the drivers on the other 19 ADF-2 cards in a crate is accomplished by not installing "zero Ohm" resistors R1021:R1027. These isolation jumpers are located close to the backplane connector to minimize the parasitic capacitive load on these backplane signals. This technique of fully isolating the unused drivers is used because it results in cleaner signals on the backplane. Notice that the SCLD control signals are received from the SCLD and driven onto the backplane with just straight buffers, i.e. these signals are not latched or "re-clocked" before going onto the backplane. This is easily possible because the state of these SCLD control signals can only change once every 132 nsec (once every tick) and if a signal is going to change state then it makes that change at a know point in the tick. This allows the SCLD control signals to pass the whole way to the target Data Path FPGA before they are clocked into it using the latch in the I/O Block of the FPGA. The Data Path FPGA document at the following location provides more information about the handling of the SCLD control signals inside these FPGAs. www.pa.msu.edu/hep/d0/ftp/run2b/l1cal/hardware/adf_2/general/ adf_2_data_path_fpga_description.txt On Card Distribution of SCLD Timing and Control ----------------------------------------------- The SCLD control signals from the backplane are received by an inverting buffer U1041. This inverting buffer flips these active low open collector control signals back to positive logic (asserted state is the high Voltage state). The raison d'etre for this buffer is to isolate the open collector backplane signals from the FPGA inputs which are not 5V tolerant. Note that during the power up sequence, the backplane signals will be at its high Voltage level before this buffer receives its VDD_LOGIC power supply. This conditions may exist for some seconds before the VDD_LOGIC power supply starts running. The chip used for this buffer must be able to handle this conditions. The output signals from this buffer go in parallel to input pins on the two Data Path FPGAs. These control signals are latched in the I/O Blocks of these pins by the BX_X8_CLK edge that marks the beginning of each processing tick. 5 of the 8 sections of the U1041 inverting buffer are used for receiving these backplane SCLD control signals. One additional section of this buffer is used for receiving the VME DS1* signal and delivering that signal to the Board Control PAL as net RCVD_DS1. The two unused sections are made available for emergency use by connecting their outputs to via's and their inputs to resistors that tie them to Ground. Because these are CMOS inputs they must be tied to a valid logic level. The BX_Clock from the SCLD is carried across the backplane as a differential pair of open collector signals. The normal mode of this differential signal is attenuated by resistors R1061:R1064 while its common mode is clamped to AC Ground by C1061. The effect of R1061:R1064 is also to isolate the parasitic capacitance of the stub traces on the ADF-2 card from the backplane signals. This helps to keep the edges of the backplane BX_Clock signals clean. R1061:R1064 are picked to scale the backplane open collector signals to a level appropriate for the LVDS Receiver. One section of the LVDS receiver U1052 is used for this function. The output from that receiver, net RCVD_BX_CLOCK, is a 3.3 Volt CMOS level signal that is only used as the reference input to the X8 Phase Lock Loop. ======================================================================== BX X8 Clock Generation -------------------------- Original Rev. 17-APR-2004 Current Rev. 6-JAN-2005 The purpose of this file is to present the technical details of the BX_Clock recovery from the backplane and the PLL multiplication to make the BX_X8_Clock. These functions are done on each ADF-2 card. Tevatron Frequencies and Periods: --------------------------------- Frequency Frequency at 150 GeV at 980 GeV ------------ ------------ Tevatron RF 53.10370 Mhz 53.10474 MHz 18.83108 nsec 18.83071 nsec TeV RF / 7 7.58624 MHz 7.58639 MHz 131.81756 nsec 131.81498 nsec TeV RF 4/7 30.34497 MHz 30.34557 MHz i.e. 4x BX 32.95439 nsec 32.95374 nsec TeV RF 8/7 60.68994 MHz 60.69113 MHz i.e. 8x BX 16.47719 nsec 16.47687 nsec Ramping from 150 GeV to 980 GeV is a total change of 19.58 ppm or a "pull" of +- 9.79 ppm from a center of 53.10422 MHz. The 8/7 center frequency is 60.69054 MHz Given a center frequency of 60.6905 MHz and a pull of +- 50 ppm means that the VCXO tunes from about 60.6875 to about 60.6935. Phase Lock Loop Design Sketch ----------------------------- VCO Gain Kvco Given a center frequency of 60.6905 MHz and a pull of +- 50 ppm is caused by a 3 Volt swing in the Control Voltage this is a gain of: 6069 Hz per 3 Volts or about 2 kHz per Volt or about 4 k pi radians per sec - Volt Phase Detector Gain Kp Gain of the Phase Detector XOR output is about 3.3 Volt output swing per 2 pi radians or about 0.5 Volt per radian. See the Analog Devices AD9901 data sheet for a description. The gain of this phase detector is constant and without a dead zone going through the lock region. Kvco x Kp is the number of radians at the VCO output that is picked up per second per radian of input to the Phase Detector, i.e. a "gain" expressed as radians out per radian of input per second that this condition exists. For the VCO and phase detector described above their Kvco x Kp product, i.e. gain is about: 4 k pi radians 0.5 Volt 2 k pi -------------- x -------- = ------ sec Volt radian sec If you want unity gain at some "loop control frequency" F then you need the gain of the loop filter, at frequency F, to be the inverse of the Kp Kvco gain at that frequency F which is: 1 ----- x Kp x Kvco 2pi F The 1 over 2pi F represents the time that you effectively accumulate phase when the loop is moving at frequency F. With the normal resistor input capacitor feedback integrator its gain is: Vout 1 ---- = --------- Vin 2pi F R C So at frequency F pick the integrator gain to be the inverse of the Kp Kvco gain: 1 2pi F R C = ----- Kp Kvco 2pi F or to define the RC for the loop filter integrator: 1 R C = ------------ Kp Kvco (2pi F) sqrd The overall transfer function is: loop_filter_gain Kp Kvco. The problem is that this loop will go through unity gain with a slope of 12 dB per octave and thus not be stable. This is caused by the pole from the loop filter integrator and the second pole from the VCO itself. The VCO is a phase integrator, 1/f gain response, the lower the control frequency swing the more phase it accumulates during the extreme of each swing. This is fixed up by adding a zero in the loop filter at a frequency of 5 or more lower than unity gain for the overall transfer function. This zero allows the overall transfer function to go through unity gain with a 6 dB slope and thus have a good phase margin. The zero in the loop filter holds up (holds constant) the gain of the loop filter as the over all transfer function, loop_filter Kp Kvco goes through unity. The zero is implement by adding a resistor in series with the "integrator capacitor" in the basic RC loop filter integrator. The the frequency response of the loop filter will fall off as 1/f until it reaches this zero at which point it will hold constant. ======================================================================== ADF System Section of the NIM Paper -------------------------------------- Original Rev. 22-NOV-2006 Current Rev. 28-NOV-2006 ADF System ---------- In the D-Zero Run IIB Level 1 Calorimeter Trigger the ADF System (Analog Digital Filter) is responsible for sending to the 8 TAB cards the best estimate of the Et energy in the EM and Hadronic sections of the 1280 Trigger Towers for each Tevatron beam crossing. The calculation of these Et values by the 80 ADF cards is based upon the 2560 analog trigger signals that the ADF cards receive from the Calorimeter front-end electronics and upon the timing and control signals that are distributed through out the D-Zero DAQ system by the Serial Command Links. The ADF system is setup and monitored by a Trigger Control Computer (TCC) that is described elsewhere in this article. Generation of Trigger Signals by the Calorimeter Front-End Electronics ---------------------------------------------------------------------- The D-Zero Calorimeter front-end electronics consists of preamplifiers, which are mounted up on the Calorimeter next to its signal feed through ports, and Base Line Subtracter cards (BLS cards) which are mounted down in the platform area under the Calorimeter (Reference for the Calorimeter Front-End Electronics here). On the BLS cards the preamplifier output signals are split into two analog paths. One path leads through switch capacitor analog storage arrays to the precision readout system for the Calorimeter and the other path leads to the generation of the projective Trigger Tower based trigger signals which are used by the L1 Calorimeter Trigger. Each Trigger Tower consists of an EM section and a Hadronic section. One Trigger Tower covers a 0.2 x 0.2 eta,phi section of the Calorimeter. Typically the signals from 28 EM Calorimeter cells and 12 Hadronic Calorimeter cells belong to the eta,phi area covered by one Trigger Tower. Each BLS card forms the EM and Hadronic trigger signals for one Trigger Tower. In response to an energy deposit, the preamplifier output signal for a given Calorimeter cell has a smooth step function like waveform with the amplitude of the step being proportional to the energy E deposited in that cell. Formation of a trigger signal begins by differentiation, with a 55 nsec time constant, of all the preamplifier output signals that contribute to a given trigger signal. All of these differentiated preamplifier output signals are then individually scaled, by passing through a resistor, before being summed to make the trigger signal. This scaling of the preamplifier signals that contribute to a given trigger signal is necessary, before they can be summed, for two basic reasons: - Different sections and depths of the Calorimeter have different sampling fractions and thus different preamplifier output step amplitudes for a given value of energy deposited in the Calorimeter. - The different Calorimeter cells that contribute to a given trigger signal have different cell capacitances and thus they have different preamplifier output signal rise-times. Because of the different rise-times the differentiated preamplifier output signals have different amplitudes for a given value of energy deposited in the Calorimeter. The trigger signal scaling on the BLS cards is also used to accomplish part of the Calorimeter energy E to Et conversion. The Level 1 Calorimeter Trigger calculations are based on the Et energy in each Trigger Tower whereas the un-scaled signals on the BLS cards and the precision readout of the Calorimeter are in terms of energy E. For the highest eta Trigger Towers the value of Et is only about 1/30 th of the value of E. For accurate processing of these signals, with analog circuits having a limited dynamic range, part of the scaling to Et must be done early in the summing circuits on the BLS cards. This is accomplished by assigning three ranges in eta with each range having its own calibration target for BLS card trigger signal output Volts per GeV deposited in the Calorimeter. Within each of these eta ranges the remainder of the scaling to Et is carried out on the ADF cards as described below. Because there are over 1000 BLS cards in the Calorimeter DAQ system, one of the guide lines for the design of the Run IIB Level 1 Calorimeter Trigger was to require no modification to the existing trigger signals generated by these cards. The system of long cables that bring the BLS card trigger signals from the detector platform on the Tevatron side of the shield wall out to the L1 Calorimeter trigger was modified only by the inclusion of a Cable Transition System which is described elsewhere in this article. ADF Card Processing of the Analog Trigger Signals into Digital Et Values ------------------------------------------------------------------------ Each ADF card receives 32 analog trigger signals (Reference here for ADF Card Block Diagram and picture). On a given ADF card these trigger signals represent the EM and Hadronic components of a 4x4 array of Trigger Towers. Each differential AC coupled analog trigger signal is received by a passive circuit that terminates and compensates for some of the characteristics of the long cable that brought the signal out of the collision hall. Following this passive circuit the active part of the analog receiver circuit rejects common mode noise on the differential trigger signal, provides filtering to select the frequency range of the signal caused by a real Tevatron energy deposit in the Calorimeter, and provides additional scaling and a level shift to match the subsequent ADC circuit. The analog level shift in the trigger signal receiver circuit is controlled, separately for each of the 32 channels on an ADF card, by a 12 bit pedestal control DAC. This DAC is used both to set the pedestal of the signal coming out of the ADC that follows the receiver circuit and this DAC is used as a "stand alone" way to test the full signal path on the ADF card (except for a few passive components in the trigger signal input circuit). With no input signal, which is the typical condition because the inputs are AC coupled, the pedestal control DAC can swing the output of the ADC from slightly below zero to mid scale. This is an adequate range to provide a reasonable test of the ADF card's signal path and still provides fine enough control to accurately set the pedestal at the ADC output to within a fraction of a count. During Physics operation we set the pedestal at the ADC output to 50 counts which is a little less than 5% of its full scale range. We can not set the BLS card trigger signal level that represents zero energy deposited in the Calorimeter to be zero ADC counts for two reasons. If we set the ADC output pedestal to zero then during Physics running we could not actually see the pedestal of the BLS card trigger signal and verify that it had not drifted negative. By using this unsigned offset binary system we can both avoid the unnecessary complexity of doing signed arithmetic and still correctly account for both positive and negative noise fluctuations throughout the trigger logic. The 10 bit sampling ADCs that follows the receiver circuit include a track-and-hold function and they complete a conversion in 5 pipeline steps. As controlled by a clock signal, which will be described later, ADC conversions are made every 33 nsec. This is 4 times faster than the potential Tevatron live beam crossing period of 132 nsec. Note that with the current Run IIB Tevatron beam structure, during the periods of beam crossings in each turn which are called "super bunches", there is a live crossing every 396 nsec. There are 159 potential beam crossings locations in a turn of the Tevatron of which 36 have live crossings in the current beam structure. The fundamental clock related to the Tevatron RF has 159 periods of 132 nsec each per turn of the Tevatron. The seemingly higher than necessary ADC conversion rate is used both the reduce the latency going through the pipeline ADCs and to provide the raw data necessary to associate the rather slow rise-time trigger signals (200 nsec typical rise-time) with the correct Tevatron beam crossing. Associating energy deposits in the Calorimeter with the correct beam crossing is not currently an issue with the live beam crossings spaced 396 nsec apart. Associating Calorimeter energy deposits with the beam crossing that caused them would be a major function of the ADF system if the Tevatron were to run with a 132 nsec live crossing beam structure. On each ADF card the 10 bit outputs from the 32 ADCs flow into a pair of FPGAs, called the data path FPGAs, where the bulk of the signal processing takes place (Reference the ADF Data Path FPGA block drawing here). This signal processing task is split over two FPGAs with each FPGA handling all of the steps in the signal processing for 16 channels. Two FPGAs were used because it simplified the circuit board layout and provided an economical way to obtain the required number of I/O pins. The first step in the signal processing is to align in time all of the 2560 trigger signals. The peak of the trigger signals from a given beam crossing arrive at the L1 Calorimeter Trigger at different times because of the different length cable runs from the Calorimeter front-end electronics and because the high capacitance sections of the Calorimeter respond more slowly. This initial signal processing step makes the digitized signals from all Trigger Towers isochronous and that simplifies the operation of the rest of the L1 Calorimeter Trigger. The Trigger Tower signals are lined up in time by delaying the early signals in shift registers. The 10 bit wide data for each channel passes through a variable length shift register that steps the data every 33 nsec. The length of the shift register for a given channel is controlled by the value that is written into a control-status register for that channel by the Trigger Control Computer. Once the trigger signals have been made isochronous they are sent to both the raw ADC data circular buffers where monitoring data is recorded and to the input of the digital filter stage. The raw ADC data circular buffers are typically setup to record all of the ADC samples (636 samples) in a full turn of the accelerator. Once the writing of monitor data into these circular buffers has been started by the Trigger Control Computer it can be stopped in one of three ways. The Trigger Control Computer can synchronously stop the writing of data into these circular buffers for all 2560 channels in the system or TCC can setup the system so that the writing of data into these circular buffers will synchronously stop for all channels the next time that an L1 Accept is issued that includes a flag indicating that monitoring data should be collected. During normal Physics operation L1 Accepts with the collect monitor data flag are issued about once every 5 seconds. Using the collect monitor data flagged L1 Accept to stop the writing of data into the raw ADC data circular buffers is the normal mode of operation. The advantage of this mode is that it helps to collect a turn's worth of raw ADC monitor data that includes some signals from real Tevatron energy deposits in the Calorimeter. The third mode for stopping the writing of data into these circular buffers is to allow each channel to operate and stop independently when its trigger signal has risen above some programmable minimum threshold. This third mode is used to collect data to study the timing and shape of the trigger signals from the BLS cards. The raw ADC monitor data from these circular buffers is readout by the Trigger Control Computer and sent to a monitoring system which is described elsewhere in this article. The address of the data in these circular buffers has a known alignment with the accelerator beam crossings. The raw ADC data circular buffers can also be loaded by the TCC with simulation data. For testing this raw ADC simulation data can then be played through the rest of the down stream signal processing stages. The digital filter in the signal processing path can be used to remove high frequency noise from the trigger signals and to remove low frequency shifts in the baseline. During the initial Physics operation of this new L1 Calorimeter Trigger the filter stage has been setup to select the ADC sample from the point in time where the peak of the trigger signal is located and then to passes that data through to the next stage. This mode of operation allowed the most direct comparison of the trigger signals in this new Calorimeter Trigger with the old system. The 10 bit output from the filter stage has the same scale and offset as the output from the ADCs. The filter output is used as the 10 bit address to a lookup memory. The 8 bit data words in this lookup memory are the Et values that are sent out from the ADF system to the TAB cards. Currently the lookup memories are programmed with "straight line" data. The slope of the straight line data in a given lookup memory is used to implement the final step in the conversion from energy E to Et for that channel. TCC programs the straight line data in all channels so that the point with address 50 contains Et data value 8. The Et data sent to the TAB cards is defined to have a uniform scale of 1 count equals 0.25 GeV of Et with a pedestal of 8 counts. Without this pedestal only positive noise fluctuation would be sent to the TAB cards. That would result in "rectifier effect", i.e. the summation of positive noise fluctuations when arrays of Trigger Towers are summed together in the various steps of the trigger algorithms. In each channel the Et data from the lookup memory is one of the 4 inputs to that channel's output multiplexer. The output multiplexer, on a clock cycle by clock cycle basis, selects which of its 4 inputs is sent out to the TAB cards. The 4 inputs to the output multiplexer are: the Et data from the lookup memory, a fixed value from a programmable register, simulation data from the output data circular buffer, and data from a pseudo random noise generator. The output multiplexer for each channel is separately controllable. This control comes from a combination of timing signals and control data that TCC writes into a control-status register for that channel's output multiplexer. The signal selected by the output multiplexer is sent out to the TAB cards and it goes to the input of that channel's output data circular buffer. The output data circular buffers are used to record monitoring data or to playback simulation data in a way that is very similar to the raw ADC data circular buffers which were described above. The monitoring data recorded by the output data circular buffers is a copy of the actual data that is sent to the TAB cards. The output data circular buffers are normally set to be 159 locations long and thus hold a full accelerator turn's worth of data. For normal Physics operation TCC sets up the output multiplexers so that they select their channel's lookup memory Et data for clock periods that have a real beam crossing and they select the contents of their channel's fixed data register for the other clock periods during a turn of the accelerator. The fixed data registers are loaded by TCC with the value 8. Thus the data that is sent out from the ADF system for the non live crossings in each turn is the value which represents zero energy deposited in the calorimeter. Note that the ADF system sends data to the TAB cards for all 159 clock periods during a turn of the accelerator. Occasionally during Physics operation the trigger signal from a BLS card may become too noisy to use in generating the Level 1 triggers. In that case the output multiplexer for that channel is set so that it selects the fixed data register for all 159 clock periods in a turn of the accelerator and thus excludes that channel from participating in the level 1 decision. During testing the output multiplexer, under TCC control, can select either simulation data, fixed data, or pseudo random noise data to send to the TAB cards. Simulation data can be used to send realistic patterns of energy deposits in the Calorimeter to the TAB cards for testing the trigger algorithms. Fixed data, with the fixed data register for each channel programmed by TCC with a unique known value, is used to verify the cabling of the ADF system outputs to the TAB inputs. Pseudo random noise data is used to test the bit error rate on the ADF to TAB links. Data is sent from the ADF system to the TAB cards using a National Semiconductor Channel Link chip set with LVDS signal levels between the transmitter and receiver (Reference here for National Semiconductor Channel Link). Each Channel Link output from an ADF card carries the Et data for all 32 channels (4x4 Trigger Towers) serviced by that card. A new frame of Et data is sent every 132 nsec. All 80 ADF cards begin sending their frame of Et data for a given Tevatron beam crossing at the same point in time. Each frame of Et data also includes: the ID number of the beam crossing in a turn of the Tevatron that produced the Et values reported in this frame, synchronizing information that the TAB cards use to identify which of the 8 Channel Link transfers that make up a full frame of Et data is the first transfer in the frame, and check sum information that the TAB cards use to verify that they have received data free of transport errors. Each ADF card sends out 3 identical copies of its data. This data replication is used to implement "crack-less" trigger algorithms in the TAB cards. Timing and Control Signals from the Serial Command Link ------------------------------------------------------- As mentioned above the ADF system receives its timing and control signals over one of the Serial Command Links (Reference for the SCL here). The Serial Command Link (SCL) system delivers timing and control information to all parts of the D-Zero DAQ system. The ADF system makes use of a number of signals from the SCL. The SCL signals used by the ADF system are: the fundamental 132 nsec clock which is locked to the Tevatron RF system, a marker signal which indicates the first crossing of each turn of the accelerator, a marker signal which flags the clock periods that contain a real beam crossing at D-Zero, and marker signals that indicate when a Level 1 Trigger Accept has been issued and indicate which Level 1 Accepts should be used to initiate the collection of monitoring information. Distribution of these signals from the SCL to the 80 ADF cards is facilitated by a card designed and built by the Saclay Laboratory called the SCL Distributor or SCLD card (Reference the SCLD card here). The SCLD card receives a copy of the SCL information using a standard SCL Receiver mezzanine card. This SCL Receiver mezzanine card is standard to all parts of the D-Zero DAQ system. The SCLD card fans out the signals mentioned above to the 4 VME-64x crates that hold the 80 ADF cards. These signals are transported from the SCLD card to the 4 ADF crates using LVDS level signals. In addition each ADF crate sends back to the SCLD card two LVDS level signals. The 80 ADF cards are held in slots 2 through 21 of 4 VME-64x crates (Reference for Wiener VME Crates here). The ADF card in slot 11 of each crate receives the signals from the SCLD card and directly places them onto spare reserved bused VME-64x backplane lines at TTL open collector signal levels. These backplane lines have normal VME type terminators at each end. All 20 of the ADF cards in a crate pickup their timing and control signals from these backplane lines. The only signal that receives special treatment is the fundamental 132 nsec clock signal. Direct and complement copies of this clock signal are sent across the backplane so that it may be received differentially on each ADF card. Once it is received on an ADF card this clock signal is used only as the reference for an on-board 8x PLL. To provide a high quality clock signal on the ADF card this PLL is built from a discrete voltage controlled crystal oscillator and feedback loop components. With a tracking range of 200 ppm and a loop response of 100 Hz this PLL is well matched to the Tevatron RF, which changes by only 20 ppm during an approximately 1 minute ramp from 150 GeV to 980 GeV, and it provides a much cleaner output signal than a wide bandwidth integrated PLL. The principal need for the high quality clock signal on the ADF card is to provide a clean reference clock for the Channel Link transmitters. It also provides jitter free timing of the ADC samples and thus helps ensure a large spurious free dynamic range from the ADCs. The ADF card in slot 11 of each of the 4 crates also sends back to the SCLD card 2 signals. Currently the ADF system makes use of these 2 signals from only one of the crates. These signals are used to allow the TCC to synchronously cause activity in all 80 ADF cards. One of these signals, when asserted by TCC, causes the writing of monitor data into the circular buffers to immediately and synchronously stop on all 80 ADF cards. The other signal, when asserted by TCC, enables the next L1 Accept, that has been mark to initiate the collection of monitor data, to cause writing to the circular buffers to synchronously stop on all 80 ADF cards. Programming of the ADF System ----------------------------- The ADF cards are controlled over a VME bus. Each ADF card uses a large PAL to implement a "slave only" VME interface. This PAL configures its logic into itself at power up. Once the VME interface is running then the TCC configures the logic into the 2 data path FPGAs on each card. Both data path FPGAs on a given ADF card can be configured at the same time. Although the logic in the two data path FPGAs is not exactly the same (e.g. the output check sum generation logic must differ) a standard technique is used that implements, in each FPGA, the super set of the required logic and provides a single ID pin via which a given FPGA can lean which one it is and thus function appropriately. In this way the same module of data path FPGA logic runs in both FPGA locations on an ADF card. All 80 ADF cards currently use the same data path FPGA logic. The data path FPGAs only need to be configured with their logic once after the power has been turned on. After TCC has configured the logic into the data path FPGAs on all 80 ADF cards then all of the control-status registers and memory blocks exist that TCC must program to operate the ADF system. Information that is held on the ADF cards that is critical to their Physics triggering operation is protected by making those programmable features "read only" during normal operation. TCC must explicitly unlock the write access to these features to change their control values. In this way no single failed or miss-addressed VME cycle can overwrite this critical data. Absolutely all data that TCC can write to the ADF cards can be, and routinely is, read back by TCC to verify the correct setup of ADF system. References: ----------- Calorimeter front-end electronics http://www-d0.fnal.gov/hardware/cal/calorimeter_electronics.htm ADF card block diagram http://www.pa.msu.edu/hep/d0/ftp/run2b/l1cal/hardware/adf_2/drawings/ adf_2_card_block_diagram.pdf or .ps ADF card picture http://www.pa.msu.edu/hep/d0/ftp/run2b/l1cal/hardware/adf_2/pictures/ adf2_front.jpg ADF Data Path FPGA block drawing http://www.pa.msu.edu/hep/d0/ftp/run2b/l1cal/hardware/adf_2/drawings/ data_path_fpga_signal_processing.pdf or .ps for National Semiconductor Channel Link http://www.national.com/appinfo/lvds/files/channellink_design_guide.pdf Serial Command Link http://www.pa.msu.edu/hep/d0/l1/scl.html SCLD card http://www.pa.msu.edu/hep/d0/ftp/run2b/l1cal/hardware/scld/ Wiener Series 6000 VME-64x Crate http://www.wiener-us.com/ Drawings and Pictures which could be included in this NIM paper: ---------------------------------------------------------------- ADF card picture ADF card block drawing ADF card Data Path FPGA block drawing