Design Layout for the ADF-2 Circuit Board ------------------------=====---------------- Original Rev. 21-FEB-2004 Most Recent Rev. 11-APR-2005 This file includes all of the material that describes how the ADF-2 card will be designed. This material covers both the electrical design of the ADF-2 card and the printed circuit board layout. A partial list of changes between the ADF prototype card and the ADF-2 card are covered in the file: www.pa.msu.edu/hep/d0/ftp/run2b/l1cal/hardware/adf_prototype/general/ adf_proto_to_v2_changes.txt Net List Generation ------------------- The net list for the ADF-2 circuit board will be maintained in a number of smaller files. About 50 files will be used. Each file is small enough for a normal human to maintain "intellectual control" over it. A strong effort will be made to use uniform rational un-ambiguous net names throughout the design. The net names will be consistent between these net list files and the documentation files. To help maintain order in this aspect of the design we will use the following rules: Multiple net names will not be assigned to the same signal. All net names that represent signals that are asserted in the Low Voltage state will end in "_B". (not * or % or \") The net names of the I/O signals to FPGA F0 will be used in the design of the Data Path FPGA. The net names of the I/O signals to the Board Control PAL will be used in the design of that PAL. The Trigger Tower signals and all references to the data path channels in the ADF-2 design will be named "Channel 0:15 EM:HD". That is the channels are not named 0:31. Net List generation for the ADF-2 circuit board will be done by a combination of "key in net lists" and software generated net lists. The software generated net lists will be used in 2 places where multiple instances of the same circuit are needed. These places are: the 16 instances of the Analog-ADC circuit the 2 instances of the main FPGA circuit The software to generate these net lists will use a "template file" as input and then generate a separate output file for each instance of that circuit. Multiple passes can be made as the template file is developed. The net lists for the 2 main FPGAs will include in each NET statement a comment with the physical pin number. Direct generation and comparison with the FPGA UCF file will be possible. Signal Polarity --------------- Unless there is a good reason to do otherwise, all signals will be "positive polarity", i.e. when asserted they are at the Higher Voltage level. As noted above any signal that is asserted when it is at its Lower Voltage level will have a net name that ends in "_B". All of the open collector VME-64X Reserved Bus Lines are active in their Lower Voltage state (as is the norm for open collector buses). Making these signals Low Voltage active is achieved by using inverting open collector drivers or in the case of the 5 SCLD Control signals they are received from the SCLD by inverting receivers and then driven onto the open collector bus with non-inverting drivers. In all cases the signals from the VME-64X open collector Reserved Bus Lines are received from the bus by inverting receivers and thus are back to being "positive polarity" before they appear in any logic or registers. Reference Designators --------------------- In the ADF-2 design the reference designators will be assigned in a rational understandable order. Reference designators will be organized into groups around a given section of the overall ADF-2 design. Standard fixed increments will be used in moving from one instance of a given circuit to the next. The following table is the guide to reference designator assignments. ADF-2 Design Section Reference Designator Usage ------------ ----------------------------------------------- Backplane The backplane connectors have reference designators P1, P2, and P3. P3 is the "P0" center connector. P1, P2 Harting part no. 02-01-160-2101 P3 Harting part no. 1725-095-2102 Analog-ADC The first instance of the Analog-ADC section starts with: C1, R1, U1. The increment from one instance to the next it 50. U1 is the EM Diff Amp, U2 is the HD Diff Amp, U3 is the ADC. The EM C's and R's are 1:19 The HD C's and R's are 21:39. The ADC and common C's and R's are 41:49. R1, R2 1 Meg R3, R4 84.5 R5, R6 1.5 k R7, R8 499 R9, R10 150 R11, R12 1.82 k R41 2.15 k R42 1 k C1, C2 470 nFd C3, C4 18 pFd C5, C7 27 pFd C6 15 pFd C8:C11 0.1 uFd C41:C46 0.1 uFd N1 EXB-24V-101-JX 100 Ohm 2 resistor array N2, N3 EXB-28V-101-JX 100 Ohm 4 resistor array U1, U2 THS4141 U3 AD9218 Main FPGA The FPGA reference designators start at 801 and increment by 100. "F0" is U801 "F1" is U901 R801, R901 INIT_B pull up resistors on FPGAs F0, F1 0603 4.99 k Ohm R802, R902 DONE pull up resistors FPGAs F0, F1 0603 4.99 k Ohm R803, R903 is M0 mode resistor 0603 150 Ohm R804, R904 is M1 mode resistor 0603 150 Ohm R805, R905 is M2 mode resistor 0603 150 Ohm R806, R906 is HSWAP_EN pull up 0603 4.99 k Ohm R907 is FPGA F1 ID Pin pull up 0603 4.99 k Ohm W801 JTAG Data from BC PAL to F0 zero Ohm 0603 jumper W802 JTAG Data from F0 to F1 zero Ohm 0603 jumper W803 JTAG Data from F1 to off card zero Ohm 0603 jumper FPGA Bypass Capacitors: VDD_LOGIC 10 uFd Tantalum case B 2x C802,C803 0.47 uFd Ceramic smd 0805 5x C804:C808 0.047 uFd Ceramic smd 0603 8x C809:C816 0.0047 uFd Ceramic smd 0603 16x C817:C832 VCCINT 10 uFd Tantalum case B 2x C833,C834 0.47 uFd Ceramic smd 0805 3x C835:C837 0.047 uFd Ceramic smd 0603 4x C838:C841 0.0047 uFd Ceramic smd 0603 8x C842:C849 Bus I/O U1001, U1002 74LVC16374A 16 bit "D" Latch for VME Receiving "adrs" type information and Driving 31 of 32 sections used. 3.3V <-> 5V U1011 74LVT16245B 16 bit Transceiver for VME Data lines 16/16 used. U1021 SN74AS760 Non-Inverting O.C. Driver for SCLD Control signals and one side of BX_Clk. 6 of 8 sections are used. U1031 SN74AS756 Inverting O.C. Driver for Crate Status lines, and VME DTACK*, and for one side of BX_Clk, and for Power Up Supervisor RESIN* 7 of 8 sections are used. U1041 SN74LVC540A Octal Inverting OC Buffer for Receiving SCLD Control signals and Receiving VME DS1_B 6/8 section used. U1051, U1052 SN65LVDS32 Receive 4 LVDS signals each. Receive SCLD Control and Clock and Backplane Clock 7/8 Receivers used. U1071 SN65LVDS31 Drive 4 LVDS signals each. Drive Status to SCLD. 2 of 4 drivers are used. R1001:R1005 4.99 k Ohm 0603 1% Pull up on VME Geo Adrs W1006 Zero Ohm 0603 jumper input to unused section of U1002 a 74LVC16374A latch N1011:N1014 EXB-28V-101-JX 10k Ohm 4 resistor array Pull up resistors for the On Card Bus data bus W1021:W1027 Zero Ohm 0603 jumpers if installed drive backplane W1028, W1029 Zero Ohm 0603 jumpers control input to 2 unused sections of U1021 W1031 Zero Ohm 0603 jumpers control input to the unused section of U1031 W1041, W1042 Zero Ohm 0603 jumpers control input to 2 unused sections of U1041 R1051:R1057 100 Ohm 0603 resistor 1% Terminate LVDS from SCLD R1061, R1062 1k Ohm 0603 1% isolator R1063, R1064 499 Ohm 0603 1% divider between open collector backplane and LVDS receiver input R1065 100 Ohm 0603 1% resistor series term Rcvd_BX_Clk C1061 0.1 uFd ceramic C1062 4.7 nfd ceramic hold backplane BX_Clk common mode at ground W1071, W1072 Zero Ohm 0603 jumpers input to unused LVDS Drv R1073, R1074 100 Ohm 0603 resistor 1% Terminate unused LVDS Drv C1001, C1002, C1003, C1004, 0.1 uFd bypass capacitors C1011, C1012, all to Vdd_Logic C1041, C1051, C1052, C1071, C1005, C1006, C1007, C1008 4.7 nFd bypass capacitors C1013, C1014 all to Vdd_Logic C1042, C1053, C1054, C1072, C1021, C1031 0.1 uFd bypass capacitors C1022, C1032 4.7 nFd bypass capacitors all 4 to Vcc_Logic Board U1101 Xilinx XC95144XL Xilinx Complex PAL Control C1101 : C1105 0.1 uFd ceramic Vdd_logic bypass PAL C1106 : C1110 4.7 nFd ceramicm Vdd_logic bypass C1111 : C1112 10 uFd tantalum Vdd_logic bypass Channel_Link U1201, U1202, U1203 DS90CR483 Channel Link Transmitter ADF -> TAB links 0, 1, 2 C1201 : C1230 0.1 uFd ceramic Vdd_Logic bypass C1241 : C1246 10 uFd tantalum Vdd_Logic bypass C1251 : C1262 4.7 nFd ceramic Vdd_Logic bypass R1201, R1202, R1203 100 Ohm resistors to terminate the unused serial data output TxOUT7. R1204, R1205, R1206 Pre-Emphasis Select Resistor 1 Meg. Power Entry F1301:F1304 Fuse: Littelfuse 3 Amp Slow Blow D1301:D1304 Transient Voltage Suppressor OnSemi 1SMA5.0AT3 C1301:C1304 470 uFd 16 Volt Aluminum Electrolytic DC/DC U1321 Datel LSM-1.5/10-D5 Converters U1331 Datel LSM-3.3/10-D5 C1321, C1322, C1323 150 uFd 10 Volt Tantalum C1331, C1332, C1333 150 uFd 10 Volt Tantalum R1321, R1331 150 Ohm 0603 resistor 1% Converter Enable Isolation Power-Up U1351 TI TLC 7705 IPWR supervisor IC Supervisor C1351 0.1 uFd ceramic Vcc_logic bypass C1352, C1353 10 uFd Tant Cap_Time, Sense Filter R1351 20k Ohm 0603 R1352 2.15 k Ohm 0603 LED Displays LED1371 Dialight 592-2222 Green Power Supply Vcc Vdd LED1372 Dialight 592-2121 Red Board Control PAL 0,1 LED1381 Dialight 592-2121 Red F0 FPGA 0,1 LED1382 Dialight 592-2121 Red F0 FPGA 2,3 LED1391 Dialight 592-2121 Red F1 FPGA 0,1 LED1392 Dialight 592-2121 Red F1 FPGA 2,3 R1371, R1372 200 Ohm 0603 1% Vcc resistors R1373 150 Ohm 0603 1% Vdd resistor R1374, R1375 200 Ohm 0603 1% BC PAL resistors R1381:R1384 200 Ohm 0603 1% F0 resistors R1391:R1394 200 Ohm 0603 1% F1 resistors R1376 1k Ohm 0603 1% Front Panel Ground PLL 8x U1401 MAX 4476 Op-Amp for loop filter BX_Clk U1402 Vectron VCUGCD VCXO 60.6905 MHz +- 50 ppm Pull Range U1403 ICS552G-02I Receive 1 CMOS signal make 8 low skew copies used for 8x Clk fanout 6 of 8 outputs are used C1401, C1402 4.7 nFd ceramic cap 0603 loop filter C1403 15 pFd ceramic cap 0603 loop filter C1404, C1405 0.47 uFd ceramic cap 0805 loop filter C1406 4.7 nFd ceramic cap 0603 loop filter R1401, R1402 1k Ohm resistor 1% 0603 loop filter R1403, R1404 20k Ohm resistor 1% 0603 loop filter R1405 4.99k Ohm resistor 1% 0603 loop filter R1406 150 Ohm resistor 1% 0603 loop filter R1407 1k Ohm resistor 1% 0603 isolate mon W1401 Zero Ohm 0603 jumper Board Control PAL CNT_BIT_VAL_4 to PAL_BX_CLOCK C1411, C1412 0.1 uFd bypass capacitors all to Vcc_Analog C1413, C1414, 4.7 nFd bypass capacitors all to Vcc_Analog C1415, C1416 10 uFd bypass capacitor to Vcc_Analog C1421, C1422 0.1 uFd bypass capacitors all to Vdd_Logic C1423, C1424, 4.7 nFd bypass capacitors all to Vdd_Logic I1410 100 uH Power Inductor Delevan 4922-25L N1401, EXB-28V-101-JX 100 Ohm 4 resistor array N1402 BX_X8_CLOCK Series Terminator N1403 EXB-24V-101-JX 100 Ohm 2 resistor array FIRST_X8_EDGE Series Terminator Pedestal U1451 : U1454 DAC 12 Bit 8 Channels LTC2620CGN DAC's U1455 Voltage Reference 4.096 Volt MAX 6141 C1451 : C1455 0.1 uFd ceramic VCC_ANALOG bypass C1461 4.7 nFd ceramic DAC_REF bypass N1451 : N1458 Resistor Network 4x 100 Ohm R1451 1k Ohm resistor 1% 0603 DAC CLR_B pullup R1452 100 Ohm 1% 0603 resistor DAC Data Clk Term R1453 2.15 k Ohm 1% 0603 DAC Ref Pull Up Auxiliary C1501:C1516 10 uFd 16 Volt Tantalum VCC_ANALOG Bypass Caps C1521:C1536 10 uFd 16 Volt Tantalum VEE_ANALOG C1541:C1556 10 uFd 16 Volt Tantalum VDD_ANALOG C1561:C1564 0.1 uFd Ceramic 0603 VCC_LOGIC C1565:C1566 0.1 uFd Ceramic 0603 VDD_LOGIC C1567:C1568 0.1 uFd Ceramic 0603 VCCINT C1571:C1574 0.047 uFd Ceramic 0603 VCC_LOGIC C1575:C1576 0.047 uFd Ceramic 0603 VDD_LOGIC C1577:C1578 0.047 uFd Ceramic 0603 VCCINT C1581:C1584 0.0047 uFd Ceramic 0603 VCC_LOGIC C1585:C1586 0.0047 uFd Ceramic 0603 VDD_LOGIC C1587:C1588 0.0047 uFd Ceramic 0603 VCCINT C1601 0.1 uFd VCCINT S.E of U801 Bot C1611 0.1 uFd VDD_LOGIC N.W. of BC PAL Bot C1612 0.1 uFd VDD_LOGIC W. of Pow Super Bot C1613 0.1 uFd VDD_LOGIC Under U1203 Bot C1621 4.7 nFd VDD_LOGIC N.W. of BC PAL Top C1622 4.7 nFd VDD_LOGIC N.E. of BC PAL Top C1623 4.7 nFd VDD_LOGIC W. of Pow Super Top C1624 4.7 nFd VDD_LOGIC W. of Pow Super Top C1625 4.7 nFd VDD_LOGIC Above Chan Link Top C1626 4.7 nFd VDD_LOGIC Above Chan Link Top C1627 4.7 nFd VDD_LOGIC Under U1203 Bot Standard Circuit Board Orientation ---------------------------------- All references to the ADF-2 circuit board will assume that it is in a standard viewing position: component side up, front panel to the left, and backplane connectors to the right. This orientation will be used in all the Mentor Graphics files. |____________________ | |- | | | | | | | | | P1 Front | |_| Panel | | | | 6 U | |- 233.35 mm | | | | |_| P0 | | | | | |- | | | | | | | | | P2 | |_| |____________________| | 160 mm VME P2 Connector BLS Signal Pinout ---------------------------------- The Analog-ADC section will be layed out in a unit cell array. Which channel, what relative eta,phi it is, and what inputs of what FPGA it must be connected to is all fixed and understood. This layout is shown in the following drawing and table. The BLS connections to P2 will be arranged to eliminate any cross over of the analog input traces. ADF-2 Relative |____________________ Ch (15:0) eta,phi | |- ------------- ----------- | | | 0 EM,HD 0,0 EM,HD | | | 1 0,1 | | | P1 2 0,2 Front | FPGA |_| 3 0,3 Panel | _________ | | / \ | 4 1,0 | F1 F0 |- 5 1,1 | | | 6 1,2 | |_| P0 7 1,3 |Ch12 Ch08 Ch04 Ch00 | | | 8 2,0 |Ch13 Ch09 Ch05 Ch01 |- 9 2,1 | | | 10 2,2 |Ch14 Ch10 Ch06 Ch02 | | 11 2,3 | | | P2 |Ch15 Ch11 Ch07 Ch03 |_| 12 3,0 |____________________| 13 3,1 | 14 3,2 15 3,3 P2 Connector Pinout ------------------------------------------------------------ Row Column "C" Column "A" Column "Z" --- --------------- --------------- ----------- 1 Ch_00_EM_P Ch_00_HD_P 2 Ch_00_EM_N Ch_00_HD_N VME_64X_GND 3 Ch_04_EM_P Ch_04_HD_P 4 Ch_04_EM_N Ch_04_HD_N VME_64X_GND 5 Ch_08_EM_P Ch_08_HD_P 6 Ch_08_EM_N Ch_08_HD_N VME_64X_GND 7 Ch_12_EM_P Ch_12_HD_P 8 Ch_12_EM_N Ch_12_HD_N VME_64X_GND 9 Ch_01_EM_P Ch_01_HD_P 10 Ch_01_EM_N Ch_01_HD_N VME_64X_GND 11 Ch_05_EM_P Ch_05_HD_P 12 Ch_05_EM_N Ch_05_HD_N VME_64X_GND 13 Ch_09_EM_P Ch_09_HD_P 14 Ch_09_EM_N Ch_09_HD_N VME_64X_GND 15 Ch_13_EM_P Ch_13_HD_P 16 Ch_13_EM_N Ch_13_HD_N VME_64X_GND 17 Ch_02_EM_P Ch_02_HD_P 18 Ch_02_EM_N Ch_02_HD_N VME_64X_GND 19 Ch_06_EM_P Ch_06_HD_P 20 Ch_06_EM_N Ch_06_HD_N VME_64X_GND 21 Ch_10_EM_P Ch_10_HD_P 22 Ch_10_EM_N Ch_10_HD_N VME_64X_GND 23 Ch_14_EM_P Ch_14_HD_P 24 Ch_14_EM_N Ch_14_HD_N VME_64X_GND 25 Ch_03_EM_P Ch_03_HD_P 26 Ch_03_EM_N Ch_03_HD_N VME_64X_GND 27 Ch_07_EM_P Ch_07_HD_P 28 Ch_07_EM_N Ch_07_HD_N VME_64X_GND 29 Ch_11_EM_P Ch_11_HD_P 30 Ch_11_EM_N Ch_11_HD_N VME_64X_GND 31 Ch_15_EM_P Ch_15_HD_P 32 Ch_15_EM_N Ch_15_HD_N VME_64X_GND Notes: VME-64X labels the pins on the P2 connector in the following way: +-------------------------+ | | | D1 C1 B1 A1 Z1 | | D2 C2 B2 A2 Z2 | | D3 C3 B3 A3 Z3 | . . . . . . . . . . . . . . . . . . . . . | D30 C30 B30 A30 Z30 | | D31 C31 B31 A31 Z31 | | D32 C32 B32 A32 Z32 | | | +-------------------------+ View looking from the back of the backplane The BLS Cable Grounds are connected to the even number "Z" column pins. These pins are connected to the VME-64 backplane ground. The ADF-2 card ground plane is also connected to the even number "Z" column pins. The ADF-2 card makes no connection to the odd number pins in the "Z" column. The only connection that the ADF-2 card makes to the "D" column is a ground plane connection to pin D31. D31 is an extended "make first" pin. D31 is tied to the backplane ground. The only connections that the ADF-2 card makes to the "B" column are the following: B1, B13, B32 are net VME_5V B2, B12, B22, B31 are tied to the ground plane Recall that the VME-64 current limit per pin is 1.2 Amps at 60 degrees C. FPGA Routing and Escape Strategy ------------------------------ Escape strategy for the FG456 package is covered in the, "Virtex II Platform FPGA User Guide" starting at about page 388. As viewed from the top where are the I/O Banks. "pin #1" --> +---------+ |\ 0 | 1 /| | \ | / | |7 \ | / 2| | \|/ | +----+----| | /|\ | |6 / | \ 3| | / | \ | |/ 5 | 4 \| +---------+ What are the special functions in each I/O bank of the XC2V1000 FG456: Bank 0 has 38 I/O's of which 4 are Global Clock Inputs Bank 1 has 38 I/O's of which 4 are Global Clock Inputs Bank 2 has 42 generic I/O's Bank 3 has 42 generic I/O's Bank 4 has 34 I/O's of which 4 are Global Clock Inputs plus I/O's that 2nd as: D0/DIn, D1, D2, D3, Busy/DOut, Init_B Bank 5 has 34 I/O's of which 4 are Global Clock Inputs plus I/O's that 2nd as: D4, D5, D6, D7, RDWR_B, CS_B Bank 6 has 42 generic I/O's Bank 7 has 42 generic I/O's In ADF-2 the FPGA is placed so that pin #1 is in the lower right hand corner, i.e. pin #1 is in the South East corner. Note that the ideal layout might be to put the FPGA at 45 degrees with pin #1 straight down. The general use of banks will then be: Banks 7,0,1,2 will be used to bring into the FPGA the ADC's outputs. All 160 user I/O pins in Banks 7,0,1,2 will be used for this. This uses access to 8 Global Clock Inputs. Bank 6 will be used for the Channel Link connections. Banks 4 & 5 will be used for the Global Clocks (8 inputs are available) and it will be used for the On Card Bus (8 of the 16 data lines in this bus must land in these banks anyway) and it will be used for the SCLD control and FPGA Status signals. Bank 3 is the ADC clocks, deBug connector and LED's. Banks 7,0,1,2 will have zero outputs --> zero SSO. Bank 6 will up to 24 SSO outputs running all of the time at 61 MHz. Banks 4, 5 together will have up to 20 SSO outputs running at slow speed. Bank 3 will have 8 SSO outputs running all of the time at 30 MHz plus a few other slow speed outputs. As shown, Bank 6 has all 24 outputs to the Channel Link. These have 3 loads on each line. It may be best to split these outputs across Banks 5 and 6. As shown all 8 ADC Clocks come from bank 3. These are the only traces that cross the equator. The FPGA connections with the ADC's will be setup so that there is no crisscross of traces. This can be done in a total of 7 routing layers. As the traces enter the FPGA pin array they will be arranged on layers so that as soon as possible a full layer will drop off. This can happen by the 2nd row of pins on the FPGA. Use of Physical and Logical Circuit Board Layers ------------------------------------------------ In general the ADF-2 card will have: 8 Physical trace layers and 4 power/ground planes Physical layers. The Power Planes will be divided into various sections. A 5th plane Physical Layer will be needed under the Analog-ADC Section. Physical stackup: Phys Layer Type Function ----- ------------------------------------------------------------ 1 Trace #1 2 Ground Plane #1 This the the GROUND net plane. It picks up all ground connections and all of the P1, P2, P3 ground pins. This plane is slit between and Channel Link and Analog Sections. 3 Power Plane #1 This physical plane is used for the +5 Volt supply net, VCC_LOGIC, in the area above the FPGA section of the board (but not right along the front edge of the board above the FPGAs or in the area of the backplane connectors P1, P2, P3. This net only supplies the two DC/DC Converters and the open collector drivers U1021 and U1031. Does this need to be a plane ? In the P1, P2 connector area this is the VME +5V power entry net VME_5V which becomes the VCC_LOGIC supply net after power entry. At and above the FPGA section along the front edge of the card and under the FPGA section this Physical Plane is the VCCINT supply net, i.e. the FPGA Core supply. The VCCINT supply comes from the DC/DC Converter next to the front panel. Under the Analog Section this Physical Plane is the analog +5 Volt analog supply net which is net name VCC_ANALOG. Under the Channel Link section and under the Dean Caps this Physical Plane could be used as a shield. 4 Trace #2 5 Trace #3 6 Trace #4 7 Trace #5 8 Trace #6 9 Trace #7 10 Power Plane #2 This physical plane is used for VDD_LOGIC in the area of the Channel Link chips, the FPGAs and above. This plane does not cover the area under the backplane connectors. The VDD_LOGIC supply comes from a DC/DC Converter. Under the backplane connectors this Physical Plane is the power entry net VME_3V3 which becomes the +3.3 Volt analog Under the Analog Section this physical plane is the VDD_Analog net. 11 Ground Plane #2 dido of Physical Layer #2. 12 Trace #8 Differential analog traces from P2 to the differential amp inputs. List of all nets that are carried using planes: Net Name Function ----------- ------------------------------------------------------ - VCC_LOGIC +5 V supply for VME logic and powers the DC/DC Conv's - VDD_LOGIC +3.3 V logic supply made on card by DC/DC Conv - VCCINT +1.5 V FPGA Core supply made on card by DC/DC Conv - VCC_ANALOG +5 V analog supply comes from backplane +12 V bus - VDD_ANALOG +3.3 V analog supply comes from backplane +3.3 V bus VEE_ANALOG -5 V analog supply comes from backplane -12 V bus VME_P12V Power Entry that becomes VCC_ANALOG - VME_5V Power Entry that becomes VCC_LOGIC - VME_3V3 Power Entry that becomes VDD_ANALOG VME_N12V Power Entry that becomes VEE_ANALOG Vagrants: Power Entry planes for: VME_P12V VME_12N (may be traces) Power Supply planes for: VEE_ANALOG (Area Fill Sig_2) Power Planes that can share the same Physical Layer: VME_5V VCC_LOGIC VCCINT VCC_ANALOG (Shield under Channel Link & Dean Caps) VME_3V3 VDD_ANALOG VDD_LOGIC (Shield under the Southern part of Dean Caps) Observations: Under the Analog-ADC Section a 5th Plane Layer will be needed to carry a 3rd Power Plane, i.e. VEE_ANALOG. Under the backplane connector area we need: - VME_5V going North - VME_3V3 going South VME_P12V going South VME_N12V going South Shielded Channel Link outputs going East Shielded SCLD connections going North West Shielded BLS Inputs going West VME and Reserved VME-64 lines going East and West - Normal 2 Ground Planes The VCC_LOGIC plane only services the two DC/DC Converters and the two open collector driver chips. It could have a cut out section for the PLL clock circuit. ADC Output to FPGA Input Traces Mostly Lands ADC Num at FPGA on Pins Routed on Layer -------- ---------------------- ------------------ Ch 0 EM Row B Columns 4:11 Top Trace Layer Ch 0 HD Row C Columns 4:11 Ch 1 EM Row E Columns 6:11 Rows H:L Column 5 Ch 1 HD Row F Columns 9:11 Rows E:G Column 5 Rows J:L Column 6 Ch 2 EM Row D Columns 6:11 Ch 2 HD Rows E:L Column 4 Ch 3 EM Rows C:L Column 2 Ch 3 HD Rows E:L Column 3 Ch 4 EM Row B Columns 12:19 Top Trace Layer Ch 4 HD Row C Columns 12:18 Ch 5 EM Row E Columns 12:17 Rows H:L Column 18 Ch 5 HD Row F Columns 12:14 Rows E:G Column 18 Rows J:L Column 17 Ch 6 EM Row D Columns 12:18 Ch 6 HD Rows F:L Column 19 Ch 7 EM Rows C:L Column 21 Ch 7 HD Rows E:L Column 20 Power from the VME Bus ---------------------- The ADF-2 card brings in 4 supply voltages from the VME backplane. These 4 supplies are: VME_P12V This is the VME power distribution bus that normally carries +12 Volts. This supply enters the ADF-2 card on pin P1-C31. In the ADF-2 crates this bus will carry the Analog +5 Volt supply. This supply is used by the analog front-end differential amplifiers. After the power entry section the Analog +5 Volt net is named VCC_ANALOG. VME_5V This is the VME power distribution bus that carries +5 Volts. This supply enters the ADF-2 card on pins: P1-A32 P1-B32 P1-C32 P2-B1 P2-B13 P2-B32 After passing through the power entry fuse and filter, the +5 Volt Logic supply has net name VCC_LOGIC. On the ADF-2 this supply is used to power the following: Provide power for two VME backplane buffer driver IC's U1021 and U1031. Provide power to the Power Up Supervisor U1351. Proide input power to the DC/DC Converter that makes the +1.5 Volt FPGA Core Logic supply. On the ADF-2 this +1.5 Volt Core supply has net name VCCINT. Proide input power to the DC/DC Converter that makes the +3.3 Volt Logic supply. This +3.3 Logic supply is used by the FPGA I/O Blocks, and for the FPGA Auxiliary power, and by the other 3.3 Volt logic on the ADF-2 card. On the ADF-2 card the +3.3 Logic supply net is named VDD_LOGIC. VME_3V3 This is the VME-64x power distribution bus that carries +3.3 Volts. This supply enters the ADF-2 card on pins: P1- D12 D14 D16 D18 D20 D22 D24 D26 D28 D30 On the ADF-2 card this supply is used by the high speed ADC's. This supply is only used in the analog front-end section of the ADF-2. After the power entry section the Analog +3.3 Volt net is named VDD_ANALOG. VME_N12V This is the VME power distribution bus that normally carries -12 Volts. This supply enters the ADF-2 card on pin P1-A31. In the ADF-2 crates this bus will carry the Analog -5 Volt supply. This supply is used by the analog front-end differential amplifiers. After the power entry section the Analog -5 Volt net is named VEE_ANALOG. DC/DC Converters ---------------- During power up the Xilinx XC2V1000 have some rather specific current requirements. In addition to the FPGA power requirements the other Vdd 3.3 Volt logic, including the Complex PAL, will be loading that DC/DC converter. Known current requirements: Board Control PAL 125 ma of 3.3 Volt VDD_LOGIC National Semi Channel Link 3x at 160 ma each = 480 ma of 3.3 Volt VDD_LOGIC For each XC2V1000 FPGA Quiescent At Power Up -------------- ----------- Typ Max Minimum --------------- -------- VCCINT 100 ma / 250 ma 250 ma VCCO 1 ma / 2 ma 50 ma VCCAUX 10 ma / 25 ma 100 ma So to set the scale, per ADF-2 card, we need: at least 500 ma of 1.5 Volt to start up and run nothing at least 905 ma of 3.3 Volt to start up From module 3 page 3 of the Xilinx documentation: VCCINT, VCCAUX, and VCCO power supplies shall each ramp on no faster than 200 usec and no slower than 50 msec. Ramp on is defined as 0 Volt to minimum operating voltage for each supply. The middle of this range is 3.16 msec. From page #3 and page # of the Wiener documentation: Turning on the power supply all voltages reach the nominal values nearly simultaneously within 50 +- 2.5 msec where the voltage vs time curve shows a monotonic behavior. Voltage rise characteristic: monotonic 50 msec processor controlled In the ADF-2 a power up supervisor will be used to control the sequence of cards starting up their DC/DC Converters instead of basing this on the Geographic Address pins. The startup signal will be passed from one slot to the next on the Bus_Grant_1 VME backplane circuit. This is described in detail in: www.pa.msu.edu/hep/d0/ftp/run2b/l1cal/hardware/adf_2/drawings/ adf_2_power_up_supervisor.pdf & .ps The details of the ADF-2 Power Entry and DC/DC Converters are shown in: www.pa.msu.edu/hep/d0/ftp/run2b/l1cal/hardware/adf_2/drawings/ power_entry_and_dc_dc_converters.pdf & .ps Analog Power Supply Requirements: --------------------------------- +3.3V This is used to run the ADC's. On the ADF-2 this supply Voltage is net name VDD_ANALOG. AD9218 ADC 120 ma each x 32 = 3.84 Amps per ADF-2 card + -------- total 3.84 Amps of 3V3 per card total 76.8 Amps of 3V3 per crate +5V This is used to run the THS4141 Differential Amplifier and the Pedestal DAC's. On the ADF-2 this net is named VCC_ANALOG. THS4141 Dif Amp 15 ma each x 32 = 0.480 Amps per ADF-2 card Amp load current 2 ma each x 64 = 0.128 Amps per ADF-2 card MAX5307 DAC 2 ma each x 4 = 0.008 Amps per ADF-2 card + -------- total 0.616 Amps of +5V per card total 12.32 Amps of +5V per crate -5V This is used to run the THS4141 Differential Amplifier. On the ADF-2 this net is named VEE_ANALOG. THS4141 Dif Amp 15 ma each x 32 = 0.480 Amps per ADF-2 card + -------- total 0.480 Amps of -5V per card total 9.6 Amps of -5V per crate Digital Supply Power Requirements --------------------------------- Digital Supply Sketch: 74AS760 40 mA of VCC_DIGITAL 74AS757 40 mA of VCC_DIGITAL 65LVDS31 30 mA of VDD_DIGITAL 65LVDS32 40 mA of VDD_DIGITAL ICS552-02 50 mA od VDD_DIGITAL Board Control PAL 125 ma of 3.3 Volt VDD_LOGIC National Semi Channel Link 3x at 160 ma each = 480 ma of 3.3 Volt VDD_LOGIC For both XC2V1000 FPGA at least 500 ma of 1.5 Volt to start up and run nothing at least 905 ma of 3.3 Volt to start up Digital per card: 100 mA directly on VCC_DIGITAL 2.5 Amps of VDD_DIGITAL --> 2.4 Amps of VCC_DIGITAL 2.0 Amps of VINT --> 0.9 Amps of VCC_DIGITAL Total of 3.4 Amps of VCC_DIGITAL 17 Watts per card 340 Watts per crate Overall Power Requirements -------------------------- Digital Supply: +5.0 Volts 340 Watts per crate Analog Supplies: +3.3 Volts 254 Watts per crate +5.0 Volts 69 Watts per crate -5.0 Volts 48 Watts per crate Total DC power in each crate is: 710 Watts Estimate the efficiency of the supplies at 65% --> 1100 Watts Add 200 Watts for the fans in the crate --> total of 1300 Watts per crate The ADF-2 requires the following Buffer, Receiver, Driver, and Fanout functions: ---------------------------------------- The ADF-2 uses a number of buffers, Receivers, Drivers, and Fanout circuits. The table below shows the number of signals that must be processed by each type of these functions. Qty Description Function --- ----------------------------------- -------------------------------- 1 Receive LVDS & drive differential Receive the BX Clock from SCLD & open collector 48 ma. 5 Volt TTL Drive BX_Clock onto backplane onto the backplane 5 Receive LVDS & drive open collector Receive SCLD Control signals 48 ma. 5 Volt TTL onto backplane and Drive SCLD Control Signals onto backplane 5 Receive 5 V tolerant inputs and Receive SCLD Control Signals drive 3.3 Volt CMOS outputs from Backplane and send to FPGA 1 Receive LVDS input and drive 1 Receive BX_Clock from backplane 3.3 Volt CMOS output and send it to Board Control PAL 1 Receive CMOS input and drive 5 low Distribute 8x BX Clock to FPGAs skew 3.3 Volt CMOS outputs and to Channel Link parts Clock Buffer 4 Receive 3.3 Volt CMOS inputs and Drive Crate_Status onto Backplane drive open collector 48 ma. 5 Volt TTL outputs 2 Receive 3.3 Volt CMOS input and Send the Crate_to_SCLD signals drive LVDS outputs to the SCLD. 31 Receive 5 Volt TTL input and drive Latch 31 VME Bus signals 3.3 Volt CMOS Output with a "D" Latch function that has 3.3 Volt CMOS clock inputs 16 Transceiver: 5 Volt TTL 48 ma Buffer VME Data Lines. on 1 side, 3.3 Volt CMOS on the other side, 3.3 Volt CMOS control inputs 1 Receive 3.3 Volt CMOS input and Drive VME DTACK* drive open collector 48 ma. 5 Volt TTL output 1 Receive 5 Volt tolerant inputs Receive backplane signal and and drive 5 Volt output (must drive the Power Up Supervisor be powered from VCC_LOGIC supply) RESIN* input pin. 1 Receiver the 5 Volt VME DS1* signal and send it to the Board Control PAL. Spare Sections in the Receivers Drivers Buffers and Latches ----------------------------------------------------------- U1002 the 74LVC16374A 16 bit "D" Latch has one unused section. The input to the unused section of U1001 is pin 47. The output from the unused section is pin 2. The input to this unused section is tied to ground through zero Ohm jumper W1006. The unused section of U1002 is covered in the net list file: vme_to_board_control_pal_nets.txt That file contains all nets to both U1001 and U1002. U1021 74AS760 octal non-inv open collector driver has 2 unused sections. The unused sections of U1021 are: input pin 13 output pin 7 and input pin 15 output pin 5. These two unused input are tied to ground through zero Ohm jumpers W1028 and W1029. All nets to U1021 are contained in the net list file: receive_scld_drive_backplane_nets.txt U1031 74AS756 octal inverting open collector driver has 1 unused section. The unused section of U1031 is: input pin 15 output pin 5. This unused input is tied to ground through zero Ohm jumper W1031. The unused section of U1031 is covered in the net list file: receive_scld_drive_backplane_nets.txt The nets connecting to U1031 are contained in these 4 net list files: receive_scld_drive_backplane_nets.txt drive_crate_status_and_crate_to_scld_nets.txt power_up_supervisor_nets.txt vme_to_board_control_pal_nets.txt U1041 the 74LVC540 octal receiver buffer has 2 unused sections. The two unused sections of U1041 are: Input on pin 2 and output on pin 18 and Input on pin 3 and output on pin 17. The input to the two unused setions is connected to Ground through zero Ohm jumpers W1041, W1042. The nets for the 2 spare sections of U1041 are included in the first of the following 2 net list files. The following 2 net list files contain all of the nets for U1041: receive_backplane_timing_and_control_nets.txt vme_to_board_control_pal_nets.txt U1052 the SN65LVDS32 Quad LVDS Receive has one unused section. The inputs are: Comp pin 1 Direct pin 2 Its out is pin 3. There is a 100 Ohm terminator resistor across the input pins of this receiver. It is resistor R1055. Nets to the U1051 and U1052 LVDS Receives are in net list files: receive_scld_drive_backplane_nets.txt and receive_backplane_timing_and_control_nets.txt The unused section of U1052 is covered in the net list file: receive_scld_drive_backplane_nets.txt U1071 the SN65LVDS31 LVDS Driver has two unsused sections. The inputs to these two spare drivers are pins 1 and 7 which are tied to ground with zero Ohm jumpers W1071 and W1072. The outputs from these two spare drivers are pins 2,3 and pins 6,5. 100 Ohm terminator resistors R1073 and R1074 are used across these output pairs. The two unused sections of U1071 the LVDS Driver are included in the net list file: drive_crate_status_and_crate_to_scld_nets.txt Mentor Graphics Geometries Required for ADF-2 (initial list) ----------------------------------------------- Fuse Block from Littelfuse data sheet SMD Transient Voltage Suppressor from OnSemi data sheet SMD BIG Electrolytic from Panasonic data sheet SMD BIG Tantalum from Kemet data sheet Case Size D SMD Small Tantalum from Kemet data sheet Case Size A SMD RC 0603 from Mentor or IPC or Kemet SMD RC 0805 from Mentor or IPC or Kemet SMD Chip Resistor Arrays 0402 2, 4, 8 Resistor From Panasonic or CTS SMD DC/DC Converter from Datel SMD 3 pin SOT23 Body 1.3 mm Wide 2.9 mm Long from IPC SMD 8 pin TSSOP Body 4.4 mm Wide 3.0 mm Long 0.65 mm Pitch from TI SMD 8 pin MSOP Power PAD Body 3.0 mm Wide 3.0 mm Long 0.65 mm Pitch Power Pad about 1.8 x 1.8 mm from TI ?? SMD 16 pin TSSOP Body 4.4 mm Wide 5.0 mm Long 0.65 mm Pitch from TI SMD 20 pin SOIC from TI DW or IPC SMD 20 pin TSSOP Body 4.4 mm 0.65 mm Pitch from TI PW SMD 48 pin TSSOP48 Body 6.1 mm 0.5 mm Pitch from ?? SMD 48 pin Low Profile Quad Flat Pack (LQFP) (ST-48) from IPC SMD Body 7.0 mm Square Leads 9.0 mm Square 0.5 mm Pitch 100 pin TQFP Body 14 mm Square Leads 16 mm Square 0.5 mm Pitch from IPC SMD 144 pin TQ144 from IPC SMD 456 pin FG456 from Xilinx SMD-THD Backplane connectors 5x32 from Harting THD VME-64 connector 5x19 plus from Harting THD 5 column (plus shield) by 19 row 2mm hard metric connector DeBug Connector ??? from ?? SMD LED's from Dialight SMD-THD VCOX PLL from Vectron SMD Via for routing Mounting hole for M2.5 screw Jumper Locations ---------------- The ADF-2 circuit board uses 19 jumpers (zero Ohm 0603 resistors) to control spare resources and resources that are not used on all cards. 7 of these jumpers (W1021:W1027) are installed only on the one Maestro ADF-2 card in each crate. The following table lists all 19 jumpers, gives their X,Y location in mm, shows their function, and indicates if they are installed only on the Maestro ADF-2 cards. Location Jumper ------------- Ref X Y Function ------ ----- ----- -------------------------------------------------- W801 102.4 122.0 JTAG Data from BC PAL Output to FPGA U801 Input W802 53.5 122.0 JTAG Data from FPGA U801 Output to FPGA U901 Input W803 14.9 167.3 JTAG Data from FPGA U901 Output to Connector P4-8 W1006 130.0 199.3 Unused section of U1002 74LVC16374A input pin 47 W1021 141.0 191.0 Drive "Begin Turn_B" onto Backplane Z13 "M" Only W1022 141.0 185.9 Drive "Live BX_B" onto Backplane Z15 "M" Only W1023 141.0 180.9 Drive "Save_Monit_B" onto Backplane Z17 "M" Only W1024 141.0 178.4 Drive "SCL_Init_B" onto Backplane Z19 "M" Only W1025 141.5 170.8 Drive "BX_CLK" onto Backplane Z21 "M" Only W1026 141.5 165.8 Drive "BX_CLK_B" onto Backplane Z23 "M" Only W1027 141.5 160.5 Drive "SCLD_SPARE_B" onto Backplane Z25 "M" Only W1028 110.0 200.0 Unused section of U1021 74AS760 input pin 13 W1029 116.0 200.0 Unused section of U1021 74AS760 input pin 15 W1031 96.0 199.6 Unused section of U1031 74AS756 input pin 15 W1041 141.0 173.5 Unused section of U1041 74LVC540 input pin 2 W1042 141.0 175.9 Unused section of U1041 74LVC540 input pin 3 W1071 89.4 181.6 Unused LVDS Driver U1071 65LVDS31 input pin 1 W1072 89.4 174.4 Unused LVDS Driver U1071 65LVDS31 input pin 7 W1401 49.8 171.3 BC PAL U1101 "PAL_BX_CLOCK" input Engineering Change Orders ------------------------- ADF-2 Card Engineering Change Order Number 1 8-APR-2005 Description of the Problem During VME Read cycles there can be a positive noise spike on the BG_1_IN* signal that is received from the backplane. This positive noise spike can trigger the Power Up Supervisor circuit and thus cause a shutdown of the DC/DC Converters. This will cascade from the card where it begins up through all higher slot number ADF-2 cards. The DC/DC Converter shutdown causes a loss of Configuration in the Data Path FPGA's. - This problem is most evident in a fully loaded crate. It is not seen in a crate with only 3 or 4 cards. - All ADF-2 cards exhibit this problem. - Some crate slots show this problem a lot more than others. It has never been seen in some slots. The two different crates that were tested behaved the same way. - It only happens on VME Read cycles. The cascade starts from the card that is the target of the Read cycle. - The positive noise spike on the BG_1_IN* backplane signal is much more evident when reading lots of zeros. If you are reading $FFFF there is no noise. If you are reading $0000 you see the most noise. - The polarity of the noise spike on the BG_1_IN* backplane signal implies that the cause is not simple capacitive coupling to the data lines or ground bounce on the ADF-2 card. Installation of ECO #1 This required ECO involves installation of a 470 pFd capacitor from the BG_1_IN* signal on the ADF-2 card to Ground. All ADF-2 cards are to receive this ECO. This new 470 pFd capacitor is Reference Designator C1354. It is a 100 Volt, COG Dielectric, 5% capacitor with wire leads. Digi-Key part number: P4857-ND The capacitor is installed between U1031 pin 17 (the BG_1_IN* signal coming in from the backplane) and U1031 pin 10 (which is Ground). Install the capacitor with the marking side visible. Form the capacitors leads so that the routing is direct, and the body of the capacitor is down flat against the U1031 component. A jig is used to accurately form the capacitor leads. Wet the capacitor leads before installing it. Post installation inspection: - Make certain that the capacitor is put on U1031 and not on the other near by SOIC component. - Make certain that the capacitor runs between pins 10 and 17. - Soldering the capacitor lead to pin 17 should wet the front of this component pin (not just the foot of pin 17). - It is OK for the capacitor lead to come down along the side of pin 10. Make certain the the front of this component pin is wetted when the capacitor lead is soldered. That is don't solder this capacitor lead to just the foot of the component pin. - Make certain that the body of the capacitor is down flat against the top of component U1031. Testing after Installation of ECO #1 Installation of this ECO is straight forward enough that ADF-2 cards do not have to go back through "Production Testing" after receiving this ECO. After receiving this ECO all cards must pass through the "System Crate Tests" before being sent to Fermi.