ADF-2 FPGA Resource Usage Rev:21-May-04 Virtex-II Block SelectRAM Memory Resources ------------------------------------------ The Virtex-II family includes dedicated blocks of 18kbit dual-ported memory resources distributed across the chip. Xilinx calls this type of resource "Block SelectRAM Memory". Two of the many user choices of Block SelectRAM configurations are of special interest for the ADF-2 application: 1k x 18 bits and 2k x 9 bits. The 9 and 18 bit widths are meant to support parity as 8+1 and 16+2. However the full data width can be used as regular RAM. Block SelectRAM cells are true synchronous RAM memories. The two ports are completely independent of each other (that is, clocking, control, address, read/write functions, initialization, and data width) without arbitration. Each port has a separate set of Data In and Data Out connections. The XC2V100 used on the ADF-2 is a 1 million gate device which includes 40 such 18kbit SelectRAM blocks. ADF-2 Memory needs ------------------ The ADF-2 Data Path FPGA will use memory for several purposes: a) Memory lookup to scale input energy E into Transverse energy Et. b) Record the raw 10-bit over-sampled ADC data for a period long enough to be able to capture (i.e. remember) the raw ADC data that corresponds to a given L1 Accept issued by the L1 Framework via the SCL. Recording one full accelerator turn would be a nice target. c) Record the final 8-bit output of the ADF-2 as sent to the TAB and/or the filtered trigger tower energy before lookup and before Live Crossing Suppression. d) Support testing with simulated data that can be arbitrary programmed by TCC. Being able to play back one full accelerator turn worth of data would be a good achievement. ADF-2 Block Memory Usage ------------------------ Each ADF-2 Data Path FPGA is responsible for 8 EM+HD channel pairs. With 40 Block SelectRAM, we have 5 blocks for each channel pair, or 2 1/2 blocks per channel. Each Channel can have two blocks, and share one more block within a pair. Block #1) 2k x 9 bits for EM Et Memory Lookup Port A: Data Path Port Read only : EM Et Lookup Address = 10 bit filtered EM E Data In = Unused Data Out = 8 bit EM Et 1 spare bit Port B: TCC Port Write : TCC Write EM Et Lookup Table Read : TCC Verify EM Et Lookup Table Address = 11 LSB of On-Card Bus Address Data In = 9 LSB bits of On-Card Bus Data Data Out = 9 LSB bits of On-Card Bus Data 2k corresponds to an 11 bit address for E. The Raw ADC data is 10 bits, and this leaves an "overflow bit" in case the filtering stage involves summing or a multiplication factor. Block #2) 2k x 9 bits for HD Et Memory Lookup Same as Block #1, but for HD Channel Block #3) 1k x 18 bits for Raw EM ADC Data Port A: Data Path Port Write : Monitoring Data Read : Re-play Simulated 10 bit Raw EM ADC Data Address = 8 MSB are Tick Number 2 LSB are 2 MSB of Sub-Tick Number Data In = 10 LSB are 10 bit Raw EM ADC Data 6 spare bits 2 MSB unused bits Data Out = 10 LSB are 10 bit Simulated Raw ADC Data 6 spare bits 2 MSB unused bits Port B: TCC Port Write : TCC Write Simulated Raw ADC EM Data Read : TCC Read Monitoring Data or Verify Simulated Data Address = 10 LSB of On-Card Bus Address Data In = 16 bit On-Card Bus Data 2 MSB unused bits Data Out = 16 bit On-Card Bus Data 2 MSB unused bits 1k corresponds to a 10 bit address, or 1024 samples. This is sufficient to hold 159 Ticks sampled at 4 times the Beam Crossing rate, which corresponds to 636 samples per Turn. Block #4) 1k x 18 bits for Raw HD ADC Data Same as Block #3, but for HD Channel Block #5) 1k x 18 bits for Final EM & HD Et Output Port A: Data Path Port Write : Monitoring Data Read : Re-play Simulated EM & HD Et Data Address = 2 MSB are 2 bit Turn Number 8 LSB are Tick Number Data In = 8 LSB are 8 bit Final EM Et Output 8 bit Final HD Et Output 2 MSB unused bits Data Out = 8 LSB are 8 bit Final EM Et Output 8 bit Final HD Et Output 2 MSB unused bits Port B: TCC Port Write : TCC Write Simulated EM & HD Et Data Read : TCC Read Monitoring EM & HD Et Data or Verify Simulated EM & HD Et Data Address = 10 LSB of On-Card Bus Address Data In = 16 bit On-Card Bus Data 2 MSB unused bits Data Out = 16 bit On-Card Bus Data 2 MSB unused bits 1k corresponds to a 10 bit address. This can hold up to 1024 Ticks of data sampled at the Beam Crossing Rate. Such a large sample would be useful for building Trigger Tower Energy histograms. One could record 3 times more useful data by recording only the Live Crossings, but this would involve some significant complexity for little gain, and would no longer represent what is being sent to the TABs. The ADF-2 will record every Crossing. Generating a linearly incrementing address would yield over 6 full Turns, but be tricky to correlate to the rest of the monitoring data. We will instead use the 8 bit Tick Number for the lower address bits, and a 2 Bit Turn Number for the upper bits, which will still record 4 full turns,while being easier to manage.