Operating Parameters for the ADF-2 Cards in the Run 2B L1 Calorimeter Trigger System --------------------------------------------- Initial Rev: 7-DEC-2005 Current Rev: 14-JUN-2006 The intent of this file is to collect all of the data that is needed to operate the ADF-2 cards when they are functioning as part of the overall Run 2B L1 Cal Trig system. It is assumed that this file will have a number of almost independent sections and that it will develop and be added to as we learn more about running the ADF-2 cards in the Run 2B L1 Cal Trig system. This file is started with a description of the Et Lookup Memory data and the ADC Alignment Delay data that will be used for the initial operation of the Run 2B L1 Cal Trig system in March 2006. ========================================================================= ========================================================================= Et Lookup Memory Calibration Data for Initial Running ------------------------------------------------------- Section Rev: 7-DEC-2005 The intent of this note is to give a "best current understanding" of the Et Lookup Memory data that will be needed for the initial operation of the ADF-2 cards in March 2006. The Et Lookup Memory takes the output of the "filter" and shifts the "zero energy value" and changes the scale so that the final output data from the ADF-2 card has a "zero energy value of $08 counts and a scale of 1/4 GeV Et per count. By convention we will always run the ADF-2 card so that the output data from the "filter" will have a zero energy value of 50 decimal. This is directly implemented by always setting the ADC zero energy response to 50 counts decimal. Details about the BLS input signals are included in the web file: www.pa.msu.edu/hep/d0/ftp/run2b/l1cal/hardware/adf_2/general/ adf_2_bls_input_signals.txt The following table shows the current best understanding of the required slope that must be implemented in the Et Lookup Memories for the various etas EM and HD. This is based on the summer 2003 calibration of the Run 2A L1 Cal Trig. The summer 2003 calibration does not include any information about the TT_Eta 19, 20 signals, i.e. the massless gap and ICD signals. Slope is defined as (rise over run): delta_filter_output x Slope = delta_Et_Lookup_Mem_Output EM HD --------------------------- --------------------------- Expected ADF-2 Required Expected ADF-2 Required ADC Response EM Et ADC Response HD Et -------------- Lookup -------------- Lookup EM GeV Et per Memory HD GeV Et per Memory TT Eta EM ADC LSBit Slope HD ADC LSBit Slope ------ ------------- -------- ------------- -------- 1 0.1141 GeV 0.4564 0.1381 GeV 0.5524 2 0.1095 0.4380 0.1328 0.5312 3 0.1019 0.4076 0.1138 0.4552 4 0.0910 0.3640 0.1031 0.4124 5 0.1063 0.4252 0.1544 0.6176 6 0.0923 0.3692 0.1459 0.5836 7 0.0667 0.2668 0.0651 0.2604 8 0.0597 0.2388 0.0732 0.2928 9 0.1245 0.4980 0.1368 0.5472 10 0.1032 0.4128 0.1148 0.4592 11 0.0852 0.3408 0.0854 0.3416 12 0.0692 0.2768 0.0696 0.2784 13 0.0756 0.3024 0.0765 0.3060 14 0.0615 0.2460 0.0623 0.2492 15 0.1840 0.7360 0.1962 0.7848 16 0.1506 0.6024 0.1606 0.6424 17 0.1096 0.4384 0.1087 0.4348 18 0.0706 0.2824 0.0584 0.2336 Notes about the Slope of the data in the Et Lookup Memory: A slope of > 1.0 is fatal. It means that the data coming out of the Filter (i.e. coming out of the ADC) is already coarser than 0.25 GeV per LSBit. A slope of 0.4049 is just in the center of the range where you would like to be operating. A slop of < 0.2539 means that the "sensitivity" of that channel is so high (i.e. so few GeV per LSBit of the ADC output data) that with 10 bits you do not get the whole way up to 61.75 GeV Et. Thus the output of that Et Lookup Memory will never reach 61.75 GeV i.e. that channel will "saturate" before reaching 61.75 GeV. This Et Lookup Memory calibration data in the table format for use by the Run 2B L1 Cal Trig TCC is shown below. !------------------------------------------------------------------------------ ! L1Cal_IIb_Lookup_Coeffs.tti !------------------------------------------------------------------------------ ! Comments start with an exclamation mark ("!") anywhere on a line. ! See end of file for more syntax information. !------------------------------------------------------------------------------ ! Revision: 7-Dec-2005 !-------------------------------------------------------------------- ! Define some cosmetic constants to make the rest easier to read ! Trigger Tower Channel Type $TT_EM_Channel= 0 $TT_HD_Channel= 1 ! Trigger Tower Eta Sign $TT_Eta_Pos= 0 $TT_Eta_Neg= 1 !--------------------------- ! Define EM Et Lookup Coefficients !--------------------------- TT_Channel: $TT_EM_Channel TT_Eta_Sign: $TT_Eta_Pos To_TT_Eta_Sign: $TT_Eta_Neg TT_Eta_Magn: 1 To_TT_Eta_Magn: 20 TT_Phi: 1 To_TT_Phi: 32 Zero_Energy_Adc_E: 50 ! Zero Energy Response of the ADC and ! Filtered E data. This is the input ! address to the Et Lookup Memory. Zero_Energy_Output_Et: 8 ! Zero Energy Response of the ADF-2 ! Output Et data to the TAB. This is ! the output data from the Et Lookup ! Memory. ! The Slope is eta dependent. ! For this initial setup the slope is independent of the sign of eta. ! For this initial setup we will set the slope of TT_Etas 19, 20 to ! mid scale. TT_Eta 19 and 20 are the massless gap and ICD signals. TT_Eta_Magn: 1 Lookup_Slope: 0.4564 TT_Eta_Magn: 2 Lookup_Slope: 0.4380 TT_Eta_Magn: 3 Lookup_Slope: 0.4076 TT_Eta_Magn: 4 Lookup_Slope: 0.3640 TT_Eta_Magn: 5 Lookup_Slope: 0.4252 TT_Eta_Magn: 6 Lookup_Slope: 0.3692 TT_Eta_Magn: 7 Lookup_Slope: 0.2668 TT_Eta_Magn: 8 Lookup_Slope: 0.2388 TT_Eta_Magn: 9 Lookup_Slope: 0.4980 TT_Eta_Magn: 10 Lookup_Slope: 0.4128 TT_Eta_Magn: 11 Lookup_Slope: 0.3408 TT_Eta_Magn: 12 Lookup_Slope: 0.2768 TT_Eta_Magn: 13 Lookup_Slope: 0.3024 TT_Eta_Magn: 14 Lookup_Slope: 0.2460 TT_Eta_Magn: 15 Lookup_Slope: 0.7360 TT_Eta_Magn: 16 Lookup_Slope: 0.6024 TT_Eta_Magn: 17 Lookup_Slope: 0.4384 TT_Eta_Magn: 18 Lookup_Slope: 0.2824 TT_Eta_Magn: 19 Lookup_Slope: 0.4 TT_Eta_Magn: 20 Lookup_Slope: 0.4 !--------------------------- ! Define HD Et Lookup Coefficients !--------------------------- TT_Channel: $TT_HD_Channel TT_Eta_Sign: $TT_Eta_Pos To_TT_Eta_Sign: $TT_Eta_Neg TT_Eta_Magn: 1 To_TT_Eta_Magn: 20 TT_Phi: 1 To_TT_Phi: 32 Zero_Energy_Adc_E: 50 ! Zero Energy Response of the ADC and ! Filtered E data. This is the input ! address to the Et Lookup Memory. Zero_Energy_Output_Et: 8 ! Zero Energy Response of the ADF-2 ! Output Et data to the TAB. This is ! the output data from the Et Lookup ! Memory. ! The Slope is eta dependent. ! For this initial setup the slope is independent of the sign of eta. ! For this initial setup we will set the slope of TT_Etas 19, 20 to ! mid scale. TT_Eta 19 and 20 are the massless gap and ICD signals. TT_Eta_Magn: 1 Lookup_Slope: 0.5524 TT_Eta_Magn: 2 Lookup_Slope: 0.5312 TT_Eta_Magn: 3 Lookup_Slope: 0.4552 TT_Eta_Magn: 4 Lookup_Slope: 0.4124 TT_Eta_Magn: 5 Lookup_Slope: 0.6176 TT_Eta_Magn: 6 Lookup_Slope: 0.5836 TT_Eta_Magn: 7 Lookup_Slope: 0.2604 TT_Eta_Magn: 8 Lookup_Slope: 0.2928 TT_Eta_Magn: 9 Lookup_Slope: 0.5472 TT_Eta_Magn: 10 Lookup_Slope: 0.4592 TT_Eta_Magn: 11 Lookup_Slope: 0.3416 TT_Eta_Magn: 12 Lookup_Slope: 0.2784 TT_Eta_Magn: 13 Lookup_Slope: 0.3060 TT_Eta_Magn: 14 Lookup_Slope: 0.2492 TT_Eta_Magn: 15 Lookup_Slope: 0.7848 TT_Eta_Magn: 16 Lookup_Slope: 0.6424 TT_Eta_Magn: 17 Lookup_Slope: 0.4348 TT_Eta_Magn: 18 Lookup_Slope: 0.2336 TT_Eta_Magn: 19 Lookup_Slope: 0.4 TT_Eta_Magn: 20 Lookup_Slope: 0.4 ========================================================================= ========================================================================= ========================================================================= BLS Signal Latency Compensation Data for Initial Running ------------------------------------------------------------ Section Rev: 7-DEC-2005 The intent of this note is to give a "best current understanding" of the delays that must be inserted into the ADC output signals to compensate for the latency of the BLS Signals from the various locations in the Calorimeter. This is the setup data that will be used for the initial operation of the ADF-2 cards in March 2006. The following timing alignment delay data takes care of the relative latencies between the various BLS signals. In addition to that the overall latency of the ADC data is adjusted by the "global base alignment delay value" which TCC gets from the boot_auxi.mcf file (or can be explicit given to TCC at anytime from the console). The initial alignment delay data that will be used with the ADF-2 system just matches the delays that are used in the Run 2A L1 Cal Trig CTFE cards. For details on the CTFE ADC Clock vs BLS signal timing please see the log book for: 19:25-JULY-2002, 31-JULY, 1:2-AUG-2002, 7-AUG-2002, 10:13-DEC 2002, 6-JAN-2003, 11:15-Nov-2003, 9:13-JUNE-2003. This setup basically just compensates for the added delay caused by the longer cable runs to CC and South EC. North EC, which is negative eta, has the shortest BLS cables to the MCH and thus North EC data must be delayed for a longest time on the ADF-2 cards. We have no good understanding of when the massless gap and ICD signals should be sampled, i.e. TT_Etas 19 and 20. The initial alignment delay setup will be: EM_TT_Etas -20:-7 additional delay 2 X4_Clocks EM_TT_Etas -6:+6 additional delay 1 X4_Clocks EM_TT_Etas +7:+20 additional delay 0 X4_Clocks HD_TT_Etas -20:-6 additional delay 2 X4_Clocks HD_TT_Etas -5:+5 additional delay 1 X4_Clocks HD_TT_Etas +6:+20 additional delay 0 X4_Clocks This Alignment Delay data in the table format for use by the Run 2B L1 Cal Trig TCC is shown below. !------------------------------------------------------------------------------ ! L1Cal_IIb_Alignment_Delay.tti !------------------------------------------------------------------------------ ! Comments start with an exclamation mark ("!") anywhere on a line. ! See end of file for more syntax information. !------------------------------------------------------------------------------ ! Revision: 7-Dec-2005 !-------------------------------------------------------------------- ! Define some cosmetic constants to make the rest easier to read ! Trigger Tower Channel Type $TT_EM_Channel= 0 $TT_HD_Channel= 1 ! Trigger Tower Eta Sign $TT_Eta_Pos= 0 $TT_Eta_Neg= 1 !--------------------------- ! Define EM Trigger Tower Alignment Delay !--------------------------- TT_Channel: $TT_EM_Channel TT_Eta_Sign: $TT_Eta_Pos TT_Phi: 1 To_TT_Phi: 32 TT_Eta_Magn: 1 Alignment_Delay: 1 TT_Eta_Magn: 2 Alignment_Delay: 1 TT_Eta_Magn: 3 Alignment_Delay: 1 TT_Eta_Magn: 4 Alignment_Delay: 1 TT_Eta_Magn: 5 Alignment_Delay: 1 TT_Eta_Magn: 6 Alignment_Delay: 1 TT_Eta_Magn: 7 Alignment_Delay: 0 TT_Eta_Magn: 8 Alignment_Delay: 0 TT_Eta_Magn: 9 Alignment_Delay: 0 TT_Eta_Magn: 10 Alignment_Delay: 0 TT_Eta_Magn: 11 Alignment_Delay: 0 TT_Eta_Magn: 12 Alignment_Delay: 0 TT_Eta_Magn: 13 Alignment_Delay: 0 TT_Eta_Magn: 14 Alignment_Delay: 0 TT_Eta_Magn: 15 Alignment_Delay: 0 TT_Eta_Magn: 16 Alignment_Delay: 0 TT_Eta_Magn: 17 Alignment_Delay: 0 TT_Eta_Magn: 18 Alignment_Delay: 0 TT_Eta_Magn: 19 Alignment_Delay: 0 TT_Eta_Magn: 20 Alignment_Delay: 0 TT_Eta_Sign: $TT_Eta_Neg TT_Phi: 1 To_TT_Phi: 32 TT_Eta_Magn: 1 Alignment_Delay: 1 TT_Eta_Magn: 2 Alignment_Delay: 1 TT_Eta_Magn: 3 Alignment_Delay: 1 TT_Eta_Magn: 4 Alignment_Delay: 1 TT_Eta_Magn: 5 Alignment_Delay: 1 TT_Eta_Magn: 6 Alignment_Delay: 1 TT_Eta_Magn: 7 Alignment_Delay: 2 TT_Eta_Magn: 8 Alignment_Delay: 2 TT_Eta_Magn: 9 Alignment_Delay: 2 TT_Eta_Magn: 10 Alignment_Delay: 2 TT_Eta_Magn: 11 Alignment_Delay: 2 TT_Eta_Magn: 12 Alignment_Delay: 2 TT_Eta_Magn: 13 Alignment_Delay: 2 TT_Eta_Magn: 14 Alignment_Delay: 2 TT_Eta_Magn: 15 Alignment_Delay: 2 TT_Eta_Magn: 16 Alignment_Delay: 2 TT_Eta_Magn: 17 Alignment_Delay: 2 TT_Eta_Magn: 18 Alignment_Delay: 2 TT_Eta_Magn: 19 Alignment_Delay: 2 TT_Eta_Magn: 20 Alignment_Delay: 2 !--------------------------- ! Define HD Trigger Tower Alignment Delay !--------------------------- TT_Channel: $TT_HD_Channel TT_Eta_Sign: $TT_Eta_Pos TT_Phi: 1 To_TT_Phi: 32 TT_Eta_Magn: 1 Alignment_Delay: 1 TT_Eta_Magn: 2 Alignment_Delay: 1 TT_Eta_Magn: 3 Alignment_Delay: 1 TT_Eta_Magn: 4 Alignment_Delay: 1 TT_Eta_Magn: 5 Alignment_Delay: 1 TT_Eta_Magn: 6 Alignment_Delay: 0 TT_Eta_Magn: 7 Alignment_Delay: 0 TT_Eta_Magn: 8 Alignment_Delay: 0 TT_Eta_Magn: 9 Alignment_Delay: 0 TT_Eta_Magn: 10 Alignment_Delay: 0 TT_Eta_Magn: 11 Alignment_Delay: 0 TT_Eta_Magn: 12 Alignment_Delay: 0 TT_Eta_Magn: 13 Alignment_Delay: 0 TT_Eta_Magn: 14 Alignment_Delay: 0 TT_Eta_Magn: 15 Alignment_Delay: 0 TT_Eta_Magn: 16 Alignment_Delay: 0 TT_Eta_Magn: 17 Alignment_Delay: 0 TT_Eta_Magn: 18 Alignment_Delay: 0 TT_Eta_Magn: 19 Alignment_Delay: 0 TT_Eta_Magn: 20 Alignment_Delay: 0 TT_Eta_Sign: $TT_Eta_Neg TT_Phi: 1 To_TT_Phi: 32 TT_Eta_Magn: 1 Alignment_Delay: 1 TT_Eta_Magn: 2 Alignment_Delay: 1 TT_Eta_Magn: 3 Alignment_Delay: 1 TT_Eta_Magn: 4 Alignment_Delay: 1 TT_Eta_Magn: 5 Alignment_Delay: 1 TT_Eta_Magn: 6 Alignment_Delay: 2 TT_Eta_Magn: 7 Alignment_Delay: 2 TT_Eta_Magn: 8 Alignment_Delay: 2 TT_Eta_Magn: 9 Alignment_Delay: 2 TT_Eta_Magn: 10 Alignment_Delay: 2 TT_Eta_Magn: 11 Alignment_Delay: 2 TT_Eta_Magn: 12 Alignment_Delay: 2 TT_Eta_Magn: 13 Alignment_Delay: 2 TT_Eta_Magn: 14 Alignment_Delay: 2 TT_Eta_Magn: 15 Alignment_Delay: 2 TT_Eta_Magn: 16 Alignment_Delay: 2 TT_Eta_Magn: 17 Alignment_Delay: 2 TT_Eta_Magn: 18 Alignment_Delay: 2 TT_Eta_Magn: 19 Alignment_Delay: 2 TT_Eta_Magn: 20 Alignment_Delay: 2 ========================================================================= ========================================================================= ========================================================================= Memory Block Address Offsets in the Boot_Auxi.mcf File -------------------------------------------------------- Section Rev: 12-JAN-2006 This section describes the Register Address Offsets that are used to associated either the Monitor Data or Simulation Data in one of the memory blocks with a given Tick Number. Background Information: - The Ticks are numbered 1:159. The first Live Beam Crossing of the first Super Bunch is on Tick Number 7. The table showing the Tick Numbers in decimal and in hex of the Live Crossings is: SCL Frame L1 Accept Tick Number of the 36x36 Accelerator Live Crossings --------------------------------------- First Second Third Super Super Super Bunch Bunch Bunch --------- --------- --------- BX dec hex dec hex dec hex ---- --- --- --- --- --- --- 1st 7 07 60 3c 113 71 2nd 10 0a 63 3f 116 74 3rd 13 0d 66 42 119 77 4th 16 10 69 45 122 7a 5th 19 13 72 48 125 7d 6th 22 16 75 4b 128 80 7th 25 19 78 4e 131 83 8th 28 1c 81 51 134 86 9th 31 1f 84 54 137 89 10th 34 22 87 57 140 8c 11th 37 25 90 5a 143 8f 12th 40 28 93 5d 146 92 - The offsets shown below are for the ADF-2 T7-Phy Data Path firmware. These offsets may change for future versions of the Data Path firmware. - These offsets were first determined in July 2005 and then checked again in Jan 2006. All measurements were made on ADF-2 channel 0, i.e. 0,0 EM. - The specific measurements that were made are the following: Raw ADC Simulation Data The 159 x 4 = 636 Register Addresses that are used in this Raw ADC memory block are 2048:2683. It was determined that the Raw ADC Simulation Data in memory block Reg Adrs 2072 controls the Final Output Et value for Tick #7 i.e. the first Live BX of the first Super Bunch. This implies that the Raw ADC Simulation Data in memory block Reg Adrs 2048 controls the Final Output Et value for Tick #1. This implies a Raw ADC Simulation Data Address Offset of 0. Final Output Monitor Data The 159 Reg Adrss that are used in this Final Output memory block are 1024:1182. It was determined that the Final Output Monitor Data in memory block Reg Adrs 1030 is the monitor data for Tick #7 i.e. the first Live BX of the first Super Bunch. This implies that the Final Output Monitor Data in memory block Reg Adrs 1024 is the Monitor Data for Tick #1. This implies a Final Output Monitor Data Address Offset of 0. Final Output Simulation Data The 159 Reg Adrss that are used in this Final Output memory block are 1024:1182. It was determined that the Final Output Simulation Data in memory block Reg Adrs 1029 is the simulation data for Tick #7 i.e. the first Live BX of the first Super Bunch. This implies that the Final Output Simulation Data in memory block Reg Adrs 1182 is the Simulation Data for Tick #1. This implies a Final Output Simulation Data Address Offset of -1. - The above demonstrate, as expected, that a given memory block location holds the Monitor data for Tick "N" and the Simulation data for Tick "N+1". - It needs to be checked, but from the above we will assume that the Raw ADC Monitor Data Address Offset is +1. From all of the above, the Memory Block Address Offsets that should be used in the Boot_Auxi.mcf file with the T7_Phy Data Path firmware are: !------------------------------------------------------------------------------ ! This is the Register Address Offset within the Raw ADC Memory Block ! where TCC will read Monitoring Data for the first ADC sample of Tick #1. !------------------------------------------------------------------------------ OffsetTick1RawAdcMonit: +1 !------------------------------------------------------------------------------ ! This is the Register Address Offset within the Raw ADC Memory Block ! where TCC will write Simulated Data for the first ADC sample of Tick #1. !------------------------------------------------------------------------------ OffsetTick1RawAdcSimu: 0 !------------------------------------------------------------------------------ ! This is the Register Address Offset within the Output Et Memory Block ! where TCC will read Monitoring Data for Tick #1. !------------------------------------------------------------------------------ OffsetTick1OutputEtMonit: 0 !------------------------------------------------------------------------------ ! This is the Register Address Offset within the Output Et Memory Block ! where TCC will write Simulated Data for Tick #1. !------------------------------------------------------------------------------ OffsetTick1OutputEtSimu: -1 ========================================================================= ========================================================================= ========================================================================= Offset Triggered to Tick at Capture in the Boot_Auxi.mcf File --------------------------------------------------------------- Section Rev: 12-JAN-2006 This section describes the current estimate of how far back in the monitor data one will need to look to find the data from the Tick that caused the L1_Acpt when the circular buffer monitor data writting was stopped by the Save Monitor Data signal. This calculation is done for the Final Output Monitor Data and it is assumed that TCC will calculate the Tick of the BX that caused the L1_Acpt the caused the Save Monitor Data signal based on the stopping address that it reads from the Final Output Address Generator. Background Information: - Calculating how far back one must look in the monitor data to find the data from the BX that caused the L1_Acpt is done by taking the difference between, how long after the BX happens that causes the L1_Acpt until the Address Generators actually stop, and how long it is between when a BX happens until the monitor data from that BX is actually written into the circular memory of monitor data. - How long is it from the time that the BX happens that causes the L1_Acpt that causes the Save Monitor Data signal until writing into the Final Output Monitor Data circular memories has actually stopped (i.e. until the Address Generators are stopped) ? 1. With the experiment timing that has been in use since late September 2002, the L1_Accept comes out of the SCL Receiver about 4.09 usec after the BX that caused the L1_Accept. 2. The delay in the SCDL in asserting the Save_Monitor_Data signal is expected to be 8 RF clocks i.e. 8 x 18.8 nsec = 150 nsec. 3. Transmission from the SCLD to the ADF-2 cards is fast, perhps 20 nsec. 4. The Data Path FPGA on the ADF-2 card does not ingest the Save_Monitor_Data signal until the next cycle of the BX_Clock, i.e. 132 nsec later. 5. The Address Generator stops, and the last data is written to the memory block on the next enabled clock to the Address Generator. This is 132 nsec later for the Final Et Output Address Generator. 6. This is a total of about 4524 nsec or about 34 Ticks. - How long is it from the time that a BX happens until the data from that BX is written into the Final Et Output Monitor Data circular memory block ? 1. Delay from the Beam Crossing to the peak of the BLS signal at the ADF-2 card is about 700 nsec. 2. Delay in the analog signal processing: 66 nsec 3. Delay in the ADC from analog sample to digital data output: 165 nsec 4. Delay to the output of the Data Path FPGA ADC Data I/O Block FDE: 33 nsec 5. Delay to the output of the ADC Data Alignment Shift Register when set for minimum delay: 33 nsec 6. Delay to output of the Filter delay: 33 nsec 7. Delay to clocking the address into the Et Lookup Menory: 33 nsec 8. Delay doing the lookup and delivering the Et value to the Ouput Memory Block, i.e. delay until the Et data has been clocked into the Output Memory Block: 132 nsec 9. This is a total of about 1195 nsec or about 9 Ticks. - The difference in these two numbers (34 minus 9) is 25 Ticks. Thus I think that the data from the BX that caused the L1_Acpt will be about 25 addresses back in the Final Et Output memory block. From all of the above the offset between the Triggered Tick and the last Tick captured in the Final Output Monitor Data memory block, when writing of monitor data is stopped by the Save Monitor Data signal, is the following. This is for the T7_Phy Data Path firmware and needs to be included in the Boot_Auxi.mcf file. !------------------------------------------------------------------------------ ! This value is the Tick Offset between the Triggered Crossing Tick Number ! and the Tick Number currently recorded at the time the Captured Monitoring ! Data Signal stops the Address Generator(s). !------------------------------------------------------------------------------ OffsetTriggeredToTickAtCapture: 25 ========================================================================= ========================================================================= ========================================================================= ADF Crate Wiener Power Supply Setup ----------------------------------------- Section Rev: 9-FEB-2006 The ADF Crate Wiener power supplies will work just fine with their default factory settings. The only thing that needed to be set was each crate's CAN-Bus Address. But, someone at Fermi insisted on playing with all the settings including moving some of them, e.g. the Over Voltage Protection crowbar, to dangerous values. Thus the following values have been set in all 4 ADF Crates. The spare Wiener power supply will be check for operation with the same setup. Setup of all 4 of the ADF Crates ADF U0 U1 U3 U5 Crate +5.0 V +5.0 V +3.3 V -5.0 V Setting Digital Analog Analog Analog ------- ------- ------ ------ ------ Ilim 80 A 20 A 80 A 20 A Uadj 0 % 0 % 0 % 0 % Unom 5.00 V 5.00 V 3.29 V 5.00 V OVP 6.25 V 6.25 V 3.50 V 6.25 V Imax 70 A 16 A 70 A 16 A Umin 4.75 V 4.75 V 3.10 V 4.75 V Umax 5.25 V 5.25 V 3.50 V 5.25 V Fans 3300 rpm CAN-Bus Address ADF Crate "A" = 1 ... ADF Crate "D" = 4 Notes: Ilim is the supply's output current limit. Uadj is the fine adjustment on the supply's output Voltage. Unom is the coarse adjustment on the supply's output Voltage. OVP is the trip point for the supply's Over Voltage Protection. Imax is the maximum current that may be drawn from the supply and still have it report "good" status to the monitoring. Umin is the minimum output Voltage that can be coming from the supply and still have it report "good" to the monitoring. Umax is the maximum output Voltage that can be coming from the supply and still have it report "good" to the monitoring. The +5V digital supply and the +3.3V supply are both 115A bricks The +- 5V analog supplies are both 30A bricks. ========================================================================= ========================================================================= ========================================================================= BLS Signal Latency Compensation Data First Adjustment After Initial Running -------------------------------------------------- Section Rev: 14-JUNE-2005 The initial setting of the BLS Signal Latency Compensation, that was used for the first 3 Stores in Run 2B is described above at the date 7-DEC-2005. This section describes the adjustments made to the BLS Signal Latency Compensation based on data collected during the first 3 Stores of Run 2B. The details of this data and its collection are in the log book. Summary of the adjustments made in this iteration of the BLS Signal Latency Compensation Data: For CC EM increase the delay by 2 ADC samples. For CC HD increase the delay by 1 ADC sample. For South (+) EC EM increase the delay by 1 ADC sample. For South (+) EC HD increase the delay by 2 ADC samples. For North (-) EC EM increase the delay by 1 ADC sample. For North (-) EC HD increase the delay by 2 ADC samples. The CC EC split implied here is between TT Eta 6 and 7, i.e. where the long BLS cable runs split between which section of the Platform they go to. The 14-JUNE-2006 version of the BLS Signal Latency Compensation Data is given in the following tti format table: !------------------------------------------------------------------------------ ! L1Cal_IIb_Alignment_Delay.tti !------------------------------------------------------------------------------ ! Comments start with an exclamation mark ("!") anywhere on a line. ! See end of file for more syntax information. !------------------------------------------------------------------------------ ! Revision: 14-June-2005 ! ! This is the first adjustment of the BLS Signal Latency Compensation Data ! based on data collected during running in the first three Stores of Run 2B. ! !------------------------------------------------------------------------------ ! ! Define some cosmetic constants to make the rest easier to read ! Trigger Tower Channel Type $TT_EM_Channel= 0 $TT_HD_Channel= 1 ! Trigger Tower Eta Sign $TT_Eta_Pos= 0 ! South $TT_Eta_Neg= 1 ! North !--------------------------- ! Define EM Trigger Tower Alignment Delay !--------------------------- TT_Channel: $TT_EM_Channel TT_Eta_Sign: $TT_Eta_Pos ! South TT_Phi: 1 To_TT_Phi: 32 TT_Eta_Magn: 1 Alignment_Delay: 3 TT_Eta_Magn: 2 Alignment_Delay: 3 TT_Eta_Magn: 3 Alignment_Delay: 3 TT_Eta_Magn: 4 Alignment_Delay: 3 TT_Eta_Magn: 5 Alignment_Delay: 3 TT_Eta_Magn: 6 Alignment_Delay: 3 TT_Eta_Magn: 7 Alignment_Delay: 1 TT_Eta_Magn: 8 Alignment_Delay: 1 TT_Eta_Magn: 9 Alignment_Delay: 1 TT_Eta_Magn: 10 Alignment_Delay: 1 TT_Eta_Magn: 11 Alignment_Delay: 1 TT_Eta_Magn: 12 Alignment_Delay: 1 TT_Eta_Magn: 13 Alignment_Delay: 1 TT_Eta_Magn: 14 Alignment_Delay: 1 TT_Eta_Magn: 15 Alignment_Delay: 1 TT_Eta_Magn: 16 Alignment_Delay: 1 TT_Eta_Magn: 17 Alignment_Delay: 1 TT_Eta_Magn: 18 Alignment_Delay: 1 TT_Eta_Magn: 19 Alignment_Delay: 1 TT_Eta_Magn: 20 Alignment_Delay: 1 TT_Eta_Sign: $TT_Eta_Neg ! North TT_Phi: 1 To_TT_Phi: 32 TT_Eta_Magn: 1 Alignment_Delay: 3 TT_Eta_Magn: 2 Alignment_Delay: 3 TT_Eta_Magn: 3 Alignment_Delay: 3 TT_Eta_Magn: 4 Alignment_Delay: 3 TT_Eta_Magn: 5 Alignment_Delay: 3 TT_Eta_Magn: 6 Alignment_Delay: 3 TT_Eta_Magn: 7 Alignment_Delay: 3 TT_Eta_Magn: 8 Alignment_Delay: 3 TT_Eta_Magn: 9 Alignment_Delay: 3 TT_Eta_Magn: 10 Alignment_Delay: 3 TT_Eta_Magn: 11 Alignment_Delay: 3 TT_Eta_Magn: 12 Alignment_Delay: 3 TT_Eta_Magn: 13 Alignment_Delay: 3 TT_Eta_Magn: 14 Alignment_Delay: 3 TT_Eta_Magn: 15 Alignment_Delay: 3 TT_Eta_Magn: 16 Alignment_Delay: 3 TT_Eta_Magn: 17 Alignment_Delay: 3 TT_Eta_Magn: 18 Alignment_Delay: 3 TT_Eta_Magn: 19 Alignment_Delay: 3 TT_Eta_Magn: 20 Alignment_Delay: 3 !--------------------------- ! Define HD Trigger Tower Alignment Delay !--------------------------- TT_Channel: $TT_HD_Channel TT_Eta_Sign: $TT_Eta_Pos ! South TT_Phi: 1 To_TT_Phi: 32 TT_Eta_Magn: 1 Alignment_Delay: 2 TT_Eta_Magn: 2 Alignment_Delay: 2 TT_Eta_Magn: 3 Alignment_Delay: 2 TT_Eta_Magn: 4 Alignment_Delay: 2 TT_Eta_Magn: 5 Alignment_Delay: 2 TT_Eta_Magn: 6 Alignment_Delay: 2 TT_Eta_Magn: 7 Alignment_Delay: 2 TT_Eta_Magn: 8 Alignment_Delay: 2 TT_Eta_Magn: 9 Alignment_Delay: 2 TT_Eta_Magn: 10 Alignment_Delay: 2 TT_Eta_Magn: 11 Alignment_Delay: 2 TT_Eta_Magn: 12 Alignment_Delay: 2 TT_Eta_Magn: 13 Alignment_Delay: 2 TT_Eta_Magn: 14 Alignment_Delay: 2 TT_Eta_Magn: 15 Alignment_Delay: 2 TT_Eta_Magn: 16 Alignment_Delay: 2 TT_Eta_Magn: 17 Alignment_Delay: 2 TT_Eta_Magn: 18 Alignment_Delay: 2 TT_Eta_Magn: 19 Alignment_Delay: 2 TT_Eta_Magn: 20 Alignment_Delay: 2 TT_Eta_Sign: $TT_Eta_Neg ! North TT_Phi: 1 To_TT_Phi: 32 TT_Eta_Magn: 1 Alignment_Delay: 2 TT_Eta_Magn: 2 Alignment_Delay: 2 TT_Eta_Magn: 3 Alignment_Delay: 2 TT_Eta_Magn: 4 Alignment_Delay: 2 TT_Eta_Magn: 5 Alignment_Delay: 2 TT_Eta_Magn: 6 Alignment_Delay: 2 TT_Eta_Magn: 7 Alignment_Delay: 4 TT_Eta_Magn: 8 Alignment_Delay: 4 TT_Eta_Magn: 9 Alignment_Delay: 4 TT_Eta_Magn: 10 Alignment_Delay: 4 TT_Eta_Magn: 11 Alignment_Delay: 4 TT_Eta_Magn: 12 Alignment_Delay: 4 TT_Eta_Magn: 13 Alignment_Delay: 4 TT_Eta_Magn: 14 Alignment_Delay: 4 TT_Eta_Magn: 15 Alignment_Delay: 4 TT_Eta_Magn: 16 Alignment_Delay: 4 TT_Eta_Magn: 17 Alignment_Delay: 4 TT_Eta_Magn: 18 Alignment_Delay: 4 TT_Eta_Magn: 19 Alignment_Delay: 4 TT_Eta_Magn: 20 Alignment_Delay: 4 ========================================================================= ========================================================================= =========================================================================