ADF-2 Routing Notes ------------------------ Original Rev. 20-JULY-2004 Current Rev. 5-OCT-2004 This file is the technical notes about the routing of the ADF-2 circuit board. ADF-2 Routing: 21-JULY-04 change the size of the Analog-ADC unit cell to: X = 28.0 mm Y = 27.0 mm Trace widths that will be used: Between Comp Via's within BGA 5 mil 0.13 mm BGA pad to BGA via traces: 6 mil 0.15 mm Narrowest Routing traces: 6 mil 0.15 mm Signal traces to TQFP IC's: 8 mil 0.20 mm e.g. Chan Link Ground Power to TQFP IC's: 10 mil 0.25 mm e.g. Chan Link Analog Routing traces: 10 mil 0.25 mm Ground Power traces to tssop IC's: 10 mil 0.25 mm Ground Power traces to SQFP IC's: 12 mil 0.30 mm e.g. ADC Ground Power traces to msop IC's: 16 mil 0.35 mm e.g. Diff Amp Ground Power traces to 0603 caps: 20 mil 0.50 mm Ground Power traces to Case A caps: 30 mil 0.75 mm Ground Power traces to Power Comps 47 mil 1.20 mm e.g. big cap's Standard Routing Via: name: via_mm65 Drill Hole size: 12 mil 0.30 mm Land diameter: 26 mil 0.65 mm Plane to via relief: 39 mil 1.00 mm Tented via, no opening in the Solder_Mask. Full description of the VIA's and Terminals and Pad_Stacks is near the end of this file. Special Mentor Layers Used: Reference Designators not printed on Silkscreen: BREAKOUT may change to DRAWING Cuts in the GROUND Plane PCB Stackup Layers #3 & #10: DAM_1 Cuts in the PCB Stackup Layers #4 Plane: DAM_2 Slice: VCC_LOGIC, VCC_INT, VCC_ANALOG, VME_5V Moat: VCC_PLL Cuts in the PCB Stackupl Layers #9 Plane: DAM_3 Slice: VDD_LOGIC, VDD_ANALOG, VME_3V3 Project ID Label on all Films: DRAWING_1 Placement Grid: 0.10 mm The assignments of the plane net names to the Plane Logic Layers are: Mentor Plane Net Name Logical Layer ---------- ------------- GROUND POWER_1 VCC_LOGIC POWER_2 VCCINT POWER_3 VCC_ANALOG POWER_4 VME_5V POWER_5 VDD_LOGIC POWER_6 VDD_ANALOG POWER_7 VME_3V3 POWER_8 The assignment of Mentor Physical Layers to Mentor Logical Layers is: Mentor Physical Mentor Plane Layer Logical Layer Net Name -------- ------------- ---------- 1 SIGNAL_1 2 SIGNAL_2 3 POWER_1 GROUND 4 POWER_2 VCC_LOGIC 5 POWER_3 VCCINT 6 POWER_4 VCC_ANALOG 7 POWER_5 VME_5V 8 SIGNAL_3 9 SIGNAL_4 10 SIGNAL_5 11 SIGNAL_6 12 POWER_6 VDD_LOGIC 13 POWER_7 VDD_ANALOG 14 POWER_8 VME_3V3 15 SIGNAL_7 16 SIGNAL_8 Stackup of the manufactured circuit board: PCB Layer #1 Trace Layer #1 SIGNAL_1 and PAD_1 PCB Layer #2 Trace Layer #2 SIGNAL_2 and VEE_ANALOG PCB Layer #3 Plane #1 POWER_1 net GROUND PCB Layer #4 Plane #2 POWER_2 net VCC_LOGIC POWER_3 net VCCINT POWER_4 net VCC_ANALOG POWER_5 net VME_5V PCB Layer #5 Trace Layer #3 SIGNAL_3 PCB Layer #6 Trace Layer #4 SIGNAL_4 PCB Layer #7 Trace Layer #5 SIGNAL_5 PCB Layer #8 Trace Layer #6 SIGNAL_6 PCB Layer #9 Plane #3 POWER_6 net VDD_LOGIC POWER_7 net VDD_ANALOG POWER_8 net VME_3V3 PCB Layer #10 Plane #4 POWER_1 net GROUND PCB Layer #11 Trace Layer #7 SIGNAL_7 PCB Layer #12 Trace Layer #8 SIGNAL_8 and PAD_2 The VEE_ANALOG plane is an Area Fill on layer Signal_2. Layout of the Analog ADC Section of the ADF-2 |_________________________ | | | |- | | | | | | | | | | | | P1 | | | Front | FPGA |_| Panel | ____________ | | / \ | | F1 F0 |- | | | | | | P0 | Ch12 Ch08 Ch04 Ch00 |_| | U601 U401 U201 U1 | | | | Ch13 Ch09 Ch05 Ch01 |- | U651 U451 U251 U51 | | | | | | Ch14 Ch10 Ch06 Ch02 | | | U701 U501 U301 U101 | | P2 | | | | Ch15 Ch11 Ch07 Ch03 |_| | U751 U551 U351 U151 | |_________________________| | What different types of signals need to be routed in the Analog ADC section and what are the constraints on each type of signals. First just list the signal types, and then describe each signal type and its constraints. List of the Signal Types: Analog Unit Cell Routing ADC output to FPGA input signals ADC Clock lines ADC Enable Signal Pedestal Analog control lines Pedestal DAC digital control lines BLS input signal lines VEE_ANALOG power distribution Descripton of each Signal Type; Analog Unit Cell Routing 95% of this is on the Top and Bottom signal layers. The one trace that does not fit on Top or Bottom should be routed on a good quiet layer, e.g. next to the GROUND plane, e.g. Signal_2 or Signal_7. This trace is under the Differential Amp section, not under the ADC section. Route this on Signal_2. ADC output to FPGA input signals All 8 signal layers are needed to carry the ADC output up to the Data Path FPGA's. There is a lot of flexibility about which layer is used for what. There are also many constraints: - Use the same setup of layers in all 4 columns of the analog unit cells. - The TOP and BOTTOM layers can not, in general, be used to run the long vertical ADC output to FPGA input traces because these paths are blocked by traces and components that are within, part of, the Analog ADC Unit Cell itself. o. The only possible use of the BOTTOM layer is for connecting the Channel 0 (4,8,12) EM ADC output to the FPGA input. o. By far the most practical use of the TOP layer is for connecting the Channel 0 (4,8,12) HD ADC output to the FPGA input. --> Channel 0 (4,8,12) HD FPGA input pads should be direct in without vias in the BGA456 Component Geometry. o. It is probably possible to use the TOP layer for connecting the Channel 1 (5,9,13) HD ADC output to the FPGA input. o. The ADC output to FPGA input trace routing for the top row of Analog ADC Unit Cells (which uses the TOP and BOTTOM pcb layers) will need to be different from the ADC output to FPGA input routing for the other 3 rows of Analog ADC Unit Cells. - The best use of the Next to Top layer and Next to Bottom layer is for routing the Channel 1 ADC outputs to the FPGA. This is choice minimizes the number of Analog ADC Unit Cells that these un-shielded (they are not below a Ground Plane) digital signals run under. I don't think that the assignment of Channel 1 EM or HD to the Next to Top or to the Next to Bottom layer makes any significant difference. - Given these constraints the most rational layout of ADC output to FPGA input traces is: ADC Output to Route on FPGA Input Traces Logical Layer ----------------- ---------------- Channel 0 EM Signal_8 BOTTOM Channel 0 HD Signal_3 Channel 1 EM Signal_4 Channel 1 HD Signal_1 TOP Channel 2 EM Signal_5 Channel 2 HD Signal_6 Channel 3 EM Signal_2 Channel 3 HD Signal_7 See ADC Output Layers Sketch #7 below. - The EM output from Channel 0 (4,8,12) will come to the TOP layer soon after these traces get above the Analog ADC Section and then use the direct in paths to the FPGA's. The intent of this is to free up the layer that Channel 0 EM started out on so that it may be used for local routing of signal traces around the FPGA, e.g. ADC Clock lines. Thus, above the Analog ADC Section, Signal_8 the BOTTOM layer is not used for ADC Output to FPGA Input traces and is free for local routing around the FPGA. Note that this hopefully will also free up some space on Signal_8 the BOTTOM layer close to the Data Path FPGAs for power supply ByPass capacitors. ADC Clock lines The ADC Clock lines to a given Unit Cell will use the same layers as are used for the ADC output lines from that unit cell. The ADC Clock lines are to the right hand side of the ADC output lines. For some of the ADC Clock outputs from the Data Path FPGA this is their natural location. For the ADC Clock outputs that come from the left hand side of the FPGA these signals cross over to there required location right after the series resistor using layer Signal_8. See the topic above. ADC Enable Signal This signal comes from the Board Control PAL and runs to all 16 ADC chips on the card. The trace for this signal runs down each column of unit cells just to the right of the ADC Clock lines. This trace runs on the layer that is used for the Channel 3 (7,11,15) HD ADC output lines, i.e. layer Signal_7. These vertical column traces are collected together by a horizontal trace that runs just above the Analog ADC Section. This horizontal trace is on layer Signal_8. Pedestal Analog control lines These need to be routed on a quiet analog layer, e.g. next to a Ground plane. They run the full vertical height of the analog section of the card from the Pedestal DAC section at the very bottom up to the top of the top row of the Analog ADC section unit cells. These traces will run under the Differential Amp section, i.e. not in the ADC section. Most of the Pedestal Analog control lines will run on Layer Signal_7. For the bottom row of Analog Unit Cells we can also use layers Signal_1 and Signal_8 to run the Pedestal Analog control lines. Pedestal DAC digital control lines There are 4 digital lines that control the Pedestal DAC's. They are: serial data in/out chip select and serial data clock. During all normal operation these lines are quiescent and thus make no electrical noise. These 4 lines run from the Board Control PAL down to the Pedestal DAC section at the very bottom of the ADF-2 card. The assumption is that these lines will run down the very front of the card and will use any convenient layers (nothing else is routed right along this section of the front of the card). Care should be taken with the DAC Serial Clock line and the DAC Select line to make certain that they can not pick up noise. BLS input signal lines This should be handled as a differential pair of signals. We must not let in any normal mode noise at this point. These traces need to be routed on a pair of quiet analog layers, e.g. next to a Ground plane. May also need to route as a pair of traces next to each other on the same layer (a quiet layer next to a Ground plane). These traces run from the RC components located to the right of the Analog ADC section the whole way across the Analog ADC section to the right hand side of the left hand column of unit cells. The layers that are available and reach the whole way across the card depend on what row of Analog Unit Cells you are looking at. This is shown in the ascii sketches in the next section. In summary, the BLS input signal run on Layers: pairs on Signal_3 Signal_4 rows Ch #1, #2, #3 pairs on Signal_5 row Ch #2 pairs on Signal_5 Signal_6 row Ch #3 The relative merits of over/under vs side/side routing in this is application is still being studied. The TOP and BOTTOM layers Signal_1 and Signal_8 may also be used to connect the BLS input signals to the right hand column of Analog Unit Cells (the column next to the area of BLS input RC components). The BLS input signal traces are launched and landed in order so there should be no need for any criss crossing. VEE_ANALOG power distribution VEE_ANALOG is carried on a plane that is an area fill in one of the Signal layers. This area fill must share the Signal layer with a set of ADC output lines. This area fill will be vertical fingers that run under the Differential Amp section of each of the 4 columns of Analog ADC unit cells. Under at least the bottom row of Analog ADC unit cells this area fill will span the full width of the Analog ADC section and reach under the VEE_ANALOG input filter components that are next to the P2 connector. This area fill will be on layer Signal_2. This could/should also be the layer that is used to bring the VME_N12V to the VEE_ANALOG input filter. Signal_2 is next to a Ground plane. Setting up the area will require matching Design Rules. In the Analog ADC Section and in connecting the ADC output to the Data Path FPGAs what the routing layers are used for what. SIGNAL_1: Ch #1 HD ADC Output, Top surface traces in the Analog Unit Cells, above the Analog ADC Section also carries Ch #0 EM ADC Output, Top surface direct access to FPGA pads for Ch #1 HD and for Ch #0 EM. SIGNAL_2: Ch #3 EM ADC Output, VEE_ANALOG Area Fill SIGNAL_3: Ch #0 HD ADC Output, BLS Input Signal routing SIGNAL_4: Ch #1 EM ADC Output, BLS Input Signal routing SIGNAL_5: Ch #2 EM ADC Output, BLS Input Signal routing SIGNAL_6: Ch #2 HD ADC Output, BLS Input Signal routing SIGNAL_7: Ch #3 HD ADC Output, Pedestal Analog control lines, trace in the Diff Amp section of the Analog Unit Cells, ADC Enable signal (vertical in the Unit Cells), Complement signals from backplane connector to the BLS RC's. SIGNAL_8: Ch #0 EM ADC Output, local routing (mostly horizontal) above the Analog ADC Section, Direct signals from backplane connector to the BLS RC's. =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- Design Sketches The Whole 9 Yards about ADC Output Traces vs PCB Layers ---------------------------------------------------------- ADC Output Layers Sketch #1 South North +-------------------O Signal 1 Top +-----+-------------------o Signal 2 ======================================================== Planes +----------+-----+-------------------o Signal 3 +----+----------+-----+-------------------o Signal 4 +-----+----+----------+-----+-------------------o Signal 5 +----+-----+----+----------+-----+-------------------o Signal 6 ======================================================== Planes | | | | +----+-----+-------------------o Signal 7 | | | | | | | +--------------o Signal 8 Bottom | | | | | | | | -- -- -- -- -- -- -- -- ---- HD EM HD EM HD EM HD EM FPGA ------- ------- ------- ------- Ch #3 Ch #2 Ch #1 Ch #0 South of Ch #0 EM: surface layer --> side/side pairs between cells South of Ch #0 HD: surface layer --> side/side pairs between cells South of Ch #1 EM: internal layer --> side/side pairs o/u btwn cells South of Ch #1 HD: internal layer --> side/side pairs o/u btwn cells South of Ch #2 EM: internal layer --> side/side pairs South of Ch #2 HD: internal layer --> over/under pairs ADC Output Layers Sketch #2 South North +-------------------O Signal 1 Top +-----+-------------------o Signal 2 ======================================================== Planes +----+-----+-------------------o Signal 3 +-----+----+-----+-------------------o Signal 4 +----+-----+----+-----+-------------------o Signal 5 +-----+----+-----+----+-----+-------------------o Signal 6 ======================================================== Planes +----+-----+----+-----+----+-----+-------------------o Signal 7 | | | | | | | +--------------o Signal 8 Bottom | | | | | | | | -- -- -- -- -- -- -- -- ---- HD EM HD EM HD EM HD EM FPGA ------- ------- ------- ------- Ch #3 Ch #2 Ch #1 Ch #0 South of Ch #0 EM: surface layer --> side/side pairs between cells South of Ch #0 HD: surface layer --> side/side pairs between cells South of Ch #1 EM: internal layer --> side/side pairs o/u btwn cells South of Ch #1 HD: internal layer --> side/side pairs South of Ch #2 EM: internal layer --> over/under pairs South of Ch #2 HD: internal layer --> over/under pairs ADC Output Layers Sketch #3 South North +-------------------O Signal 1 Top +----------------+-------------------o Signal 2 ======================================================== Planes | +-----+-------------------o Signal 3 | +----+-----+-------------------o Signal 4 +----------+-----+----+-----+-------------------o Signal 5 +----+----------+-----+----+-----+-------------------o Signal 6 ======================================================== Planes | | +----+-----+----+-----+-------------------o Signal 7 | | | | | | | +--------------o Signal 8 Bottom | | | | | | | | -- -- -- -- -- -- -- -- ---- HD EM HD EM HD EM HD EM FPGA ------- ------- ------- ------- Ch #3 Ch #2 Ch #1 Ch #0 South of Ch #0 EM: surface layer --> side/side pairs between cells South of Ch #0 HD: surface layer --> side/side pairs between cells South of Ch #1 EM: internal layer --> side/side pairs South of Ch #1 HD: internal layer --> over/under pairs South of Ch #2 EM: internal layer --> side/side pairs o/u btwn cells South of Ch #2 HD: internal layer --> side/side pairs o/u btwn cells ADC Output Layers Sketch #4 South North +-------------------O Signal 1 Top +---------------------------+-------------------o Signal 2 ======================================================== Planes | +-----+-------------------o Signal 3 | +----+-----+-------------------o Signal 4 | +-----+----+-----+-------------------o Signal 5 | +----+-----+----+-----+-------------------o Signal 6 ======================================================== Planes +----+-----+----+-----+----+-----+-------------------o Signal 7 | | | | | | | +--------------o Signal 8 Bottom | | | | | | | | -- -- -- -- -- -- -- -- ---- HD EM HD EM HD EM HD EM FPGA ------- ------- ------- ------- Ch #3 Ch #2 Ch #1 Ch #0 South of Ch #0 EM: surface layer --> side/side pairs between cells South of Ch #0 HD: surface layer --> side/side pairs between cells South of Ch #1 EM: internal layer --> side/side pairs South of Ch #1 HD: internal layer --> over/under pairs South of Ch #2 EM: internal layer --> side/side pairs South of Ch #2 HD: internal layer --> over/under pairs ADC Output Layers Sketch #5 South North +------------------------------O Signal 1 Top +-----+------------------------------o Signal 2 ======================================================== Planes | | +-------------------o Signal 3 | | +-----+-------------------o Signal 4 +----------+-----+----+-----+-------------------o Signal 5 +----+----------+-----+----+-----+-------------------o Signal 6 ======================================================== Planes | | +----+-----+----+-----+-------------------o Signal 7 | | | | | | | +--------------o Signal 8 Bottom | | | | | | | | -- -- -- -- -- -- -- -- ---- HD EM HD EM HD EM HD EM FPGA ------- ------- ------- ------- Ch #3 Ch #2 Ch #1 Ch #0 South of Ch #0 EM: surface layer --> side/side pairs between cells South of Ch #0 HD: internal layer --> side/side pairs South of Ch #1 EM: internal layer --> over/under pairs South of Ch #1 HD: surface layer --> side/side pairs between cells South of Ch #2 EM: internal layer --> side/side pairs o/u btwn cells South of Ch #2 HD: internal layer --> side/side pairs o/u btwn cells ADC Output Layers Sketch #6 South North +------------------------------O Signal 1 Top +----------------+------------------------------o Signal 2 ======================================================== Planes | | +-------------------o Signal 3 | | +-----+-------------------o Signal 4 | +-----+----+-----+-------------------o Signal 5 | +----+-----+----+-----+-------------------o Signal 6 ======================================================== Planes +----+-----+----+-----+----+-----+-------------------o Signal 7 | | | | | | | +--------------o Signal 8 Bottom | | | | | | | | -- -- -- -- -- -- -- -- ---- HD EM HD EM HD EM HD EM FPGA ------- ------- ------- ------- Ch #3 Ch #2 Ch #1 Ch #0 South of Ch #0 EM: surface layer --> side/side pairs between cells South of Ch #0 HD: internal layer --> side/side pairs South of Ch #1 EM: internal layer --> over/under pairs South of Ch #1 HD: surface layer --> side/side pairs between cells South of Ch #2 EM: internal layer --> side/side pairs South of Ch #2 HD: internal layer --> over/under pairs ADC Output Layers Sketch #7 ADF-2 is built this way. South North +------------------------------O Signal 1 Top +----------------+------------------------------o Signal 2 ======================================================== Planes | | +-------------------o Signal 3 | | +-----+-------------------o Signal 4 | +-----+----+-----+-------------------o Signal 5 | +----+-----+----+-----+-------------------o Signal 6 ======================================================== Planes +----+-----+----+-----+----+-----+-------------------o Signal 7 | | | | | | | +--------------o Signal 8 Bottom | | | | | | | | -- -- -- -- -- -- -- -- ---- HD EM HD EM HD EM HD EM FPGA ------- ------- ------- ------- Ch #3 Ch #2 Ch #1 Ch #0 South of Ch #0 EM: surface layer --> side/side pairs between cells South of Ch #0 HD: internal layer --> side/side pairs South of Ch #1 EM: internal layer --> over/under pairs South of Ch #1 HD: surface layer --> side/side pairs between cells South of Ch #2 EM: internal layer --> side/side pairs South of Ch #2 HD: internal layer --> over/under pairs =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- BLS Signal Input RC Component Placement, Nets, and Routing ------------------------------------------------------------ - Want the C's on the top surface of the card. (They are tall.) - Vertical spacing between the rows of RC is big enough that you have space for 1 via per row. That will end up with a little more than 1/2 of the copper in the planes still intact. row to row vertical space between 2 RC in a pair: 2.2 mm row to row vertical space between pairs of RC: 2.6 mm - Will need a via at all inputs to the RC's. - Could use Signal_8 to bring traces from the backplane connector to the input of the BLS RC's. But on the surface it is harder for the RC input traces to reach both the right hand RC column and the left hand RC column all on a single layer. These traces must run under the Analog Power Input Filter Components. As currently setup Signal_7 carries the VEE_ANALOG power on an area fill. Could move the VEE_ANALOG power to an area fill on layer Signal_2. It would be nice to run the backplane connector to BLS RC input traces on Signal_7 and then area fill Signal_8 with GND to fully shield these traces. The Analog Power Input Filters will have a significant number of via's and the backplane connector to BLS RC input traces will need to route around these. - You are forced to use 2 layers for the input trace layers for a number of reasons: Routing on a single layer would result in escaping the backplane connector with the traces mixed EM and HD, e.g. EM+ HD+ EM- HD-. Routing on a single layer would make it hard to find enough space to place the large required number of via's in the Analog Power Filter area. - So this forces use of 2 layers to connect the backplane connector to the BLS RC components. And that forces Over/Under pairing. - What layers to use for the backplane connector to BLS RC component traces ? Can not use any of the GND or Power Plane layers. Can not use the layer that has the Area Fill for VEE_ANALOG. Can not use the Top surface layer (need to get under the Analog Power Input Filters. It would be best not to use a layer that is used to run traces from the BLS RC components over to the Unit Cell BLS inputs. Using different layers to enter and escape gives the maximum flexibility in how the output traces are organized. That leaves Signal_7 and Signal_8 for the backplane connector to BLS RC traces. Put the Complement signals on Signal_7 and the Direct signals on Signal_8 This requires moving VEE_ANALOG area fill to Signal_2. - Will need a via at most outputs of the C's for the traces running over to the Unit Cell BLS Signal inputs. - A few of the C output to Unit Cell inputs could run on the Top surface layer without via's or on the bottom surface layer with the use of via's. - Will need some via's to connect the GND end of the 1 Meg Ohm R's to the GND Plane. - Could use bottom surface trace to bus the GND end of the 1 Meg Ohm R's together and then connect to GND at only a few points. There is zero current in this circuit and they should not talk to each other. - For the lower 1/2 of the left hand column (where there is lots of room for routing) the GND's from the 1 Meg Ohm resistors could run to the bottom surface layer GND traces in the right hand column of Unit Cells. - On the Top Surface layer there is not enough vertical space between capacitor pads of adjacent capacitor pairs to run 2 traces but there is enough space to run a single trace. Between the capacitor pads within a pair there is not enough vertical space on the Top layer to run a trace. - On the Bottom layer with the smaller resistor pads there is enough vertical space between resistor pads of adjacent resistor pairs to run 2 traces. Between resistor pads within a pair there is enough space to run 1 trace. - The arrangement of components in the columns could be: EM+ Ch #N EM- Ch #N HD+ Ch #N HD- Ch #N EM+ Ch #N+1 EM- Ch #N+1 HD+ Ch #N +1 HD- Ch #N+1 or it could be: EM+ Ch #N HD+ Ch #N EM- Ch #N HD- Ch #N EM+ Ch #N+1 HD+ Ch #N+1 EM- Ch #N +1 HD- Ch #N+1 The lower pattern keeps things tighter in differential pairs but: it is slightly less flexible in how you escape and it has a significantly harder problem of connecting the GND end of the resistors. There is only an issue at the very top end of the columns. Thus go with the tighter differential pairing and force some solution for the DC GND's at the top of the columns. - The actual BLS signal inputs on the right hand edge of the Unit Cells have the Complement signal on top and the Direct signal at a lower value of "Y". =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- Pedestal DAC Analog Pedestal Control Signals Runs Up Into the Unit Cells ------------------------------------------------------------------------ - Most of the Analog Pedestal Control Signal traces run on layer Signal_7. - A few of the Analog Pedestal Control Signal traces, the ones that go to the bottom row of Unit Cells, could run on the Top or Bottom Surface layers of the card. - The output from the Pedestal DAC Section is setup so that all the Analog Pedestal Control traces will be in order if: the traces to the bottom row of Unit Cells are routed to the right of the Unit Cell BLS signal input via's and the traces to the upper 3 rows are routed to the left of the Unit Cell BLS signal input via's. - There is enough space to the left of the BLS signal input via's to run at least 6 traces for these Analog Pedestal Control signals. =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- BGA_456 Geometry ---------------- - The orientation of this geometry is with "pin #1" in the South-East corner, i.e. the same as it appears on the ADF-2 card. - For all details about pad size and such, follow the Xilinx Board Routing Guidelines (e.g. page 388:395 of the Virtex-ii Platform FPGA Users Guide). Exceptions to this: Pad to Via Distance "D" is set to 0.7071 mm (1/2 sqrt 2) instead of the Xilinx 0.700 mm. This puts the via exactly in the center of a square of bga pads and thus keeps everything on grid. The Xilinx value for "D" has the via 0.0071 mm (i.e. 0.0003") away from the center. Tie Width "W" is set to 0.15 mm instead of 0.13 mm. I.E. it is set to 5.9 mil instead of 5.1 mil This matches a standard plot aperture. Thus the overall effect is that the tie is about 4% longer and 16% wider. - The general layout of bga pads and via's will be as shown on page 394. - Want a clean way to edit the geometry to control which bga pads use direct in top surface traces and which bga pads have associated via's built into the geometry. =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- Data Path FPGA to 3x Channel Link Chips Trace Routing ------------------------------------------------------ FPGA "F0" U801 to Channel Link Traces as the Route over the top ---- ---- Trace order Top-to-Bottom Connection to WEST side of U801 Route on Layer: EM and HD Et are on Signal_6 Reserved are on Signal_5 U801-M21 HD Chan #7 Et Serial Output U801-N21 EM Chan #7 Et Serial Output U801-P21 HD Chan #6 Et Serial Output U801-R21 EM Chan #6 Et Serial Output U801-R20 Rsrvd Serial F0>(2) U801-T21 HD Chan #5 Et Serial Output U801-T20 Rsrvd Serial F0>(1) U801-U21 EM Chan #5 Et Serial Output U801-V21 HD Chan #4 Et Serial Output U801-V20 Rsrvd Serial F0>(0) U801-W21 EM Chan #4 Et Serial Output U801-W20 Rsrvd Serial F0(3) Trace order Top-to-Bottom Connection to EAST side of U801 Route on Layers: Signal_5 and Signal_6 U801-W2 HD Chan #3 Et Serial Output # on Signal_6 U801-V3 Serial Parity F0 # on Signal_5 U801-V2 EM Chan #3 Et Serial Output # on Signal_6 U801-U3 Serial Frame F0 # on Signal_5 U801-U2 HD Chan #2 Et Serial Output # on Signal_6 U801-T3 Serial BX Count F0 # on Signal_5 U801-T2 EM Chan #2 Et Serial Output # on Signal_5 U801-R2 HD Chan #1 Et Serial Output # on Signal_5 U801-P2 EM Chan #1 Et Serial Output # on Signal_5 U801-N2 HD Chan #0 Et Serial Output # on Signal_5 U801-M2 EM Chan #0 Et Serial Output # on Signal_5 FPGA "F1" U901 to Channel Link Traces as the Route over the top ---- ---- Trace order Top-to-Bottom Connection to WEST side of U901 Route on Layer Signal_4 U901-M21 HD Chan #15 Et Serial Output U901-N21 EM Chan #15 Et Serial Output U901-P21 HD Chan #14 Et Serial Output U901-R21 EM Chan #14 Et Serial Output U901-R20 Rsrvd Serial F1>(2) U901-T21 HD Chan #13 Et Serial Output U901-T20 Rsrvd Serial F1>(1) U901-U21 EM Chan #13 Et Serial Output U901-V21 HD Chan #12 Et Serial Output U901-V20 Rsrvd Serial F1>(0) U901-W21 EM Chan #12 Et Serial Output Trace order Top-to-Bottom Connection to EAST side of U901 Route on Layer Signal_3 U901-W2 HD Chan #11 Et Serial Output U901-V2 EM Chan #11 Et Serial Output U901-U2 HD Chan #10 Et Serial Output U901-T2 EM Chan #10 Et Serial Output U901-R2 HD Chan #9 Et Serial Output U901-P2 EM Chan #9 Et Serial Output U901-N2 HD Chan #8 Et Serial Output U901-M2 EM Chan #8 Et Serial Output =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- VIA's and Terminals and Pad_Stacks ---------------------------------- Standard Routing Via: name: via_mm65 Drill Hole size: 12 mil 0.30 mm Land diameter: 26 mil 0.65 mm Plane to via relief: 39 mil 1.00 mm Tented via, no opening in the Solder_Mask. Terminal used as Via in the BGA_456 Component: name: TERM_0_3_MM Drill Hole size: 12 mil 0.30 mm Land diameter: 24 mil 0.61 mm Plane to via relief: 33 mil 0.85 mm Tented via, no opening in the Solder_Mask. Terminal used in the P0 hard metric connector and as the power routing via via_0_6_mm and as the component wrap_0_6_mm : name: TERM_0_6_MM Drill Hole size (finished): 24 mil 0.60 mm Land diameter: 43 mil 1.10 mm Plane to via relief: 65 mil 1.65 mm Solder Mask Opening diameter: 43 mil 1.10 mm Terminal used in the P1 & P2 connectors: name: TERM_hart_vme Drill Hole size (finished): 39 mil 1.00 mm Land diameter: 61 mil 1.55 mm Plane to via relief: 85 mil 2.15 mm Solder Mask Opening diameter: 61 mil 1.55 mm Recall wire wrap wire approximate diameter: 26 AWG Copper diameter: 16 mil 0.40 mm 28 AWG Copper diameter: 13 mil 0.33 mm 30 AWG Copper diameter: 10 mil 0.25 mm =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- Clearance vs Spacing -------------------- Trace Between BGA Component Via's --------------------------------- Via Pad is 0.61 mm Via spacing is 1.00 mm Trace Width is 0.13 mm --> Trace to Pad Clearance is 0.13 mm Diagonal Bus Runs (assume 0.15 mm Trace) ----------------- Stagger at the Bend ------------------------------------- Parallel CTC 0 1 2 3 4 ------------ ----- ----- ----- ----- ----- 0.4 mm - 0.204 0.274 0.345 0.416 mm clearance 0.5 mm 0.204 0.274 0.345 0.416 - mm clearance Clearance between traces in a parallel run CTC of 0.4 mm is 0.25 mm. Approach to Pads (assume 0.15 mm Trace) ---------------- Approach 0.60 mm Pad 0.65 mm Pad --------------- ----------- ----------- Parallel @ 0.80 0.425 mm 0.400 mm clearance Parallel @ 0.70 0.325 mm 0.300 mm clearance Parallel @ 0.60 0.225 mm 0.200 mm clearance Diag 0.7 x 0.7 0.615 mm 0.590 mm clearance Diag 0.7 x 0.6 0.547 mm 0.522 mm clearance Diag 0.7 x 0.5 0.485 mm 0.460 mm clearance Diag 0.7 x 0.4 0.431 mm 0.406 mm clearance Diag 0.7 x 0.3 0.387 mm 0.362 mm clearance Diag 0.8 x 0.7 0.688 mm 0.663 mm clearance Diag 0.8 x 0.6 0.625 mm 0.600 mm clearance Diag 0.8 x 0.5 0.568 mm 0.543 mm clearance Diag 0.8 x 0.4 0.519 mm 0.494 mm clearance Diag 0.8 x 0.3 0.479 mm 0.454 mm clearance =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- Below here is old background material. Some information below here may no longer be correct. Review what has been done: ------------------------------------------------------------------ From Denis 30-JAN-2004 ADF Rev #1 The design rules follow "Class 6" - maybe there is a precise standard for that; but what was used is: minimum trace to trace spacing = 0.12 mm minimum trace to pad spacing = 0.12 mm minimum pad to pad spacing = 0.12 mm but we always put more so that mounting components is possible pad diameter of your small via's = 0.7 mm for top layer 0.81 mm on the bottom layer 0.64 mm on internal layers hole diameter of your small via's = 0.3 mm minimum via to via spacing = 0.12 mm ------------------------------------------------------------------ Multek 2004 minimum line width: 4 mil 0.10 mm minimum line spacing: 4 mil 0.10 mm minimum via size: 10 mil 0.25 mm ------------------------------------------------------------------ Multek 1996 minimum drilled hole size: 8 mil 0.20 mm minimum finished hole size: 4 mil 0.10 mm minimum via land size: 12 mil 0.30 mm minimum via relief: 22 mil 0.56 mm minimum line width: 2 mil 0.05 mm minimum line spacing: 2 mil 0.05 mm minimum line to via spacing: 3 mil 0.08 mm ------------------------------------------------------------------ Advanced Circuits minimum line width: 5 mil 0.13 mm minimum line spacing: 5 mil 0.13 mm minimum finished hole size: 10 mil 0.25 mm ------------------------------------------------------------------ What we need for the BGA 456 layout: BGA pad to via traces: 5 mil 0.13 mm via land diameter: 24 mil 0.61 mm via hole diameter: 12 mil 0.30 mm escape lines: 5 mil 0.13 mm secape lines: 6 mil 0.15 mm ------------------------------------------------------------------ ADF-1 Sketch was done with: For now the small traces will be 7 mil. Power / Gnd traces from the differential amp are 14 mil Power / Gnd traces from the ADC are 13 mil Power / Gnd traces from the 0603 bypass capacitors are 20 mil Analog signal traces are 10 mil To work with the ADC pad layout we need to use a Trace to Pad clearance of 5.5 mils. For now the Trace to Trace clearance must also be 5.5 mils to clear these pads. ADF-1 analog unit cell sketch was done in: X = 27.5 mm Y = 25.0 mm make VIA_30 30 mil pads 12 mil hole edit the adf_1_pcb ascii geometry edit the tech.tech"N" file to change the Net Rules VIA type edit the traces.traces"N" file to change the VIA type ------------------------------------------------------------------ ADC Output to FPGA Input Traces - not current Mostly Lands ADC Num at FPGA on Pins Routed on Layer -------- ---------------------- ------------------ Ch 0 EM Row B Columns 4:11 Top Trace Layer Ch 0 HD Row C Columns 4:11 Ch 1 EM Row E Columns 6:11 Rows H:L Column 5 Ch 1 HD Row F Columns 9:11 Rows E:G Column 5 Rows J:L Column 6 Ch 2 EM Row D Columns 6:11 Ch 2 HD Rows E:L Column 4 Ch 3 EM Rows C:L Column 2 Ch 3 HD Rows E:L Column 3 Ch 4 EM Row B Columns 12:19 Top Trace Layer Ch 4 HD Row C Columns 12:18 Ch 5 EM Row E Columns 12:17 Rows H:L Column 18 Ch 5 HD Row F Columns 12:14 Rows E:G Column 18 Rows J:L Column 17 Ch 6 EM Row D Columns 12:18 Ch 6 HD Rows F:L Column 19 Ch 7 EM Rows C:L Column 21 Ch 7 HD Rows E:L Column 20