ADF-2 VME Address Space Usage Rev:4-May-04 Last Edited:02-Aug-04 *** This is a working draft *** All IO to the ADF-2 are performed using A24/D16 VME data cycles. This includes the configuration of the Data Path FPGA by downloading the firmware over the VME bus. Not all addressable registers are 16 bit wide, but all VME IOs are 16 bit wide, and the ADF-2 will ignore unsused bits during write cycles, and return zeroes (if possible) for non-existing bits during read cycles. ADF-2 VME Address Space Usage ============================= +---+---------------+---+-----------------------------------+-----------------+ | A | A A A A A | A | A A A A A A A A A A A A A A A A A | | | 2 | 2 2 2 1 1 | 1 | 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 | | | 3 | 2 1 0 9 8 | 7 | 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | | +---+---------------+---+-----------------------------------+-----------------+ | | Slot ID# 1:21 | | | | | 0 | S S S S S | 0 | 0 0 0 0 0 0 0 0 0 0 0 0 X X X X 0 |Board Control PAL| | | | | |Address Space | | | | | | | | | | | | | | | | 0 | X X X X X X X X X X X X X X X X 0 |Data Path FPGA #0| | | | | |Address Space | | | | | | | | | | 1 | 0 0 0 0 0 0 0 0 0 0 0 0 X X X X 0 |Unassigned | | | | | | | | | | | | | | | | 1 | X X X X X X X X X X X X X X X X 0 |Data Path FPGA #1| | | | | |Address Space | +---+---------------+---+-----------------------------------+-----------------+ Note that in the figure above, the Board Control PAL address space appears to overlap with the Data Path FPGA#0 address space. The address space for the Data Path FPGAs will not include the whole range as summarized in the above table, as the lower part of the range is reserved for the Board Control PAL. The Board Control PAL will use VME Address bits A18:22 along with the VME-64X Geographical Addressing pins to recognize when this particular ADF-2 Board is being addressed. The Board Control PAL will use VME Address bit A17 to determine which of the two Data Path FPGAs is being addressed, and assert the corresponding Data Path FPGA Chip Enable signal. The Board Control PAL will also need to use VME Address bits A05:17 to recognize its own reserved address space and not assert the Data Path FPGA #0 Chip Enable signal for addresses within the Board Control PAL address space. The lower 16 addresses of Data Path FPGA 1 are unassigned and the Board Control PAL will not enable any OCB device if this adress range is addressed. [16 registers for Board Control PAL is an arbitrary number for this draft] Note: Avoiding VME Address bit A23 (i.e. requiring it low) guarantees that the ADF-2 address space will not interfere with the space reserved by the Vertical Interconnect Master/Slave to access A16 address space. The base address for each card is decoded by matching the slot ID to address bits A18:22. This is also the Base Address of the Board Control PAL address space. Card Slot Card Base Address (A18:A22) --------- ------------------ 1 Slot reserved for crate controller 2 0x080000 3 0x0C0000 4 0x100000 5 0x140000 6 0x180000 7 0x1C0000 8 0x200000 9 0x240000 10 0x280000 11 0x2C0000 12 0x300000 13 0x340000 14 0x380000 15 0x3C0000 16 0x400000 17 0x440000 18 0x480000 19 0x4C0000 20 0x500000 21 0x540000 The base address for each Data Path FPGA is decoded by A17. The following table gives the Data Path FPGA Base Address Offset: FPGA # Data Path FPGA Base Address Offset (A17) --------- ---------------------------------- 0 0x000000 1 0x020000 Reminder: the usable Data Path FPGA address space does not actually start right at this base address in order to leave room for the Board Control PAL. Board Control PAL Address Space =============================== Address Offset = 0x00000000 Address Range = 0x00000000 - 0x0000001E = 16 D16 Words [16 CSR registers is an arbitrary number for this draft] e.g. firmware configuration : Enable read FPGA status 2x4 read crate status x4 write crate status x4 write Crate Signal to SCLD x2 Channel Link: DC balance, deskew ADC Enable Pedestal DAC Serial Write, Read Data Path FPGA Address Space ============================ +-------+---+---+---+---+---+---+---+---+---+---+---+---+---+---+-------------+ | A A A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | | | 1 1 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | | 6 5 4 | 3 | 2 | 1 | 0 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | | +-------+---+---+---+---+---+---+---+---+---+---+---+---+---+---+-------------+ | 0 0 0 | 0 0 0 0 0 0 0 0 0 | X X X X | 0 |Resvd for PAL| +-------+---+---+---+---+---+---+---+---+---+---+---+---+---+---+-------------+ | 0 0 0 | 0 0 0 1 0 0 0 0 0 | X X X X | 0 |FPGA Glob Reg| +-------+---+---+---+---+---+---+---+---+---+---+---+---+---+---+-------------+ |TrgTwr#| 0 0 0 1 1 0 0 0 0 | X X X X | 0 |EM Chan CSR | | 0:7 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+-------------+ | T T T | 0 0 0 1 1 1 0 0 0 | X X X X | 0 |HD Chan CSR | | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+-------------+ | | 0 0 1 | RAM Address bits 9..0 | 0 |EM&HD Et Out | | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+-------------+ | | 0 1 0 | RAM Address bits 9..0 | 0 |EM Raw ADC | | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+-------------+ | | 0 1 1 | RAM Address bits 9..0 | 0 |HD Raw ADC | | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+-------------+ | | 1 0 | RAM Address bits 10..0 | 0 |EM Et Lookup | | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+-------------+ | | 1 1 | RAM Address bits 10..0 | 0 |HD Et Lookup | +-------+---+---+---+---+---+---+---+---+---+---+---+---+---+---+-------------+ Each FPGA is responsible for 8 Trigger Towers, each Trigger Tower is a pair of one EM and one HD channel, for a total of 16 ADC input channels per FPGA. The Data Path FPGA uses VME Address bit A14:16 to determine which Trigger Tower Channel pair is being addressed. The lower 16 addresses (of D16 words) of the address space are reserved for the Board Control PAL. The Board Control PAL uses this reserved space appearing right before the address range for TrgTwr #0 of Data Path FPGA #0. [16 registers is an arbitrary number for this draft] An additional 16 addresses (of D16 words) starting at offset 0x000800 are reserved for Global Data Path FPGA Control Status Registers which are not specific to a given Trigger Tower or a given ADC channel, but instead apply to the whole FPGA. FPGA Global Registers --------------------- Address Offset = 0x00000400 Address Range = 0x00000400 - 0x0000041E = 16 D16 Words [16 CSR registers is an arbitrary number for this draft] e.g. Tick and Turn Counters Control Capture Monit Data Trigger Tower Registers ----------------------- The Base address for Each Trigger Tower is TrgTwr # Trigger Tower Base Address Offset --------- ------------------ 0 0x0000000 1 0x0004000 2 0x0008000 3 0x001C000 4 0x0010000 5 0x0014000 6 0x0018000 7 0x001C000 Reminder: the usable Trigger Tower address space does not actually start right at this base address. EM Channel Control Status Registers ----------------------------------- Address Offset = 0x00000600 Address Range = 0x00000600 - 0x0000061E = 16 D16 Words [16 CSR registers is an arbitrary number for this draft] HD Channel Control Status Registers ----------------------------------- Address Offset = 0x00000700 Address Range = 0x00000700 - 0x0000071E = 16 D16 Words [16 CSR registers is an arbitrary number for this draft] Same as above, but for HD channel of same Trigger Tower EM & HD Channel Et Output ------------------------- Address Offset = 0x00000800 Address Range = 0x00000800 - 0x00000FFE = 1k D16 Words Data Width = 16 bit Content = Circular Register holding the Final EM & HD Et Data sent to TABs Read Only = Saved Monitoring Data Lower 8 bits of each D16 word are EM Et Output of this Trigger Tower Channel Upper 8 bits of each D16 word are HD Et Output of this Trigger Tower Channel The upper 2x address bits in this 1k range identify a local Turn Number, and the lower 8x bits identify the Tick Number. This means that only 4x159 of the 4x256 addresses can hold real data. EM Raw ADC ---------- Address Offset = 0x00001000 Address Range = 0x00001000 - 0x000017FE = 1k D16 Words Data Width = 10 bit Content = Raw EM ADC data sampled at 4 time the Beam Crossing Rate Write = Test Mode only: Program Simulated Raw ADC Data Read = Normal Running Mode: Saved Monitoring Raw ADC Data Test Mode only: Verify Simulated Raw ADC Data The upper 8x address bits in this 1k range identify the Tick Number, and the lower 2x bits identify the 4 successive samples within each Beam Crossing. This means that only 159x4 of the 256x4 addresses can hold real data. HD Raw ADC ---------- Address Offset = 0x00001800 Address Range = 0x00001800 - 0x00001FFE = 1k D16 Words Data Width = 10 bit Same as above, but for HD channel of same Trigger Tower EM Et Lookup Table ------------------ Address Offset = 0x00002000 Address Range = 0x00002000 - 0x00002FFE = 2k D16 Words Data Width = 8 bit Read/Write = Final Lookup to convert EM E -> EM Et HD Et Lookup Table ------------------ Address Offset = 0x00003000 Address Range = 0x00003000 - 0x00003FFE = 2k D16 Words Data Width = 8 bit Same as above, but for HD channel of same Trigger Tower