ADF Crate BC_Clock Signal Backplane Distribution ------------------------------------------------------ Original Rev. 8-MAR-2004 Most Recent Rev. 12-MAR-2004 This file describes the distribution of the BX_Clock signal in the ADF Crate. A different circuit is used on the ADF-2 card to distribute this signal than was used on the ADF-1 prototype. Accurate low jitter distribution of the Beam Crossing Clock in the ADF Crate is important for the successful operation of the ADF cards. This clock signal is put onto the backplane bus by the ADF card in the center of the crate (the ADF card that is connected with the SCLD) and it is distributed over a VME-64x reserved bus line to the other 19 ADF cards. An accurate low jitter BX_Clk signal is important to the operation of the ADF system because: - It is the fundamental clock that supplies timing to all parts of the ADF card - It is used as the reference for PLL's that multiply the BX_Clk by 4x and 8x and eventually 48x for Channel Link serial bit rate clock. - These are not fancy narrow bandwidth narrow tracking range PLL's that will work magic and clean up ugly input reference signals. These are wide tracking range PLL's and noise on their reference input will quickly degrade their output clock quality. - We can not afford to have Channel Link problems with this system (random loss of sync and such) caused by clock jitter. - Problems with high quality BX_Clk distribution can not be fixed after the system is built. This is a question of etch not firmware. - We can not test the quality of the BX_Clk distribution with just a single ADF card. It really requires a full loaded crate to verify and measure this aspect of the ADF system. - Scope pictures of the ADF-1 backplane BX_Clk signal do not look encouraging or safe to me. - The BX_Clk signal that is received on a given ADF card must continue to be clean and jitter free even when that card is running its full digital processing and carrying out VME Bus I/O cycles. - VME Bus read cycles (the typical VME cycle used for monitoring during Physics beam running operation) will require a given ADF card to asynchronously sink 500 ma from the backplane bus to drive the 16 VME data lines. During these fast 500 ma shifts in ground current, the edges of the BX_Clk signal, as received by the ADF card, must not appear to shift in time. The ADF-1 design uses a single ended 24 ma 3.3 V CMOS FPGA output to drive the VME-64x reserved bus line that is used to carry the BX_Clk signal. This driver is "tri-stated" on all ADF cards except for the one in the center that drives the BX_Clk signal. The reserved bus line is pulled up "terminated" at each end by the equivalent of a 194 Ohm resistor to a +2.94 Volt supply. Each ADF card receives the BX_Clk signal with a 3.3V CMOS FPGA input. The characteristics of the BX_Clk signal on the bus can be seen in scope pictures in: www.pa.msu.edu/hep/d0/ftp/run2b/l1cal/hardware/adf_prototype/pictures/ To help guarantee the proper distribution of the BX_Clk signal in a fully loaded ADF crate I would like to move this aspect of the ADF-2 card to a more conservative design. This must be done within the basic constraints of the system, e.g. using the VME-64x reserved bus lines to distribute this signal. The changes that I would like to make are: - Move the distribution of the BX_Clk to using differential signaling. This helps increase the dV/dt of the signal as it goes through the receiver's threshold region. This helps control the detrimental effect of the ground plane on the receiving ADF card moving around wrt the backplane ground. - Only electrically connect the drives on the card in the center of the crate to the backplane bus. Isolate the other 19 drives from the bus by using non-installed jumpers. This cuts the parasitic capacitive load of each bus stub almost in half. - Drive this signal pair with bipolar open collector drivers, e.g. 38's. This will help eliminate the noise on the positive edge of the signal (pull up is by the terminators only). The slower falling edge will reduce the ringing on the falling edge. The higher frequency components available with the FPGA's CMOS outputs are not effectively conducted down the VME bus structure anyway, so there is no point in adding their noise to the distribution of this signal. - Receive the BX_Clk signal with a LVDS input pair that is built into the FPGA. Use a resistive attenuator between the differential bus lines and this LVDS input. This allows BX_Clk input load, that is presented to the bus by each ADF card, to appear almost resistive to the backplane bus. This reduces the effect of the capacitive stubs at each card along the bus. - Use the VME-64x Reserved Bus lines that on the ADF card are called VME_RSVBUS(8) and VME_RSVBUS(9) to carry the differential BX_Clk signal. On the ADF-1 card this signal is carried (single ended) on VME_RSVBUS(8) and VME_RSVBUS(9) is used for Initialize Acknowledge Out. On ADF-2 Initialize Acknowledge Out can be carried on VME_RSVBUS(13) which is a spare signal on ADF-1. A drawing of the proposed circuit is shown in: www.pa.msu.edu/hep/d0/ftp/run2b/l1cal/hardware/adf_2/drawings/ Characteristics of the Virtex-II LVDS_33 Receiver: Differential Input Voltage 100 mV Min. (with input common mode = 1.25V) 350 mv Typ. n/a Max. Input Common Mode Voltage 0.20 V Min. (with input differential 1.25 V Typ. Voltage +- 350 mV) 2.80 V Max. The expected characteristics of this circuit are the following: Operating with a single receiver load: Differential Input to the LVDS Receiver 837 mV Common Mode Input to the LVDS Receiver 1.605 V Operating with 20 receiver loads: Differential Input to the LVDS Receiver 525 mV Common Mode Input to the LVDS Receiver 1.137 V Measured performance is shown in the scope pictures in: www.pa.msu.edu/hep/d0/ftp/run2b/l1cal/hardware/adf_2/pictures/ Information about the setup for making these scope pictures and an explanation of these pictures is presented in the file: 000_readme_adf_2_pictures.txt which is in the directory listed above. The main points are that the differential BX_Clk signal seen by the LVDS receiver is well with in the differential and common mode input range of this receiver, it looks clean and monotonic and that it passes through the +- 100 mV threshold region in about 1.5 nsec.