ADF-2 Board Control PAL Implementation ---------------------------- Original Rev. 24-APR-2004 Most Recent Rev. 16-Feb-2005 This file describes the implementation of the Board Control PAL that is on each ADF-2 circuit board. Outline ------- Design Strategy Signals State Machine READ Registers WRITE Registers References While reading this document, refer to the following diagrams. http://www.pa.msu.edu/hep/d0/ftp/run2b/l1cal/hardware/adf_2/drawings/ adf_2_pal_top_level_schematic.pdf and ps adf_2_pal_vme_invalid_cycle_timing_diagrams.pdf and ps adf_2_pal_vme_read_timing_diagrams.pdf and ps adf_2_pal_vme_write_timing_diagrams.pdf and ps clock_bx_x8_generation.pdf and ps adf_2_pal_state_machine_timing_diagrams.pdf and ps Notation and Definitions ------------------------ ! means complement/not + means OR * means AND A XOR B => (!A*B) + (!B*A) A NXOR B => (!A*!B) + (B*A) A=B => A NXOR B (number) implies a reference when not preceded by a net name Design Strategy --------------- Since the latency requirement for this design is long (132 ns), the logic has been made human readable rather than minimized. The rationale is to make the design easy to impliment, check and change. Full address decoding is implimented so that control lines transition only when they need to. Even if an enable signal prevents a signal from being listened to, the singal should not transition. This helps prevent an accidental write or configuration change if there is an error with the enable bit. Power up and quiescent states are also defined so that the PAL is in a known configuration when the power is turned on and after a reset. All outputs are latched so that a glitch cannot affect the outputs and also to ensure all output transitions are isochronous. Signals ------- The logic that defines each singal state is described below. There are external I/O signals and internal intermediate signals. Internal signals are used to simplify the implementaion of the PAL logic. They can be computed in one location and bussed to all logic that needs them or the logic for they can be substituted where ever the signal is used. Table 1 summarizes the signal type, power up state and quiescent state. For complete external signal descriptions see the Board Control PAL Description docuement (1). Quiescent States ---------------- Quiescent states of outputs are set by ANDing or ORing terms with the signal NEXT_STATE_QUIESCENT. Ouputs are to be set to their quiescent state when in the IDLE_STATE or LATCH_1_STATE states. In other states logic is allowed to drive them out of their quiescent state. Since all outputs are latched with a D Flip Flop, NEXT_STATE_QUIESCENT must be set one clock cycle earlier than the desired output assignment. See the diagram adf_2_pal_state_machine_timing_diagrams. NEXT_STATE_QUIESCENT -------------------------- Flip Flop --------- PowerUp = 0 D = IDLE_STATE * DS1_B + SET_QUIESCENT_STATE + VALID_CYCLE_B * (LATCH_2_STATE + IO_2_STATE) + VALID_CYCLE * IO_2_STATE * DS1_B R = '0' S = SYSRESET_DEBOUNCED En = 1 CLK = PAL_BX_CLOCK Q = NEXT_STATE_QUIESCENT -- new NEXT_STATE_QUIESCENT = IDLE_STATE + LATCH_1_STATE + VALID_CYCLE_B Quiescent High -------------- For signals that are high/1 in their quiescent state, their output logic is ORed with NEXT_STATE_QUIESCENT. The karnaugh map is given below. NEXT_STATE_ QUIESCENT | 0 1 --+------ | +-+ LOGIC 0| 0|1| D = NEXT_STATE_QUIESCENT + OUTPUT_LOGIC |+-+-+ 1||1|1| +-+-+ Quiescent Low ------------- For signals that are Low/0 in their quiescent state, their output logic is ANDed with !NEXT_STATE_QUIESCENT. The karnaugh map is given below. NEXT_STATE_ QUIESCENT | 0 1 --+------ | LOGIC 0| 0 0 D = !NEXT_STATE_QUIESCENT * OUTPUT_LOGIC |+-+ 1||1|0 +-+ Table 1: I/O Signal Summary --------------------------- Internal/ Power Up Quiescent Signal In/Out State State Latched Register =================================================================================== ADC_ENABLE Out 0 x X X BOARD_CONTROL_1_SEL Internal x x BOARD_CONTROL_2_SEL Internal x x BOARD_CONTROL_DATA_1(0:7) Internal x x BOARD_CONTROL_DATA_2(0:7) Internal x x BOARD_STATUS_1_SEL Internal x x BOARD_STATUS_2_SEL Internal x x BOARD_STATUS_DATA_1(0:7) Internal x x BOARD_STATUS_DATA_2(0:7) Internal x x PAL_BX_CLOCK In x x CNFG_BUSY(0:1) In x x X CNFG_CCLK Out 0 0 X CNFG_CONTROL_DATA(0:7) Internal x x CNFG_CONTROL_SEL Internal x x CNFG_CS_B(0:1) Out 1 x X X CNFG_DONE(0:1) In x x X CNFG_INIT_B(0:1) In x x X CNFG_PROG_B(0:1) Out 1 x X X CNFG_PROG_B_REQ(0:1) Internal 1 x X X CNFG_RDWR_B Out 1 x X X CNFG_STATUS_SEL Internal x x CNFG_STATUS_DATA(0:7) Internal x x CNT_BIT_VAL_1 Internal 0 x X CNT_BIT_VAL_2 Internal 0 x X CNT_BIT_VAL_4 In/Out 0 x X CNTRL_PAL_LED_1 In/Out 0 x X CONFIGURE_FPGAS Internal x x CRATE_STATUS_B(0:3) In x x X DAC_CHIP_SELECT_B Out 1 x X DAC_CHIP_SELECT_B_REQ Internal 1 x X X DAC_SERIAL_DATA_CLOCK Out 1 1 X DATA_BUF_DIR Out 1 1 X DATA_BUF_ENB_B Out 1 1 X DATA_TO_FIRST_DAC_INPUT Out 0 0 DRV_CRATE_TO_SCLD(0:1) Out 0 x X X DRV_CRATE_STATUS(0:3) Out 0 x X X DRV_DTACK Out 0 0 X DRV_PAL_LED(0:1) Out 1 x X DS1 Internal 0 0 X DS1_TMP Internal 0 0 X ENABLE_FPGA Internal 0 x X X _CONFIGURATION ENABLE_LOADING_DACS Internal 0 x X X ENABLE_PAL_ACCESS_OUTPUT Internal 0 x X X FPGA_0_STATUS(0:3) In x x X FPGA_1_STATUS(0:3) In x x X IDLE_STATE Internal 1 x X IO_1_STATE Internal 0 x X IO_2_STATE Internal 0 x X LAST_DAC_OUTPUT_DATA In x x X LATCH_1_STATE Internal 0 x X LATCH_2_STATE Internal 0 x X LED_STRETCHER Internal 0 x X LOAD_DACS Internal x x LOOP_FILTER_REF Out 0 x X LTCHD_AM(0:5) In x x LTCHD_IACK_B In x x LTCHD_WRITE_B In x x NEXT_STATE_QUIESCENT Internal 1 x X OCB_ADRS(1:23) In x x OCB_CHIP_SEL(0:2) Internal x x OCB_CHIP_SEL_B(0:1) Out 1 1 X OCB_DATA(0:7) In/Out 0 x X OCB_DATA_OUTPUT_ENABLE Internal 0 0 X OCB_DIRECTION Out 1 1 X OCB_WRITE_STRB_B Out 1 1 X OUTPUT_DATA Internal x x PAL_ACCESS(0:16) Out 0 x X PAL_BX_X8_CLOCK In x x PAL_FIRST_X8_EDGE Out 0 x X PAL_REGISTER(0:15) Internal x x PHASE_DET_OUT Out x x RCVD_BX_CLOCK In 0 x X RCVD_DS1 In x x SER_DC_BALANCE Out 0 x X X SER_DESKEW_B Out 1 x X X SET_QUIESCENT_STATE Internal 0 x X SYSRESET_DEBOUNCED Internal 0 x X THIS_CARD Internal x x VALID_AM Internal x x VALID_CYCLE Internal x x VME_GEO_B(0:4) In x x VME_SYSRESET_B In x x VME_LTCH_CLK Out 0 0 X WRITE_TO_PAL Internal x x ===================================================================================== Signal Definitions ------------------ ADC_ENABLE ---------- ACD_ENABLE is in the deasserted state when the power is turned on and remains deasserted until asserted by TCC. This signal is a register controlled signal. It is bit 7 of Board Level Control Register 1.(1) See teh Write Registers section. Quiescent: X Flip Flop --------- PowerUp = 0 D = OCB_DATA(7) * WRITE_TO_PAL * BOARD_CONTROL_1_SEL * OCB_WRITE_STRB + ADC_ENABLE * OCB_WRITE_STRB_B * BOARD_CONTROL_1_SEL + ADC_ENABLE * !BOARD_CONTROL_1_SEL R = SYSRESET_DEBOUNCED S = 0 En = 1 CLK = PAL_BX_CLOCK Q = ADC_ENABLE BOARD_CONTROL_1_REGISTER_SEL (Board Level Control 1) ---------------------------------------------------- This signal is used for register address decoding and is asserted when PAL_REGISTER(0) and OCB_CHIP_SEL(2) are asserted.(1) BOARD_CONTROL_1_SEL = PAL_REGISTER(0) * OCB_CHIP_SEL(2) BOARD_CONTROL_2_REGISTER_SEL (Board Level Control 2) ---------------------------------------------------- This signal is used for register address decoding and is asserted when PAL_REGISTER(1) and OCB_CHIP_SEL(2) are asserted.(1) BOARD_CONTROL_2_SEL = PAL_REGISTER(1) * OCB_CHIP_SEL(2) BOARD_CONTROL_DATA_1(0:7) ------------------------- This represents the singals in the Board Control Register 1. These signals are: Bit| Signal ---+--------------- 0 | SER_DESKEW_B 1 | SER_DC_BALANCE 2 | 3 | CNTRL_PAL_LED_1_REQ 4 | ENABLE_FPGA_CONFIGURATION 5 | ENABLE_LOADING_DACS 6 | ENABLE_PAL_ACCESS_OUTPUT 7 | ADC_ENABLE See these signals and OCB_DATA for the logic that implements them. BOARD_CONTROL_DATA_2(0:7) ------------------------- This represents the singals in the Board Control Register 2. These signals are: Bit| Signal ---+--------------- 0 | DRV_CRATE_STATUS(0) 1 | DRV_CRATE_STATUS(1) 2 | DRV_CRATE_STATUS(2) 3 | DRV_CRATE_STATUS(3) 4 | DRV_CRATE_TO_SCLD(0) 5 | DRV_CRATE_TO_SCLD(1) 6 | DAC_CHIP_SELECT_B_REQ 7 | See these signals and OCB_DATA for the logic that implements them. BOARD_STATUS_1_REGISTER_SEL (Board Level Status 1) -------------------------------------------------- This signal is used for register address decoding and is asserted when PAL_REGISTER(2) and OCB_CHIP_SEL(2) are asserted.(1) BOARD_STATUS_1_SEL = PAL_REGISTER(2) * OCB_CHIP_SEL(2) BOARD_STATUS_REGISTER_2_SEL (Board Level Status 2) -------------------------------------------------- This signal is used for register address decoding and is asserted when PAL_REGISTER(3) and OCB_CHIP_SEL(2) are asserted.(1) BOARD_STATUS_2_SEL = PAL_REGISTER(3) * OCB_CHIP_SEL(2) BOARD_STATUS_DATA_1(0:7) ------------------------ This represents the singals in the Board Status Register 1. These signals are: Bit| Signal ---+--------------- 0 | FPGA_0_STATUS(0) 1 | FPGA_0_STATUS(1) 2 | FPGA_0_STATUS(2) 3 | FPGA_0_STATUS(3) 4 | FPGA_1_STATUS(0) 5 | FPGA_1_STATUS(1) 6 | FPGA_1_STATUS(2) 7 | FPGA_1_STATUS(3) See these signals and OCB_DATA for the logic that implements them. BOARD_STATUS_DATA_2(0:7) ------------------------ This represents the singals in the Board Status Register 2. These signals are: Bit| Signal ---+--------------- 0 | CRATE_STATUS(0) 1 | CRATE_STATUS(1) 2 | CRATE_STATUS(2) 3 | CRATE_STATUS(3) 4 | LAST_DAC_OUTPUT_DATA 5 | 6 | 7 | See these signals and OCB_DATA for the logic that implements them. PAL_BX_CLOCK ------------ This an input signal and does not need logic to define it. CNFG_BUSY(0:1) -------------- This signal is part of the read only status registers. See the OCB_DATA signal description and the Read Registers section. CNFG_CCLK --------- This is a control signal for FPGA configuration. Configuration data is ingested by the FPGAs on the rising edge of this signal. CNFG_CCLK is asserted in the IO_1 state when CONFIGURE_FPGAS is asserted. Quiescent: 0 Flip Flop --------- PowerUp = 0 D = !NEXT_STATE_QUIESCENT * LATCH_2_STATE * OCB_CHIP_SEL(2) * !LTCHD_WRITE_B * CONFIGURE_FPGAS --new D = LATCH_2_STATE * CONFIGURE_FPGAS Q = CNFG_CCLK R = SYSRESET_DEBOUNCED S = 0 En = 1 CLK = PAL_BX_CLOCK CNFG_CONTROL_DATA(0:7) ---------------------- This represents the singals in the Configuration Control register. These signals are: Bit| Signal ---+--------------- 0 | CNFG_PROG_B_REQ(0) 1 | CNFG_PROG_B_REQ(1) 2 | CNFG_CS_B(0) 3 | CNFG_CS_B(1) 4 | CNFG_RDWR_B 5 | 6 | 7 | See these signals and OCB_DATA for the logic that implements them. CNFG_CONTROL_REGISTER_SEL (Configuration Control) ------------------------------------------------- This signal is used for register address decoding and is asserted when PAL_REGISTER(5) and OCB_CHIP_SEL(2) are asserted. CNFG_CONTROL_SEL = PAL_REGISTER(5) * OCB_CHIP_SEL(2) CNFG_CS_B(0:1) -------------- These are TCC controlled register bits. They are bits 2 and 3 of the Configuration Control Register.(1) CNFG_CS_B(0) --------------- Quiescent: X Flip Flop --------- PowerUp: 0 D = OCB_DATA(2) * WRITE_TO_PAL * CNFG_CONTROL_SEL * OCB_WRITE_STRB + CNFG_CS_B(0) * OCB_WRITE_STRB_B * CNFG_CONTROL_SEL + CNFG_CS_B(0) * !CNFG_CONTROL_1_SEL Q = CNFG_CS_B(0) R = 0 S = SYSRESET_DEBOUNCED En = 1 CLK = PAL_BX_CLOCK CNFG_CS_B(1) --------------- Quiescent: X Flip Flop --------- PowerUp: 0 D = OCB_DATA(3) * WRITE_TO_PAL * CNFG_CONTROL_SEL + CNFG_CS_B(1) + CNFG_CS_B(1) * OCB_WRITE_STRB_B * CNFG_CONTROL_SEL + CNFG_CS_B(1) * !CNFG_CONTROL_1_SEL Q = CNFG_CS_B(1) R = 0 S = SYSRESET_DEBOUNCED En = 1 CLK = PAL_BX_CLOCK CNFG_DONE(0:1) -------------- This signal is part of the read only status registers. See the OCB_DATA, CNFG_STATUS_REGISTER and the Read Registers section. CNFG_INIT_B(0:1) ---------------- This signal is part of the read only status registers. See the OCB_DATA signal description, CNFG_STATUS_REGISTER and the Read Registers section. CNFG_PROG_B(0:1) ---------------- These are configuration control bits for the FPGAs. Their assertion will clear the FPGAs configuration and initiate a configuration cycle. They are asserted low when both ENABLE_FPGA_CONFIGURATION and CNFG_PROG_B(X) are asserted. CNFG_PROG_B(0:1) ---------------- CNFG_PROG_B(0) --------------- Quiescent: x Flip Flop --------- POWERUP: 1 D = ENABLE_FPGA_CONFIGURATION * CNFG_PROG_B_REQ(0) Q = CNFG_PROG_B(0) R = 0 S = SYSRESET_DEBOUNCED En = 1 CLK = PAL_BX_CLOCK CNFG_PROG_B(1) --------------- Quiescent: x Flip Flop --------- POWERUP: 1 D = ENABLE_FPGA_CONFIGURATION * CNFG_PROG_B_REQ(1) Q = CNFG_PROG_B(1) R = 0 S = SYSRESET_DEBOUNCED En = 1 CLK = PAL_BX_CLOCK CNFG_PROG_B_REQ(0:1) ---------------- These are TCC controlled register bits. They are bits 0 and 1 of the Configuration Control register. CNFG_PROG_B_REQ(0) --------------- Quiescent: X Flip Flop --------- POWERUP: 1 D = OCB_DATA(0) * WRITE_TO_PAL * CNFG_CONTROL_SEL * OCB_WRITE_STRB + CNFG_PROG_B_REQ(0) * OCB_WRITE_STRB_B * CNFG_CONTROL_SEL + CNFG_PROG_B_REQ(0) * !CNFG_CONTROL_SEL Q = CNFG_PROG_B_REQ(0) R = 0 S = SYSRESET_DEBOUNCED En = 1 CLK = PAL_BX_CLOCK CNFG_PROG_B_REQ(1) --------------- Quiescent: X Flip Flop --------- POWERUP: 1 D = OCB_DATA(1) * WRITE_TO_PAL * CNFG_CONTROL_SEL * OCB_WRITE_STRB + CNFG_PROG_B_REQ(1) * OCB_WRITE_STRB_B * CNFG_CONTROL_SEL + CNFG_PROG_B_REQ(1) * !CNFG_CONTROL_SEL Q = CNFG_PROG_B_REQ(1) R = 0 S = SYSRESET_DEBOUNCED En = 1 CLK = PAL_BX_CLOCK CNFG_RDWR_B ----------- This is a TCC controlled register bit. It is bit 4 of the Configuration Control register. Quiescent: x Flip Flop --------- POWERUP: 1 D = OCB_DATA(4) * WRITE_TO_PAL * CNFG_CONTROL_SEL * OCB_WRITE_STRB + CNFG_RDWR_B * OCB_WRITE_STRB_B * CNFG_CONTROL_SEL + CNFG_RDWR_B * !CNFG_CONTROL_SEL Q = CNFG_RDWR_B R = 0 S = SYSRESET_DEBOUNCED En = 1 CLK = PAL_BX_CLOCK CNFG_STATUS_REGISTER_SEL (Configure Status) ------------------------------------------- When the target address is the Configuration Status Register (PAL_REGISTER(7)) and OCB_CHIP_SEL(2) is asserted.(1) CNFG_STATUS_SEL = PAL_REGISTER(7) * OCB_CHIP_SEL(2) CNFG_STATUS_DATA(0:7) ---------------- This represents the singals in the CNFG Status register. These signals are: Bit| Signal ---+--------------- 0 | CNFG_INIT_B(0) 1 | CNFG_INIT_B(1) 2 | CNFG_BUSY(0) 3 | CNFG_BUSY(1) 4 | CNFG_DONE(0) 5 | CNFG_DONE(1) 6 | 7 | See these signals and OCB_DATA for the logic that implements them. CNT_BIT_VAL_1 ------------- This is the least significant bit in a 3 bit count-down wrap around counter. See clock_bx_x8_generation.pdf. Quiescent: x Flip Flop --------- POWERUP: 0 D = !CNT_BIT_VAL_4 * !CNT_BIT_VAL_2 * !CNT_BIT_VAL_1 + CNT_BIT_VAL_4 * CNT_BIT_VAL_2 * !CNT_BIT_VAL_1 + CNT_BIT_VAL_4 * !CNT_BIT_VAL_2 * !CNT_BIT_VAL_1 + !CNT_BIT_VAL_4 * CNT_BIT_VAL_2 * !CNT_BIT_VAL_1 Q = CNT_BIT_VAL_1 R = 0 S = 0 En = 1 CLK = PAL_BX_X8_CLOCK CNT_BIT_VAL_2 ------------- This is the second least significant bit in a 3 bit count-down wrap around counter. See clock_bx_x8_generation.pdf. Quiescent: x Flip Flop --------- POWERUP: 0 D = !CNT_BIT_VAL_4 * !CNT_BIT_VAL_2 * !CNT_BIT_VAL_1 + CNT_BIT_VAL_4 * CNT_BIT_VAL_2 * CNT_BIT_VAL_1 + CNT_BIT_VAL_4 * !CNT_BIT_VAL_2 * !CNT_BIT_VAL_1 + !CNT_BIT_VAL_4 * CNT_BIT_VAL_2 * CNT_BIT_VAL_1 Q = CNT_BIT_VAL_2 R = 0 S = 0 En = 1 CLK = PAL_BX_X8_CLOCK CNT_BIT_VAL_4 ------------- This is the most significant bit in a 3 bit count-down wrap around counter. See clock_bx_x8_generation.pdf. Quiescent: x Flip Flop --------- POWERUP: 0 D = !CNT_BIT_VAL_4 * !CNT_BIT_VAL_2 * !CNT_BIT_VAL_1 + CNT_BIT_VAL_4 * CNT_BIT_VAL_2 * CNT_BIT_VAL_1 + CNT_BIT_VAL_4 * CNT_BIT_VAL_2 * !CNT_BIT_VAL_1 + CNT_BIT_VAL_4 * !CNT_BIT_VAL_2 * CNT_BIT_VAL_1 Q = CNT_BIT_VAL_4 R = 0 S = 0 En = 1 CLK = PAL_BX_X8_CLOCK CNTRL_PAL_LED_1 --------------- This signal is a TCC controlled register bit that enables or disables PAL LED 1. This signal is asserted high. When CNTRL_PAL_LED_1 is high the LED will be on. QUIESCENT: x Flip Flop --------- POWERUP: 0 D = OCB_DATA(3) * WRITE_TO_PAL * BOARD_CONTROL_1_SEL * OCB_WRITE_STRB + CNTRL_PAL_LED_1 * OCB_WRITE_STRB_B * BOARD_CONTROL_1_SEL + CNTRL_PAL_LED_1 * !BOARD_CONTROL_1_SEL Q = CNTRL_PAL_LED_1 R = SYSRESET_DEBOUNCED S = 0 En = 1 CLK = PAL_BX_CLOCK CONFIGURE_FPGAS --------------- When the target address is the Configuration Data Register (PAL_REGISTER(6)) and ENABLE_FPGA_CONFIGURATION is asserted this signal is asserted (1). CONFIGURE_FPGAS = PAL_REGISTER(6) * ENABLE_FPGA_CONFIGURATION * OCB_CHIP_SELECT(2) CRATE_STATUS_B(0:3) ------------------- This signal is part of the read only status registers. See the OCB_DATA signal description, BOARD_LEVEL_STATUS_REGISTER_2 and the Read Registers section. DAC_CHIP_SELECT_B ----------------- DAC_CHIP_SELECT_B is in the deasserted state when the power is turned on and remains deasserted until ENABLE_DAC_LOADING and DAC_CHIP_SELECT_B_REQ are asserted. This signal is asserted low. Quiescent: X FLIP FLOP --------- POWERUP: 1 D = ENABLE_LOADING_DACS + DAC_CHIP_SELECT_B_REQ Q = DAC_CHIP_SELECT_B R = 0 S = SYSRESET_DEBOUNCED EN = 1 CLK = PAL_BX_CLOCK DAC_CHIP_SELECT_B_REQ --------------------- DAC_CHIP_SELECT_B is in the deasserted state when the power is turned on and remains deasserted until asserted by TCC. This is bit 6 of Board Level Control Register 2. Quiescent: X FLIP FLOP --------- POWERUP: 1 D = OCB_DATA(6) * WRITE_TO_PAL * BOARD_LEVEL_CONTROL_2_SEL * OCB_WRITE_STRB + DAC_CHIP_SELECT_B_REQ * OCB_WRITE_STRB_B * CNFG_CONTROL_SEL + DAC_CHIP_SELECT_B_REQ * !CNFG_CONTROL_SEL Q = DAC_CHIP_SELECT_B_REQ R = 0 S = SYSRESET_DEBOUNCED EN = 1 CLK = PAL_BX_CLOCK DAC_SERIAL_DATA_CLOCK --------------------- This signal is asserted high. It is a control signal for the DACs. The DACs capture serial data on this signals rising edge. The DAC_SERIAL_DATA_CLOCK is asserted during the IO_1 state when LOAD_DACS is asserted. Quiescent: 1 Flip Flop --------- POWERUP: 1 D = NEXT_STATE_QUIESCENT + LATCH_2_STATE + LOAD_DACS_B + !LTCHD_WRITE_B * LOAD_DACS Q = DAC_SERIAL_CLOCK R = 0 S = SYSRESET_DEBOUNCED En = 1 CLK = PAL_BX_CLOCK DATA_BUF_DIR ------------ DATA_BUF_DIR is assigned to the same value as LTCHD_WRITE_B when VALID_CYCLE is asserted. QUIESCENT: 1 Flip Flop --------- POWERUP: 1 D = SET_QUIESCENT_STATE + NEXT_STATE_QUIESCENT + VALID_CYCLE_B + LTCHD_WRITE Q = DATA_BUF_DIR R = 0 S = SYSRESET_DEBOUNCED En = 1 CLK = PAL_BX_CLOCK DATA_BUF_ENB_B -------------- When VALID_CYCLE is asserted this signal is asserted and deasserted otherwise. QUIESCNET: 1 Flip Flop --------- POWERUP: 1 D = SET_QUIESCENT_STATE + NEXT_STATE_QUIESCENT + !VALID_CYCLE Q = DATA_BUF_ENB_B R = 0 S = SYSRESET_DEBOUNCED En = 1 CLK = PAL_BX_CLOCK DATA_TO_FIRST_DAC_INPUT ----------------------- When LOAD_DACS is asserted, the least significant bit of the OCB_DATA is put on an output to the first DAC in the daisy chain. Otherwise this signal is held low to keep the signal stable in ordert to minimize noise from the digital part of the board from affecting the analog part of the board. QUIESCNET: 0 Flip Flop --------- POWERUP: 0 D = !NEXT_STATE_QUIESCENT * LOAD_DACS * OCB_DATA(0) Q = DATA_TO_FIRST_DAC_INPUT R = SYSRESET_DEBOUNCED S = 0 En = 1 CLK = PAL_BX_CLOCK DRV_CRATE_TO_SCLD(0:1) ---------------------- Initially DRV_CRATE_TO_SCLD(0:1) is a register controlled signal, but it may be controlled by PAL logic in the future. Therefore the output for DRV_CRATE_TO_SCLD will be another macrocell instead of the macrocell for the register. In the initial implimentation this macrocell will pass the bit from the control register. In a future implementation, other logic can be used to drive this signal. These are bits 4 and 5 of Board Level Control 2 register. DRV_CRATE_TO_SCLD(0) --------------- QUIESCENT: X Flip Flop --------- POWERUP: 0 D = OCB_DATA(4) * WRITE_TO_PAL * BOARD_CONTROL_2_SEL * OCB_WRITE_STRB + DRV_CRATE_TO_SCLD(0) * OCB_WRITE_STRB_B * BOARD_CONTROL_2_SEL + DRV_CRATE_TO_SCLD(0) * !BOARD_CONTROL_2_SEL Q = DRV_CRATE_TO_SCLD(0) R = 0 S = SYSRESET_DEBOUNCED En = 1 CLK = PAL_BX_CLOCK DRV_CRATE_TO_SCLD(1) --------------- QUIESCENT: X Flip Flop --------- POWERUP: 0 D = OCB_DATA(5) * WRITE_TO_PAL * BOARD_CONTROL_2_SEL * OCB_WRITE_STRB + DRV_CRATE_TO_SCLD(1) * OCB_WRITE_STRB_B * BOARD_CONTROL_2_SEL + DRV_CRATE_TO_SCLD(1) * !BOARD_CONTROL_2_SEL Q = DRV_CRATE_TO_SCLD(1) R = 0 S = SYSRESET_DEBOUNCED En = 1 CLK = PAL_BX_CLOCK DRV_CRATE_STATUS(0:3) --------------------- Initially DRV_CRATE_STATUS is a register controlled signal, but it may be conrtorlled by PAL logic in the future. Therefore the output of DRV_CRATE_STATUS will be another macrocell instead of the macrocell for the control bit register. In the initial implimentation this macrocell will pass the bit from the control register. In a future implementation, other logic can be used to drive this signal. These are bits 0 to 4 of Board Level Control 2 register (BOARD_CONTROL_2_SEL). DRV_CRATE_STATUS(0) --------------------- Quiescent: x Flip Flop --------- POWERUP: 0 D = OCB_DATA(0) * WRITE_TO_PAL * BOARD_CONTROL_2_SEL * OCB_WRITE_STRB + DRV_CRATE_STATUS(0) * OCB_WRITE_STRB_B * BOARD_CONTROL_2_SEL + DRV_CRATE_STATUS(0) * !BOARD_CONTROL_2_SEL Q = CRATE_STATUS_B(0) R = 0 S = SYSRESET_DEBOUNCED En = 1 CLK = PAL_BX_CLOCK DRV_CRATE_STATUS(1) --------------------- Quiescent: x Flip Flop --------- POWERUP: 0 D = OCB_DATA(1) * WRITE_TO_PAL * BOARD_CONTROL_2_SEL * OCB_WRITE_STRB + DRV_CRATE_STATUS(1) * OCB_WRITE_STRB_B * BOARD_CONTROL_2_SEL + DRV_CRATE_STATUS(1) * !BOARD_CONTROL_2_SEL Q = CRATE_STATUS_B(1) R = 0 S = SYSRESET_DEBOUNCED En = 1 CLK = PAL_BX_CLOCK DRV_CRATE_STATUS(2) --------------------- Quiescent: x Flip Flop --------- POWERUP: 0 D = OCB_DATA(2) * WRITE_TO_PAL * BOARD_CONTROL_2_SEL * OCB_WRITE_STRB + DRV_CRATE_STATUS(2) * OCB_WRITE_STRB_B * BOARD_CONTROL_2_SEL + DRV_CRATE_STATUS(2) * !BOARD_CONTROL_2_SEL Q = CRATE_STATUS_B(2) R = 0 S = SYSRESET_DEBOUNCED En = 1 CLK = PAL_BX_CLOCK DRV_CRATE_STATUS(3) --------------------- Quiescent: x Flip Flop --------- POWERUP: 0 D = OCB_DATA(3) * WRITE_TO_PAL * BOARD_CONTROL_2_SEL * OCB_WRITE_STRB + DRV_CRATE_STATUS(3) * OCB_WRITE_STRB_B * BOARD_CONTROL_2_SEL + DRV_CRATE_STATUS(3) * !BOARD_CONTROL_2_SEL Q = CRATE_STATUS_B(3) R = 0 S = SYSRESET_DEBOUNCED En = 1 CLK = PAL_BX_CLOCK DRV_DTACK --------- DRV_DTACK is asserted when in the IO_2_STATE state when VALID_CYCLE is asserted and deasserted otherwise. Quiescent: x Flip Flop --------- PowerUp: 0 D = !NEXT_STATE_QUIESCENT * (IO_1_STATE + IO_2_STATE) * DS1 * VALID_CYCLE) Q = DRV_DTACK R = SYSRESET_DEBOUNCED S = 0 En = 1 CLK = PAL_BX_CLOCK DRV_PAL_LED(0:1) ---------------- DRV_PAL_LED are control flip flops that drive the PAL LEDs. One LED is controlled by a TCC controlled register and the other is a copy of the VALID_CYCLE signal. The VALID_CYCLE signal is stretched so that the LED will be on long enough for people to see it. DRV_PAL_LED(0) -------------- Quiescent: x Flip Flop --------- PowerUp: 1 D = LED_STRETCHER_COUNTER_IS_ZERO Q = DRV_PAL_LED(x) R = 0 S = SYSRESET_DEBOUNCED En = 1 CLK = PAL_BX_CLOCK DRV_PAL_LED(1) -------------- Quiescent: x Flip Flop --------- PowerUp: 1 D = !CNTRL_PAL_LED_1 Q = DRV_PAL_LED(x) R = 0 S = SYSRESET_DEBOUNCED En = 1 CLK = PAL_BX_CLOCK DS1 --- DS1 is a latched copy of RCVD_DS1 that is passed through 2 flip flops to reduce the chance of a metastable problem with other flip flops since RCVD_DS1 is asynchronous. +---+ +---+ RCVD_DS1---|D Q|----DS1_TMP----|D Q|---DS1 | | | | PAL_BX_CLOCK-+-|> | +-|> | | +---+ | +---+ | | | +---+ | +-|NOT|-------------+ +---+ DS1_TMP ------- Quiescent: x Flip Flop --------- PowerUp: 0 D = RCVD_DS1 Q = DS1_TMP R = SYSRESET_DEBOUNCED S = 0 En = 1 CLK = PAL_BX_CLOCK DS1 --- Quiescent: x Flip Flop --------- PowerUp: 0 D = DS1_TMP Q = DS1 R = SYSRESET_DEBOUNCED S = 0 En = 1 CLK = !PAL_BX_CLOCK ENABLE_FPGA_CONFIGURATION ------------------------- This is a TCC controlled register bit. It is bit 4 of the Board Level Control 1 register. Quiescent: x Flip Flop --------- POWERUP: 0 D = OCB_DATA(4) * WRITE_TO_PAL * BOARD_CONTROL_1_SEL * OCB_WRITE_STRB + ENABLE_FPGA_CONFIGURATION * OCB_WRITE_STRB_B * BOARD_CONTROL_1_SEL + ENABLE_FPGA_CONFIGURATION * !BOARD_CONTROL_1_SEL Q = ENABLE_FPGA_CONFIGURATION R = SYSRESET_DEBOUNCED S = 0 En = 1 CLK = PAL_BX_CLOCK ENABLE_LOADING_DACS ------------------- This is a TCC controlled register bit. It is bit 5 of the Board Level Control 1 register. Quiescent: x Flip Flop --------- POWERUP: 0 D = OCB_DATA(5) * WRITE_TO_PAL * BOARD_CONTROL_1_SEL * OCB_WRITE_STRB + ENABLE_LOADING_DACS * OCB_WRITE_STRB_B * BOARD_CONTROL_1_SEL + ENABLE_LOADING_DACS * !BOARD_CONTROL_1_SEL Q = ENABLE_LOADING_DACS R = SYSRESET_DEBOUNCED S = 0 En = 1 CLK = PAL_BX_CLOCK ENABLE_PAL_ACCESS_OUTPUT ------------------------ This is a TCC controlled register bit. It enables the output for the PAL ACCESS bus. It is enabled at powerup so that it can be used for debugging if TCC is not able to communicate with the ADF card. Quiescent: x Flip Flop --------- POWERUP: 1 D = OCB_DATA(6) * WRITE_TO_PAL * BOARD_CONTROL_1_SEL * OCB_WRITE_STRB + ENABLE_PAL_ACCESS_OUTPUT * OCB_WRITE_STRB_B * BOARD_CONTROL_1_SEL + ENABLE_PAL_ACCESS_OUTPUT * !BOARD_CONTROL_1_SEL Q = ENABLE_PAL_ACCESS_OUTPUT R = SYSRESET_DEBOUNCED S = 0 En = 1 CLK = PAL_BX_CLOCK FPGA_0_STATUS(0:3) ------------------ This signal is part of the read only status registers. See the OCB_DATA signal description and the Read Registers section. FPGA_1_STATUS(0:3) ------------------ This signal is part of the read only status registers. See the OCB_DATA signal description and the Read Registers section. IDLE_STATE ---------- The IDLE_STATE signal is asserted when the state machine is in the IDLE_STATE. See State Machine section. IO_1_STATE ---------- The IO_1_STATE signal is asserted when the state machine is in the IO_1_STATE. See State Machine section. IO_2_STATE ---------- The IO_2_STATE signal is asserted when the state machine is in the IO_2_STATE. See State Machine section. LAST_DAC_OUTPUT_DATA -------------------- This signal is part of the read only status registers. See the OCB_DATA and the Read Registers section. LATCH_1_STATE ------------- The LATCH_1_STATE signal is asserted when the state machine is in the LATCH_1_STATE state. See State Machine section. LATCH_2_STATE ------------- The LATCH_2_STATE signal is asserted when the state machine is in the LATCH_2_STATE state. See State Machine section. LED_STRETCHER ------------- The LED_STRETCHER triggers on VALID_CYCLE and stays asserted for 200ms. LED STRETCHER --------------- +----------------LED_STRETCHER_COUNTER_IS_NOT_ZERO--------------+ | | | +---+ CBCE | +-| | +-----------+ +---+ | VALID_CYCLE--|OR |-LED_STRETCHER_CE-|CE Q[15:0]|--LED_STRETHCER_Q--|OR |--+ +---+ | | +---+ | | PAL_BX_CLOCK------------------------|>C CEO|-----------LED_STRETCHER_CEO | | | | SYSRESET_DEBOUNCED------------------|CLR TC|--LED_STRETCHER_TC +-----------+ The LED Stretcher circuit takes the VALID_CYCLE signal and stretches is out in time. The assertion of the VALID_CYCLE signal starts a 14-bit counter. The counter continues to count until it wraps around and VALID_CYCLE is not asserted. The output of the circuit is a singal named LED_STRETCHER_COUNTER_IS_NOT_ZERO. As the name implies, it is asserted when the counter is output is not zero. The output is asserted for 2^14(16384) clock cycles after VALID_CYCLE has been asserted. This is about 2ms for a 132ns clock. LOAD_DACS --------- When VME target address for is Board Level DAC DATA register (PAL_REGISTER(4)) of the PAL and ENABLE_LOADING_DACS is asserted, this signal is asserted.(1) LOAD_DACS = PAL_REGISTER(4) * ENABLE_LOADING_DACS * OCB_CHIP_SEL(2) LOOP_FILTER_REF --------------- This is a signal for the PLL. See clock_bx_x8_generation.pdf. Flip Flop --------- PowerUp = 0 D = !LOOP_FILTER_REF Q = LOOP_FILTER_REF R = 0 S = 0 En = 1 CLK = PAL_BX_CLOCK LTCHD_AM(0:5) ------------- These are input signals and do not need logic to define them. LTCHD_IACK_B ------------ This is an input signal and does not need logic to define it. LTCHD_WRITE_B ------------- This is an input signal and does not need logic to define it. NEXT_STATE_QUIESCENT -------------------- This signal is asserted if the current state is IDLE_STATE or LATCH_1_STATE. It is used to drive a Flip Flop to its quiescent state during the IDLE and LATCH_1 states, and during LATCH_2 state when VALID_CYCLE is deasserted. Flip Flop --------- PowerUp = 1 D = IDLE_STATE * !DS1 + SET_QUIESCENT_STATE + !VALID_CYCLE * (LATCH_2_STATE + IO_2_STATE) + VALID_CYCLE * IO_2_STATE * !DS1 Q = NEXT_STATE_QUIESCENT R = 0 S = SYSRESET_DEBOUNCED En = 1 CLK = PAL_BX_CLOCK -- new NEXT_STATE_QUIESCENT = IDLE_STATE + LATCH_1_STATE + VALID_CYCLE OCB_ADRS(1:23) -------------- These are input signals and do not need logic to define them. OCB_CHIP_SEL(0:2) ----------------- If the OCB_ADRS(5:17) match the bit pattern for OCB_CHIP_SEL(X) address and VALID_CYCLE is asserted then OCB_CHIP_SEL(X) is asserted.(1)(2) Address +---------------------------------+ |1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0| Target |7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1| +-----------+---------------------------------+ | 0: FPGA 0 |0 <--Not all 0's--------> x x x x| | 1: FPGA 1 |1 <--Not all 0's--------> x x x x| | 2: PAL |0 0 0 0 0 0 0 0 0 0 0 0 0 x x x x| +-----------+---------------------------------+ OCB_CHIP_SEL(0) --------------- OCB_CHIP_SEL(0) = !OCB_ADRS(17) and (OCB_ADRS(5) or OCB_ADRS(6) or OCB_ADRS(7) or OCB_ADRS(8) or OCB_ADRS(9) or OCB_ADRS(10) or OCB_ADRS(11) or OCB_ADRS(12) or OCB_ADRS(13) or OCB_ADRS(14) or OCB_ADRS(15) or OCB_ADRS(16) ) and VALID_CYCLE = !OCB_ADRS(17) * (OCB_ADRS(5) + OCB_ADRS(6) + OCB_ADRS(7) + OCB_ADRS(8) + OCB_ADRS(9) + OCB_ADRS(10) + OCB_ADRS(11) + OCB_ADRS(12) + OCB_ADRS(13) + OCB_ADRS(14) + OCB_ADRS(15) )* VALID_CYCLE OCB_CHIP_SEL(1) --------------- OCB_CHIP_SEL(1) = OCB_ADRS(17) and (OCB_ADRS(5) or OCB_ADRS(6) or OCB_ADRS(7) or OCB_ADRS(8) or OCB_ADRS(9) or OCB_ADRS(10) or OCB_ADRS(11) or OCB_ADRS(12) or OCB_ADRS(13) or OCB_ADRS(14) or OCB_ADRS(15) or OCB_ADRS(16) ) and VALID_CYCLE = OCB_ADRS(17) * (OCB_ADRS(5) + OCB_ADRS(6) + OCB_ADRS(7) + OCB_ADRS(8) + OCB_ADRS(9) + OCB_ADRS(10) + OCB_ADRS(11) + OCB_ADRS(12) + OCB_ADRS(13) + OCB_ADRS(14) + OCB_ADRS(15) )* VALID_CYCLE OCB_CHIP_SEL(2) --------------- OCB_CHIP_SEL(2) = !OCB_ADRS(17) and !OCB_ADRS(5:16) and VALID_CYCLE = !OCB_ADRS(17) * !OCB_ADRS(5:16) * VALID_CYCLE OCB_CHIP_SEL_B(0:1) ----------------- This is a latched inverted copy of OCB_CHIP_SEL(0) and OCB_CHIP_SEL(1) that is sent to the FPGAs. Flip Flop --------- POWERUP = 1 D = NEXT_STATE_QUIESCENT + !OCB_CHIP_SEL(X) Q = OCB_CHIP_SEL_B(X) R = 0 S = SYSRESET_DEBOUNCED En = 1 CLK = PAL_BX_CLOCK OCB_DATA(0:7) ------------- This is the lower 8 bits of the OCB_DATA.(1)(3) Flip Flop --------- PowerUp = 0 D = OUTPUT_DATA(X) Q = OCB_DATA(X) R = SYSRESET_DEBOUNCED S = 0 En = OCB_DATA_OUTPUT_ENABLE CLK = PAL_BX_CLOCK OCB_DATA_OUTPUT_ENABLE ---------------------- This signal controls the output buffers for the OCB_DATA signals. This signal is latched to prevent inadvertant enabling of the outputs. It is asserted when OCB_CHIP_SEL(2) is asserted and LTCHD_WRITE_B is deasserted. Quiescent: 0 Flip Flop --------- PowerUp = 0 D = !NEXT_STATE_QUIESCENT * OCB_CHIP_SEL(2) * LTCHD_WRITE_B Q = OCB_DATA_OUTPUT_ENABLE R = SYSRESET_DEBOUNCED S = 0 En = 1 CLK = PAL_BX_CLOCK OCB_DIRECTION ------------- When VALID_CYCLE is asserted and LTCHD_WRITE_B is asserted, OCB_DIRECTION is asserted, otherwise it is deasserted. Quiescent: 1 Flip Flop --------- PowerUp = 1 D = NEXT_STATE_QUIESCENT + (LATCH_2_STATE * VALID_CYCLE) + (VALID_CYCLE * LTCHD_WRITE_B) Q = OCB_DIRECTION R = 0 S = SYSRESET_DEBOUNCED En = 1 CLK = PAL_BX_CLOCK OCB_WRITE_STROBE_B ------------------ This is the clock signal for the On Card Bus. Writes are defined to happen the on falling edge of this signal. OCB_WRITE_STRB_B is high during invalid IO cycles, valid read IO cycles and during the LATCH_1, LATCH_2, IO_2 and SET_QUIESCENT states of a valid write IO cycle. It is only asserted low during the IO_1 state when the current IO cycle is valid and a write to an On Card Bus target. Quiescent: 1 Flip Flop --------- PowerUp = 1 D = NEXT_STATE_QUIESCENT + !(LATCH_2_STATE * LTCHD_WRITE * (OCB_CHIP_SEL(2) + OCB_CHIP_SEL(1) + OCB_CHIP_SEL(0))) Q = OCB_WRITE_STROBE_B R = 0 S = SYSRESET_DEBOUNCED En = 1 CLK = PAL_BX_CLOCK OUTPUT_DATA(0:7) ---------------- This represents the multiplexed output data that has been selected from the configuration and status registers. This signal is only needed for refering to the multiplexed signals and exists internally in macrocells between the OR gate and the output buffer. This is the D input to the Flip Flops for OCB_DATA(0:7) OUTPUT_DATA(X) = BOARD_STATUS_1(X) * BOARD_STATUS_1_SEL + BOARD_STATUS_2(X) * BOARD_STATUS_2_SEL + CNFG_STATUS(X) * CNFG_STATUS_SEL + BOARD_CONTROL_1(X) * BOARD_CONTROL_1_SEL + BOARD_CONTROL_2(X) * BOARD_CONTROL_2_SEL + CNFG_CONTROL(X) * CNFG_CONTROL_SEL PAL_ACCESS(0:16) ---------------- These are programable IO for the PAL. They can be used to output debugging signals or they can be used to get additional inputs and outputs to the PAL is the design needs to be changed. The PAL_ACCESS signals are defined to be bi-directional but the are assumed to be latched outputs until otherwise specified. The PAL_ACCESS signals are set up in the following configurations. VME COMMUNICATIONS DEBUGGING Index| Signal -----+------------ 0 | PAL_BX_CLOCK 1 | DS1 2 | DRV_DTACK 3 | VALID_CYCLE 4 | VME_LTCH_CLK 5 | DATA_BUF_ENB_B 6 | DATA_BUF_DIR 7 | OCB_DIRECTION 8 | OCB_CHIP_SEL(2) 9 | OCB_DATA_OUTPUT_ENABLE 10 | OCB_WRITE_STRB_B 11 | OCB_DATA(0) 12 | OCB_ADRS(1) 13 | WRITE_TO_PAL 14 | BOARD_CONTROL_1_SEL 15 | SER_DESKEW_B 16 | DRV_CRATE_STATUS(0) Latched Outputs --------------- PAL_ACCESS(X) --------------- Flip Flop --------- D = Q = PAL_ACCESS(0) R = 0 S = 0 En = 1 CLK = PAL_BX_CLOCK PAL_BX_X8_CLOCK --------------- This is an input signal and does not need logic to define it. See clock_bx_x8_generation.pdf. PAL_FIRST_X8_EDGE ----------------- This is a divider this counting the first state of the 3 bit count-down wrap around counter implemented with the signals CNT_BIT_VAL_1, CNT_BIT_VAL_2, and CNT_BIT_VAL_4. See clock_bx_x8_generation.pdf. Flip Flop --------- PowerUp = 0 D = !CNT_BIT_VAL_4 * !CNT_BIT_VAL_2 * CNT_BIT_VAL_1 Q = PAL_FIRST_X8_EDGE R = 0 S = 0 En = 1 CLK = PAL_BX_X8_CLOCK PAL_REGISTER(0:15) ------------------ This array represents the decoding of the lower address bits OCB_ADRS(1:4). An element of the array is asserted when its index matches the OCB_ADRS decoding. PAL_REGISTER(0) = !OCB_ADRS(4) * !OCB_ADRS(3) * !OCB_ADRS(2) * !OCB_ADRS(1) PAL_REGISTER(1) = !OCB_ADRS(4) * !OCB_ADRS(3) * !OCB_ADRS(2) * OCB_ADRS(1) PAL_REGISTER(2) = !OCB_ADRS(4) * !OCB_ADRS(3) * OCB_ADRS(2) * !OCB_ADRS(1) PAL_REGISTER(3) = !OCB_ADRS(4) * !OCB_ADRS(3) * OCB_ADRS(2) * OCB_ADRS(1) PAL_REGISTER(4) = !OCB_ADRS(4) * OCB_ADRS(3) * !OCB_ADRS(2) * !OCB_ADRS(1) PAL_REGISTER(5) = !OCB_ADRS(4) * OCB_ADRS(3) * !OCB_ADRS(2) * OCB_ADRS(1) PAL_REGISTER(6) = !OCB_ADRS(4) * OCB_ADRS(3) * OCB_ADRS(2) * !OCB_ADRS(1) PAL_REGISTER(7) = !OCB_ADRS(4) * OCB_ADRS(3) * OCB_ADRS(2) * OCB_ADRS(1) PAL_REGISTER(8) = OCB_ADRS(4) * !OCB_ADRS(3) * !OCB_ADRS(2) * !OCB_ADRS(1) PAL_REGISTER(9) = OCB_ADRS(4) * !OCB_ADRS(3) * !OCB_ADRS(2) * OCB_ADRS(1) PAL_REGISTER(10) = OCB_ADRS(4) * !OCB_ADRS(3) * OCB_ADRS(2) * !OCB_ADRS(1) PAL_REGISTER(11) = OCB_ADRS(4) * !OCB_ADRS(3) * OCB_ADRS(2) * OCB_ADRS(1) PAL_REGISTER(12) = OCB_ADRS(4) * OCB_ADRS(3) * !OCB_ADRS(2) * !OCB_ADRS(1) PAL_REGISTER(13) = OCB_ADRS(4) * OCB_ADRS(3) * !OCB_ADRS(2) * OCB_ADRS(1) PAL_REGISTER(14) = OCB_ADRS(4) * OCB_ADRS(3) * OCB_ADRS(2) * !OCB_ADRS(1) PAL_REGISTER(15) = OCB_ADRS(4) * OCB_ADRS(3) * OCB_ADRS(2) * OCB_ADRS(1) PHASE_DET_OUT ------------- This is a signal for the PLL. See clock_bx_x8_generation.pdf. PHASE_DET_OUT = RCVD_BX_CLOCK XOR LOOP_FILTER_REF RCVD_BX_CLOCK ------------- This is a signal for the PLL. See clock_bx_x8_generation.pdf. Flip Flop --------- PowerUp = 0 D = !RCVD_BX_CLOCK Q = RCVD_BX_CLOCK R = 0 S = 0 En = 1 CLK = PAL_BX_CLOCK RCVD_DS1 -------- This is an input signal and does not need logic to define it. See DS1 signal description. SER_DC_BALANCE -------------- SER_DC_BALANCE is in the deasserted state when the power is turned on and remains deasserted until asserted by TCC. This signal is a register controlled signal. It is bit 1 of Board Level Control 1 register. Flip Flop --------- PowerUp = 0 D = OCB_DATA(1) * WRITE_TO_PAL * BOARD_CONTROL_1_SEL Q = SER_DC_BALANCE R = SYSRESET_DEBOUNCED S = 0 En = 1 CLK = PAL_BX_CLOCK SER_DESKEW_B ------------ SER_DESKEW_B is in the deasserted state when the power is turned on and remains deasserted until asserted by TCC. This signal is a register controlled signal. It is bit 0 of Board Level Control 1 register. Flip Flop --------- PowerUp = 1 D = OCB_DATA(0) * WRITE_TO_PAL * BOARD_CONTROL_1_SEL Q = ADC_ENABLE R = SYSRESET_DEBOUNCED S = 0 En = 1 CLK = PAL_BX_CLOCK SET_QUIESCENT_STATE ------------------- The SET_QUIESCENT_STATE signal is asserted when the state machine is in the SET_QUIESCENT_STATE. See State Machine section. SYSRESET_DEBOUNCED ------------------ When the VME_SYSRESET_B signal is asserted, the state machine is forced into the idle state and all signals are set to their quiescent state. To protect from noise on the VME_SYSRESET_B line reseting the Board Control PAL with a nano second spike, a debounce circuit will be used to confirm the signal was asserted for at least one cycle. This signal is a debounced copy of VME_SYSRESET_B. VME_SYSRESET_B must be deasserted for 3 clock cycles for SYS_RESET_DEBOUNCED to be asserted. There is a 3 cycle latancy for assertion and deassertion of SYSRESET_DEBOUNCED. +-----+ +-----+ +-----+ VME_SYSRESET_B-+-|D1 Q1|-TMP1-+-|D2 Q2|-TMP2-+-|D3 Q3|--+ | | | | | | | | | TMP3 PAL_BX_CLOCK-+---|> | +--|> | +----|> | | +---+ | | +-----+ || +-----+ | | +-----+ +-| | +---------------+------------+ +------------|OR |-TMP4-+ | +---------------------------| | | +------------------------------------------| | | +---+ | +-------------+ | +---+ +-|NOT|-SYSRESET_DEBOUNCED +---+ THIS_CARD --------- If the upper bits of the OCB_ADRS match the VME_GEO_B signals then this signal is asserted.(2) THIS_CARD = [VME_GEO_B(0:4) = OCB_ADRS(18:22)] and !OCB_ADRS(23) THIS_CARD = [OCB_ADRS(18) NXOR VME_GEO_B(0) + OCB_ADRS(19) NXOR VME_GEO_B(1) + OCB_ADRS(20) NXOR VME_GEO_B(2) + OCB_ADRS(21) NXOR VME_GEO_B(3) + OCB_ADRS(22) NXOR VME_GEO_B(4)]* !OCB_ADRS(23) THIS_CARD = [!OCB_ADRS(18) * !VME_GEO_B(0) + VME_GEO_B(0) * OCB_ADRS(18) + !OCB_ADRS(19) * !VME_GEO_B(1) + VME_GEO_B(1) * OCB_ADRS(19) + !OCB_ADRS(20) * !VME_GEO_B(2) + VME_GEO_B(2) * OCB_ADRS(20) + !OCB_ADRS(21) * !VME_GEO_B(3) + VME_GEO_B(3) * OCB_ADRS(21) + !OCB_ADRS(22) * !VME_GEO_B(4) + VME_GEO_B(4) * OCB_ADRS(22)]* !OCB_ADRS(23) Macrocell Bits ------------------ 1 18,19 2 20,21 3(Output) 22,Macrocell(1), Macrocell(2) A macrocell in the PAL can input 5 AND terms and OR them together. When comparing VME_GEO_B to OCB_ADRS, it does not matter which bits match or not, just that all match or at least one does not. Therefore, AND terms from 2 bits can be ORed together in the same macrocell to determine if both bits are the same or not between OCB_ADRS and VME_GEO_B. This bit comparison can be ORed with other 2 bit comparisons in other macrocells which would indicate if VME_GEO_B = ADRS(18:22). VALID_AM -------- If the VME address modifier is set to Standard Non-Priviledged Data or Standard Supervisory Data this signal is asserted. (2) VALID_AM = [LTCHD_AM(0:5) = 100111] or [LTCHD_AM(0:5) = 101111] VALID_AM = [LTCHD_AM(0) * !LTCHD_AM(1) * !LTCHD_AM(2) * LTCHD_AM(3) * LTCHD_AM(4) * LTCHD_AM(5)] + [LTCHD_AM(0) * !LTCHD_AM(1) * LTCHD_AM(2) * LTCHD_AM(3) * LTCHD_AM(4) * LTCHD_AM(5)] VALID_CYCLE --------------- If THIS_CARD and VALID_AM are asserted and the current I/O cycle is not an interrupt cycle during the LATCH_1, IO_1, IO_2 and SET_QUIESCENT states , then this signal is asserted. This means the current VME I/O cycle is valid for this card. VALID_CYCLE = LTCHD_IACK_B * THIS_CARD * VALID_AM * (LATCH_2_STATE + IO_1_STATE + IO_2_STATE + SET_QUIESCENT_STATE) VME_GEO_B(0:4) -------------- This is an input signal and does not need logic to define it. VME_SYSRESET_B -------------- This is an input signal and does not need logic to define it. See SYSRESET_DEBOUNCED signal description. VME_LTCH_CLK ------------ VME_LTCH_CLK is asserted in the LATCH_1_STATE state and deasserted otherwise. Quiescent: 0 Flip Flop --------- PowerUp = D = IDLE_STATE * DS1 Q = VME_LTCH_CLK R = SYSRESET_DEBOUNCED S = 0 En = 1 CLK = PAL_BX_CLOCK WRITE_TO_PAL ------------ This signal is asserted when OCB_CHIP_SEL(2) is asserted and when LTCHD_WRITE_B is asserted. WRITE_TO_PAL = OCB_CHIP_SEL(2) * !LTCHD_WRITE_B ------------------------------------------------------------------------------------- State Machine ------------------------------------------------------------------------------------- The state machine consists of 5 states: IDLE_STATE, LATCH_1_STATE, LATCH_2_STATE, IO_1_STATE, and IO_2_STATE. See table 2. IDLE_STATE ---------- The state machine transistions to the IDLE_STATE state when the previous state is in the IO_2_STATE state and DS1 is deasserted, when in an illegal state, when the previous state is IDLE_STATE and RCVD_DS1 is deasserted, or when VALID_CYCLE is deasserted. The IDLE_STATE state waits for DS1 asserted and transitions to the LATCH_1_STATE state. All outputs are in the quiescent state in the IDLE_STATE state. Flip Flop --------- POWERUP: 1 D = (See State Transition Truth Tables in implementation document) 1) !IDLE_STATE * !LATCH_1_STATE * !LATCH_2_STATE * !IO_1_STATE * !IO_2_STATE* !SET_QUIESCENT_STATE + 2) !IDLE_STATE * !LATCH_1_STATE * !LATCH_2_STATE * !IO_1_STATE * !IO_2_STATE* SET_QUIESCENT_STATE + 3) !IDLE_STATE * !LATCH_1_STATE * !LATCH_2_STATE * !IO_1_STATE * (IO_2_STATE* SET_QUIESCENT_STATE)+ 4) !IDLE_STATE * !LATCH_1_STATE * !LATCH_2_STATE * IO_1_STATE * !IO_2_STATE* !SET_QUIESCENT_STATE * !VALID_CYCLE + 5) !IDLE_STATE * !LATCH_1_STATE * !LATCH_2_STATE * IO_1_STATE * !IO_2_STATE* !SET_QUIESCENT_STATE * !DS1 + 6) !IDLE_STATE * !LATCH_1_STATE * !LATCH_2_STATE * IO_1_STATE * (IO_2_STATE+ SET_QUIESCENT_STATE) + 7) !IDLE_STATE * !LATCH_1_STATE * LATCH_2_STATE * !IO_1_STATE * !IO_2_STATE !SET_QUIESCENT_STATE * !DS1 + 8) !IDLE_STATE * !LATCH_1_STATE * LATCH_2_STATE * (IO_1_STATE + IO_2_STATE+ SET_QUIESCENT_STATE) + 9) !IDLE_STATE * LATCH_1_STATE * !LATCH_2_STATE * !IO_1_STATE * !IO_2_STATE * !DS1 + 10) !IDLE_STATE * LATCH_1_STATE * (LATCH_2_STATE + IO_1_STATE + IO_2_STATE+ SET_QUIESCENT_STATE) + 11) IDLE_STATE * !LATCH_1_STATE * !LATCH_2_STATE * !IO_1_STATE * !IO_2_STATE !SET_QUIESCENT_STATE * !DS1 + 12) IDLE_STATE * (LATCH_1_STATE + LATCH_2_STATE + IO_1_STATE + IO_2_STATE) SET_QUIESCENT_STATE) Q = IDLE_STATE R = 0 S = SYSRESET_DEBOUNCED EN = 1 CLK = PAL_BX_CLOCK LATCH_1_STATE ------------- LATCH_1_STATE is the next state when the previous state is IDLE_STATE and RCVD_DS1 is asserted. In the LATCH_1_STATE state, VME_LTCH_CLK is asserted and the VME_ADRS, VME_AM, VME_IACK_B, and VME_WRITE_B are latched to OCB_ADRS, LTCHD_AM, LTCHD_IACK, and LTCHD_WRITE_B respectively. After one PAL_BX_CLOCK there is a transition to the LATCH_2_STATE state. Before that PAL_BX_CLOCK, OCB_DIRECTION, OCB_CHIP_SEL_B, DATA_BUF_ENB_B and DATA_TO_FIRST_DAC_INPUT are set. The output signals states are defined in the signal section . Flip Flop --------- POWERUP: 0 D = IDLE_STATE * !LATCH_1_STATE * !LATCH_2_STATE * !IO_1_STATE * !IO_2_STATE !SET_QUIESCENT * DS1 Q = IDLE_STATE R = SYSRESET_DEBOUNCED S = 0 EN = 1 CLK = PAL_BX_CLOCK LATCH_2_STATE ------- LATCH_2_STATE is the next state when LATCH_1_STATE is the previous state. When the LATCH_2_STATE state is entered the VME_LTCH_CLK is deasserted. The transistion to IO_1_STATE state occurs on the next PAL_BX_CLOCK assertion. Flip Flop --------- POWERUP: 0 D = !IDLE_STATE * LATCH_1_STATE * !LATCH_2_STATE * !IO_1_STATE * !IO_2_STATE * !SET_QUIESCENT * DS1 Q = LATCH_2_STATE R = SYSRESET_DEBOUNCE S = 0 EN = 1 CLK = PAL_BX_CLOCK IO_1_STATE ---------- IO_1_STATE is the next state when the previous state is LATCH_2_STATE and VALID_CYCLE and DS1 are asserted. In the IO_1_STATE state the WRITE_CLOCK is asserted. The next state is IO_2_STATE and is transitioned to on the next PAL_BX_CLOCK assertion. The WRITE_CLOCK is to be asserted after OCB_ADRS, OCB_DATA, OCB_DIRECTION, and OCB_CHIP_SEL_B are asserted and stable for at least 132ns. These signals were asserted in the LATCH_1_STATE state and were stable during the LATCH_2_STATE state, so that the timing regquirements are met. (3) Flip Flop --------- POWERUP: 0 D = !IDLE_STATE * !LATCH_1_STATE * LATCH_2_STATE * !IO_1_STATE * !IO_2_STATE * !SET_QUIESCENT_STATE * RCVD_DS1 * VALID_CYCLE Q = IO_1_STATE R = SYSRESET_DEBOUNCE S = 0 EN = 1 CLK = PAL_BX_CLOCK IO_2_STATE ---------- IO_2_STATE is the next state when IO_1_STATE is the previous state. When the IO_2_STATE state is entered the WRITE_CLOCK is deasserted. The DRV_DTACK signal is asserted indicating to the VME master that the write operation is complete or that data is ready to be read. The next state is IDLE_STATE and is transitioned to on the next PAL_BX_CLOCK assertion after the VME master acknowledges and the RCVD_DS1 signal is deasserted. Since all signals are quiescent in the IDLE_STATE state, DRV_DTACK will be deasserted. Flip Flop --------- POWERUP: 0 D = !IDLE_STATE * !LATCH_1_STATE * !LATCH_2_STATE * IO_1_STATE * !IO_2_STATE * !SET_QUIESCENT_STATE * DS1 * VALID_CYCLE + !IDLE_STATE * !LATCH_1_STATE * !LATCH_2_STATE * !IO_1_STATE * IO_2_STATE * !SET_QUIESCENT * DS1 + !IDLE_STATE * !LATCH_1_STATE * LATCH_2_STATE * !IO_1_STATE * !IO_2_STATE * !SET_QUIESCENT * !VALID_CYCLE Q = IO_2_STATE R = SYSRESET_DEBOUNCE S = 0 EN = 1 CLK = PAL_BX_CLOCK SET_QUIESCENT_STATE ------------------- SET_QUIESCENT_STATE is the next state when IO_2 is the previous state and DS1 is deasserted. The next state is IDLE and is entered on the next PAL_BX_CLOCK assertion. NEXT_STATE_QUIESCENT is asserted in the SET_QUIESCENT_STATE forcing singals to be in their quiescent state during the first IDLE_STATE clock cycle after a VME IO cycle. Flip Flop --------- POWERUP: 0 D = !IDLE_STATE * !LATCH_1_STATE * !LATCH_2_STATE * !IO_1_STATE * IO_2_STATE * !SET_QUIESCENT * !DS1 Q = SET_QUIESCENT R = SYSRESET_DEBOUNCE S = 0 EN = 1 CLK = PAL_BX_CLOCK State Diagram ------------- +------------+ +--->| IDLE_STATE |<----------+ Wait for DS1 to be | +------------+ | asserted to start | | | VME IO cycle +----------+ | | | v | +-------------+ | |LATCH_1_STATE| | Latch VME address and +-------------+ | control signals and | | compute if current VME | | IO cycle is valid for | | this card v | +-------------+ | Set OCB control signals +---|LATCH_2_STATE| | | +-------------+ | | | | | v | | +-------------+ | Perform IO if current | | IO_1_STATE | | VME IO cycle is valid for | +-------------+ | this card | | | | v | | +-------------+ | Wait for DS1 to be +-->| IO_2_STATE |<-+ | deasserted to finish VME +-------------+ | | IO cycle | | | +----------+ | | | v | +-------------+ | |Set_Quiescent|----------+ Prepare to set signals +-------------+ to their quiescent states Table 2: States, Transitions and Outputs ---------------------------------------- Current Next State State Event Outputs --------------------------------------------------------------------------------- 1 IDLE LATCH_1 RCDVD_DS1 Quiescent Assertion 2 LATCH_1 LATCH_2 PAL_BX_CLOCK VME_LTCH_CLK Assert Assetion Set: OCB_DIRECTION OCB_CHIP_SEL_B DATA_BUF_DIR DATA_BUF_ENB_B DATA_TO_FIRST_DAC_INPUT 3 LATCH_2 IO_1 PAL_BX_CLOCK VME_LTCH_CLK Deassert or IO_2 Assertion 4 IO_1 IO_2 PAL_BX_CLOCK WRITE_CLOCK Assert if LTCHD_WRITE_B Assertion is asserted 5 IO_2 SET_QUIESCNET RCVD_DS1 Write_Clock Deassert or IO_2 Deassertion DRV_DTACK Assert 6 SET_QUEISCENT IDLE PAL_BX_CLOCK Next_State_Quiescent Assertion Asserted X Any IDLE SYSRESET_DEBOUNCDE All set to quiescent asserted for one clock cycle State Transition Truth Table ============================================================================ +--+-+----------------------------------+ +--+-+----------------------------------+ | |I| | CURRENT S | | |I| | CURRENT S | | |N| | STATE E | | |N| | STATE E | | I|V| | T V | | I|V| | T V | | D|A| NEXT | A | | D|A| NEXT | A | | L|L| STATE | Q L | | L|L| STATE | Q L | | E|I| | U I | | E|I| | U I | | |D| | I D | | |D| | I D | | T| | | L L E | | T| | | L L E | | E|S| | A A S C | | E|S| | A A S C | | R|T| | I T T C Y | | R|T| | I T T C Y | | M|A| | D C C I I E D C | | M|A| | D C C I I E D C | | |T| | L H H O O N S L | | |T| | L H H O O N S L | | |E| | E 1 2 1 2 T 1 E | | |E| | E 1 2 1 2 T 1 E | +--+-+--------+-------------------------+ +--+-+--------+-------------------------+ | 1|*| IDLE | 0 0 0 0 0 0 x x | | ||*| IDLE | 0 0 1 1 1 0 x x | | | | | | | || | | | | 2| | IDLE | 0 0 0 0 0 1 x x | | v|*| IDLE | 0 0 1 1 1 1 x x | | | | | | | | | | | | | |SET_ | 0 0 0 0 1 0 0 1 | | 9|*| IDLE | 0 1 0 0 0 0 0 x | | | |QUIESCENT | | | | | | | | | IO_2 | 0 0 0 0 1 0 1 x | | | | LATCH_2| 0 1 0 0 0 0 1 x | | | | | | | | | | | | 3|*| IDLE | 0 0 0 0 1 1 x x | | ^|*| IDLE | 0 1 0 0 0 1 x x | | | | | | | || | | | | 4|*| IDLE | 0 0 0 1 0 0 x 0 | | ||*| IDLE | 0 1 0 0 1 0 x x | | | | | | | || | | | | 5|*| IDLE | 0 0 0 1 0 0 0 x | | ||*| IDLE | 0 1 0 0 1 1 x x | | | | | | | || | | | | | | IO_2 | 0 0 0 1 0 0 1 1 | | ||*| IDLE | 0 1 0 1 0 0 x x | | | | | | | || | | | | ^|*| IDLE | 0 0 0 1 0 1 x x | | ||*| IDLE | 0 1 0 1 0 1 x x | | || | | | | || | | | | 6|*| IDLE | 0 0 0 1 1 0 x x | | ||*| IDLE | 0 1 0 1 1 0 x x | | || | | | | || | | | | v|*| IDLE | 0 0 0 1 1 1 x x | | ||*| IDLE | 0 1 0 1 1 1 x x | | | | | | | || | | | | | | IO_2 | 0 0 1 0 0 0 x 0 | |10|*| IDLE | 0 1 1 0 0 0 x x | | | | | | | || | | | | 7|*| IDLE | 0 0 1 0 0 0 0 x | | ||*| IDLE | 0 1 1 0 0 1 x x | | | | | | | || | | | | | | IO_1 | 0 0 1 0 0 0 1 1 | | ||*| IDLE | 0 1 1 0 1 0 x x | | | | | | | || | | | | ^|*| IDLE | 0 0 1 0 0 1 x x | | ||*| IDLE | 0 1 1 0 1 1 x x | | || | | | | || | | | | ||*| IDLE | 0 0 1 0 1 0 x x | | ||*| IDLE | 0 1 1 1 0 0 x x | | || | | | | || | | | | ||*| IDLE | 0 0 1 0 1 1 x x | | ||*| IDLE | 0 1 1 1 0 1 x x | | || | | | | || | | | | 8|*| IDLE | 0 0 1 1 0 0 x x | | ||*| IDLE | 0 1 1 1 1 0 x x | | || | | | | || | | | | ||*| IDLE | 0 0 1 1 0 1 x x | | v|*| IDLE | 0 1 1 1 1 1 x x | +==+=+========+=========================+ +==+=+========+=========================+ +--+-+----------------------------------+ +--+-+----------------------------------+ | |I| | CURRENT S | | |I| | CURRENT S | | |N| | STATE E | | |N| | STATE E | | I|V| | T V | | I|V| | T V | | D|A| NEXT | A | | D|A| NEXT | A | | L|L| STATE | Q L | | L|L| STATE | Q L | | E|I| | U I | | E|I| | U I | | |D| | I D | | |D| | I D | | T| | | L L E | | T| | | L L E | | E|S| | A A S C | | E|S| | A A S C | | R|T| | I T T C Y | | R|T| | I T T C Y | | M|A| | D C C I I E D C | | M|A| | D C C I I E D C | | |T| | L H H O O N S L | | |T| | L H H O O N S L | | |E| | E 1 2 1 2 T 1 E | | |E| | E 1 2 1 2 T 1 E | +--+-+--------+-------------------------+ +--+-+--------+-------------------------+ |11| | IDLE | 1 0 0 0 0 0 0 x | || |*| IDLE | 1 1 0 0 0 0 x x | | | | | | || | | | | | | | LATCH_1| 1 0 0 0 0 0 1 x | || |*| IDLE | 1 1 0 0 0 1 x x | | | | | | || | | | | |^ |*| IDLE | 1 0 0 0 0 1 0 x | || |*| IDLE | 1 1 0 0 1 0 x x | || | | | | || | | | | || |*| IDLE | 1 0 0 0 1 0 x x | || |*| IDLE | 1 1 0 0 1 1 x x | || | | | | || | | | | || |*| IDLE | 1 0 0 0 1 1 x x | || |*| IDLE | 1 1 0 1 0 0 x x | || | | | | || | | | | || |*| IDLE | 1 0 0 1 0 0 x x | || |*| IDLE | 1 1 0 1 0 1 x x | || | | | | || | | | | || |*| IDLE | 1 0 0 1 0 1 x x | || |*| IDLE | 1 1 0 1 1 0 x x | || | | | | || | | | | || |*| IDLE | 1 0 0 1 1 0 x x | || |*| IDLE | 1 1 0 1 1 1 x x | || | | | | || | | | | || |*| IDLE | 1 0 0 1 1 1 x x | || |*| IDLE | 1 1 1 0 0 0 x x | || | | | | || | | | | || |*| IDLE | 1 0 1 0 0 0 x x | |12|*| IDLE | 1 1 1 0 0 1 x x | || | | | | || | | | | |12|*| IDLE | 1 0 1 0 0 1 x x | || |*| IDLE | 1 1 1 0 1 0 x x | || | | | | || | | | | || |*| IDLE | 1 0 1 0 1 0 x x | || |*| IDLE | 1 1 1 0 1 1 x x | || | | | | || | | | | || |*| IDLE | 1 0 1 0 1 1 x x | || |*| IDLE | 1 1 1 1 0 0 x x | || | | | | || | | | | || |*| IDLE | 1 0 1 1 0 0 x x | || |*| IDLE | 1 1 1 1 0 1 x x | || | | | | || | | | | || |*| IDLE | 1 0 1 1 0 1 x x | || |*| IDLE | 1 1 1 1 1 0 x x | || | | | | || | | | | || |*| IDLE | 1 0 1 1 1 0 x x | |v |*| IDLE | 1 l 1 1 1 1 x x | || | | | | +==+=+========+=========================+ || |*| IDLE | 1 0 1 1 1 1 x x | || | | | | +==+=+========+=========================+ On Card Bus Data INPUT and Output --------------------------------- READ Registers -------------- The statis registers are not implemented as registers but as a multiplexed and buffered bus. The OCB_ARRS determines which status registers signals are put on the bus and OCB_CHIP_SEL_B(2) and LTCHD_WRITE_B enables or disables the output buffer. +---- Board_Status_1(7)---------| \ Board_Status_2(7)---------| \ Configuration_Status(7)---| \ Board_Control_1(7)--------| | Board_Control_2(7)--------| | Configuration_Control(7)--| | + . |8 bit | |\ . |wide |-DATA_OUT(0:7)-| \-OCB_DATA(0:7)- . |6:1 Mux| | / Board_Status_1(0)---------| | |/ Board_Status_2(0)---------| | +| Configuration_Status(0)---| / | Board_Control_1(0)--------| / | Board_Control_2(0)--------| / | Configuration_Control(0)--| / | +---- | || | +-------+ | OCB_ADRS(1:16,17)-------|Select | | |Logic | | +-------+ | | +-----+ | LTCHD_WRITE_B-----------| | | OCB_CHIP_SEL_B(2)-------| AND |--------------------+ +-----+ Each bit of the status bus is implemented in one macrocell. The bit for a status register is ANDed with its select signal to determine if it should be put on the bus. These AND terms are ORed together to determine if that bit of the Status bus is to be high or low. The bit of the status bus is buffered at the output of the macrocell. The AND of LTCHD_WRITE_B and OCB_CHIP_SEL_B(2) is used as the product term output enable (PTOE). Status_OCB_DATA(X) = [Board_Status_1(X) * BOARD_STATUS_1_SEL + Board_Status_2(X) * BOARD_STATUS_2_SEL + Configuration_Status(X) * CNFG_STATUS_SEL] CONTROL_OCB_DATA(X) = [Board_CONTROL_1(X) * BOARD_CONTROL_1_SEL + Board_CONTROL_2(X) * BOARD_CONTROL_2_SEL + Configuration_CONTROL(X) * CNFG_CONTROL_SEL] OCB_Output_Enable = OCB_CHIP_SEL_B(2) * LTCHD_WRITE_B There are 6 posible sources for OCB_DATA writes from the PAL. For the 8 bit wide bus, this means there are 48 bits needed for the data. There are individual select bits for each source and 2 control bits for the PTOE. This makes for a total of 56 needed inputs. A function block in the PAL can only input 54. There are 5 unpopulated bits in the status registers (1). If all possible addresses are considered, then OCB_DATA(0:7) will need to be split across 2 functional blocks. If at least 2 of the 5 unused bits are left out of address decoding then all of the status readout can be implemented in one functional block. All status bits considered ===================================================================================== Function Block 1 ---------------- +-----+ Board_Status_1(X)-------| | BOARD_STATUS_1_SEL------| AND |----+ +-----+ | +-----+ | +----+ Board_Status_2(X)-------| | +-----| | BOARD_STATUS_2_SEL------| AND |----------| OR |---STATUS_OCB_DATA(X) +-----+ +-----| | +-----+ | +----+ Configuration_Status(X)-| | | CNFG_STATUS_SEL---------| AND |----+ +-----+ Function Block 2 ---------------- +-----+ Board_Cotnrol_1(X)------| | BOARD_CONTROL_1_SEL-----| AND |----+ +-----+ | +-----+ | +----+ Board_Control_2(X)------| | +-----| | BOARD_CONTROL_2_SEL-----| AND |----------| OR |---CONTROL_OCB_DATA(X) +-----+ +-----| | +-----+ | +----+ Configuration_Control(X)| | | CNFG_CONTROL_SEL--------| AND |----+ +-----+ Function Block 1,2 or 3 ----------------------- +-----+ + STATUS_OCB_DATA(X)------| | |\ | OR |--DATA(x)----------| \ CONTROL_OCB_DATA(X)-----| | | /------OCB_DATA(X) +-----+ |/ +| +-----+ | !LTCHD_WRITE_B----------| | | | AND |--OCB_OUTPUT_ENABLE-+ !OCB_CHIP_SEL_B(2)------| | +-----+ Unused status bits not considered ===================================================================================== Function Block 1 ---------------- +-----+ Board_Status_1(X)-------| | BOARD_STATUS_1_SEL------| AND |----+ +-----+ | +-----+ | Board_Status_2(X)-------| | +---+ BOARD_STATUS_2_SEL------| AND |------+ | +-----+ | | +-----+ | | Configuration_Status(X)-| | | | +----+ CNFG_STATUS_SEL---------| AND |----+ | +-| | + +-----+ | +---| | |\ +-----| OR |-----| \ +-----+ +-----| | | /------OCB_DATA(x) Board_Cotnrol_1(X)------| | | +---| | |/| BOARD_CONTROL_1_SEL-----| AND |----+ | +-| | + | +-----+ | | +----+ | +-----+ | | | Board_Control_2(X)------| | | | | BOARD_CONTROL_2_SEL-----| AND |------+ | | +-----+ | | +-----+ | | Configuration_Control(X)| | | | CNFG_CONTROL_SEL--------| AND |--------+ | +-----+ | | +-----+ | !LTCHD_WRITE_B----------| | | | AND |--OCB_OUTPUT_ENABLE----+ !OCB_CHIP_SEL_B(2)------| | +-----+ Table 3 lists the source for the status bus bits. Table 3: Status register signal sources (1) Signal Source ----------------------------------- Board_Status_1(0) FPGA_0_STATUS(0) Board_Status_1(1) FPGA_0_STATUS(1) Board_Status_1(2) FPGA_0_STATUS(2) Board_Status_1(3) FPGA_0_STATUS(3) Board_Status_1(4) FPGA_1_STATUS(0) Board_Status_1(5) FPGA_1_STATUS(1) Board_Status_1(6) FPGA_1_STATUS(2) Board_Status_1(7) FPGA_1_STATUS(3) Board_Status_2(0) CRATE_STATUS(0) | Board_Status_2(1) CRATE_STATUS(1) | Board_Status_2(2) CRATE_STATUS(2) |INVERT Board_Status_2(3) CRATE_STATUS(3) | Board_Status_2(4) LAST_DAC_OUTPUT_DATA Board_Status_2(5) NC Board_Status_2(6) NC Board_Status_2(7) NC Configuration_Status(0) CNFG_INIT_B(0) Configuration_Status(1) CNFG_INIT_B(1) Configuration_Status(2) CNFG_BUSY_(0) Configuration_Status(3) CNFG_BUSY_(1) Configuration_Status(4) CNFG_DONE(0) Configuration_Status(5) CNFG_DONE(1) Configuration_Status(6) NC Configuration_Status(7) NC WRITE Registers --------------- The Control registers are alway enabled. The clock for the registers is the PAL_BX_CLOCK. The next state logic for the flip flops is the following: 1) Keep the current state if WRITE_TO_PAL is deasserted. 2) Keep the current state if the appropriate register selcect line is deasserted. 3) Keep the current state if OCB_WRITE_STRB is deasserted. 4) Update from OCB_DATA if WRITE_TO_PAL is asserted, OCB_WRITE_STRB is asserted, and the appropriate register select line is asserted. 5) The following is invalid and not considered. WRITE_TO_PAL deasserted, OCB_WRITE_STRB asserted and appropriate register asserted. This is invalid because if the register select line is asserted and OCB_WRITE_STRB is asserted, then WRITE_TO_PAL should also be asserted. Karnough Map positions for the Karnough Map next state logic conditions. next state logic Register OCB_WRITE Register OCB_WRITE Select _STRB Select _STRB 00 01 11 10 00 01 11 10 +----+----+----+----+ +----+----+----+----+ WRITE_ 00| | | | | WRITE_ 00| | | | | TO_PAL |1,2 |1,2 |1,5 |1 | TO_PAL | 0 | 0 | X | 0 | +----+----+----+----+ +----+----+----+----+ 01| | | | | 01-+--+----+| |+---- |1,2 |1,2 |1,5 |1 | || 1|| 1 || X ||1 | +----+----+----+----+ +|--|+---|+----+|---+ CURRENT 11| | | | | CURRENT 11|| 1|| 1 ||NEW ||1 | STATE |2 |2 |4 |3 | STATE -+--+----+|DATA|+---- +----+----+----+----+ +----+----+----+----+ 10| | | | | 10| | |NEW | | |2 |2 |4 |3 | | 0 | 0 |DATA| 0 | +----+----+----+----+ +----+----+----+----+ Logic to implement Karnough Map of next state logic. D = 4) OCB_DATA(X) * WRITE_TO_PAL * OCB_WRITE_STRB * REGISTER_SEL + SIGNAL_NAME * !REGISTER_SEL + SIGNAL_NAME * !OCB_WRITE_STRB Register Bit Example +-----+ OCB_DATA(X)------| | WRITE_TO_PAL-----| AND |----+ REGISTER_SEL-----| | | OCB_WRITE_SRTB---| | | +-----+ | +------------|--------------------+ | +-----+ | | +-| AND |--+ | | !REGISTER_SEL--|-| | | | | | +-----+ | | | | | | | | +-----+ | | | +-| AND |+ | | | !OCB_WRTIE_STRB--| || | | | +-----+| | | +----+ | | | +-| | | | +---| OR | +------+ | +-----| |----|D Q|-+-Signal Name +----+ | | PAL_BX_CLOCK----------------------------|> | +------+ References ---------- 1) See http://www.pa.msu.edu/hep/d0/ftp/run2b/l1cal/hardware/adf_2/general/ board_control_pal_description.txt 2) See http://www.pa.msu.edu/hep/d0/ftp/run2b/l1cal/hardware/adf_2/general/ adf_2_vme_addressing.txt 3) http://www.pa.msu.edu/hep/d0/ftp/run2b/l1cal/hardware/adf_2/general/ on_card_bus_description.txt ================================================================================ Text below this division is not needed any further ================================================================================ PAL resource allocation ----------------------- There are 94 I/O signals. See table 1. There are 66 inputs, two of which need to be input through a register. There are 35 outputs, 27 of which need to be latched with a register. The OCB_DATA signals are counted twice because they are considered both an input and an output. In neither direction do they need to be connected directly to a register. There are a total of 29 I/O signals that are directly connected to registers. There are 72 I/O signals that do not need to connect directly with the macrocell associated with their I/O pin, leaving these macrocells for other registers or combinitorial logic. There are 6 states in the state machine that implements the Board Conrol PAL. See Table 2. Between 3 and 6 registers can be used to implement this state machine. 6 registers will be used, one for each state, to make design, deguging and maintainance simple. Of the 144 available macrocells in the XC95144L PAL, 29 are used for I/O registers and 6 are used for the state machine. This leaves 109 for combinational logic. Table 1: I/O Signals --------------------- Quiescent Signal In/Out In Out Register State ---------------------------------------------------------------------------- PAL_BX_CLOCK In 1 X DRV_CRATE_TO_SCLD(0:1) Out 2 X 0? SER_DESKEW_B Out 1 X 1? SER_DC_BALANCE Out 1 X 0 ADC_ENABLE Out 1 X 0 FPGA_0_STATUS(0:3) In 4 X FPGA_1_STATUS(0:3) In 4 X DRV_CRATE_STATUS(0:3) Out 4 X 0 CRATE_STATUS_B(0:3) In 4 X DATA_TO_FIRST_DAC_INPUT Out 1 X DAC_SERIAL_DATA_CLOCK Out 1 X 0 DAC_CHIP_SELECT_B Out 1 X 1 LAST_DAC_OUTPUT_DATA In 1 ? X OCB_ADRS(1:23) In 23 X LTCHD_AM(0:5) In 6 X LTCHD_IACK_B In 1 X LTCHD_WRITE_B In 1 X VME_LTCH_CLK Out 1 X 0 VME_GEO_B(0:4) In 5 X VME_SYSRESET_B In 1 X (Debounce) X (Input) RCVD_DS1 In 1 X DRV_DTACK Out 1 X 0 OCB_DATA(0:7) In/Out 8 X DATA_BUF_DIR Out 1 X 1 (Read) DATA_BUF_ENB_B Out 1 X 1 OCB_CHIP_SEL_B(0:2) Out 3 X 1 OCB_WRITE_STRB_B Out 1 X 1 OCB_DIRECTION Out 1 X 1 (Read) CNFG_CCLK Out 1 X 0 CNFG_RDWR_B Out 1 X 1? CNFG_PROG_B(0:1) Out 2 X 1? CNFG_CS_B(0:1) Out 2 X 1? CNFG_INIT_B(0:1) In 2 X CNFG_BUSY(0:1) In 2 X CNFG_DONE(0:1) In 2 X --------------------------------------------------------------------------- Dependencies Signal # Singals ---------------------------------------------------------------------------- DRV_CRATE_TO_SCLD(0:1) 9 OCB_DATA(X) OCB_ADRS(1:4) OCB_CHIP_SEL_B(2) LTCHD_WRITE_B SER_DESKEW_B 9 OCB_DATA(X) OCB_ADRS(1:4) OCB_CHIP_SEL_B(2) LTCHD_WRITE_B SER_DC_BALANCE 9 OCB_DATA(X) OCB_ADRS(1:4) OCB_CHIP_SEL_B(2) LTCHD_WRITE_B ADC_ENABLE 9 OCB_DATA(X) OCB_ADRS(1:4) OCB_CHIP_SEL_B(2) LTCHD_WRITE_B DAC_CHIP_SELECT_B 9 OCB_DATA(X) OCB_ADRS(1:4) OCB_CHIP_SEL_B(2) LTCHD_WRITE_B CNFG_RDWR_B 9 OCB_DATA(X) OCB_ADRS(1:4) OCB_CHIP_SEL_B(2) LTCHD_WRITE_B CNFG_PROG_B(0:1) 9 OCB_DATA(X) OCB_ADRS(1:4) OCB_CHIP_SEL_B(2) LTCHD_WRITE_B CNFG_CS_B(0:1) 9 OCB_DATA(X) OCB_ADRS(1:4) OCB_CHIP_SEL_B(2) LTCHD_WRITE_B DRV_CRATE_STATUS(0:3) 9/? OCB_DATA(X) OCB_ADRS(1:4) OCB_CHIP_SEL_B(2) LTCHD_WRITE_B Or from a State in future implementations OCB_DATA(0:7) 8 BOARD_STATUS_1(X) BOARD_STATUS_1_SEL BOARD_STATUS_2(X) BOARD_STATUS_2_SEL CONFIGURATION_STATUS(X) CNFG_STATUS_SEL BOARD_CONFIG_1(X) BOARD_CONFIG_SELECT_1 BOARD_CONFIG_2(X) BOARD_CONFIG_SELECT_2 CONFIGURATION_CONTROL(X) CNFG_CONTROL_SEL LTCHD_WRITE_B OCB_CHIP_SEL_B(2) DATA_TO_FIRST_DAC_INPUT 2 OCB_DATA(0) LOAD_DACS DAC_SERIAL_DATA_CLOCK 4 WRITE_CLOCK LOAD_DACS CONFIGURE_FPGAS PAL_BX_CLOCK VME_LTCH_CLK 6 LATCH_1_STATE IDLE_STATE, LATCH_2_STATE, READ_1, WRITE_1, WRITE_2 DRV_DTACK 6 LATCH_1_STATE, LATCH_2_STATE IDLE_STATE, READ_1, WRITE_1, WRITE_2 DATA_BUF_DIR/ 2 LATCHD_WRITE_B OCB_DIRECTION VALID_CYCLE DATA_BUF_ENB_B 1 VALID_CYCLE OCB_CHIP_SEL_B(0:2) 15 VALID_CYCLE OCB_ADRS(0,5:17) OCB_WRITE_STRB_B 5 WRITE_CLOCK LTCHD_WRITE_B LOAD_DACS CONFIGURE_FPGAS PAL_BX_CLOCK CNFG_CCLK 4 WRITE_CLOCK CONFIGURE_FPGAS LOAD_DACS PAL_BX_CLOCK VALID_CYCLE 18 LTCHD_IACK_B LTCHD_AM(0:5) VME_GEO_B(0:4) OCB_ADRS(18:23) Internal Dependencies Signals # Signals --------------------------------------------------------------------------- LOAD_DACS 2 OCB_CHIP_SEL_B(2) ENABLE_LOADING_DACS WRITE_CLOCK 6 WRITE_1 IDLE_STATE, LATCH_1_STATE, LATCH_2_STATE, READ_1, WRITE_2 CONFIGURE_FPGAS 6 OCB_CHIP_SEL_B(2) ENABLE_FPGA_CONFIGURATION OCB_ADRS(1:4) BOARD_STATUS_SETECT_1 5 OCB_CHIP_SEL_B(2) OCB_ADRS(1:4) BOARD_STATUS_SELECT_2 5 OCB_CHIP_SEL_B(2) OCB_ADRS(1:4) CNFG_STATUS_SELECT 5 OCB_CHIP_SEL_B(2) OCB_ADRS(1:4) BOARD_CONFIG_SELECT_1 5 OCB_CHIP_SEL_B(2) OCB_ADRS(1:4) BOARD_CONFIG_SELECT_2 5 OCB_CHIP_SEL_B(2) OCB_ADRS(1:4) CNFG_CONTROL_SELECT 5 OCB_CHIP_SEL_B(2) OCB_ADRS(1:4) IDLE_STATE 9 IDLE_STATE, LATCH_1_STATE, LATCH_2_STATE, READ_1, WRITE_1, WRITE_2, RCVD_DS1, VALID_CYCLE, LTCHD_WRITE_B LATCH_1_STATE 9 IDLE_STATE, LATCH_1_STATE, LATCH_2_STATE, READ_1, WRITE_1, WRITE_2, RCVD_DS1, VALID_CYCLE, LTCHD_WRITE_B LATCH_2_STATE 9 IDLE_STATE, LATCH_1_STATE, LATCH_2_STATE, READ_1, WRITE_1, WRITE_2, RCVD_DS1, VALID_CYCLE, LTCHD_WRITE_B READ_1 9 IDLE_STATE, LATCH_1_STATE, LATCH_2_STATE, READ_1, WRITE_1, WRITE_2, RCVD_DS1, VALID_CYCLE, LTCHD_WRITE_B WRITE_1 9 IDLE_STATE, LATCH_1_STATE, LATCH_2_STATE, READ_1, WRITE_1, WRITE_2, RCVD_DS1, VALID_CYCLE, LTCHD_WRITE_B WRITE_2 9 IDLE_STATE, LATCH_1_STATE, LATCH_2_STATE, READ_1, WRITE_1, WRITE_2, RCVD_DS1, VALID_CYCLE, LTCHD_WRITE_B Diagram 1 --------- Signal Dependence Hierarchy ============================================================================= LTCHD_IACK_B----------------+ | LTCHD_AM(0:5)----->VALID_AM-+ |-->VALID_CYCLE-+->DATA_BUF_ENB_B VME_GEO_B(0:4)--+ | | |->THIS_CARD+ | OCB_ADRS(18:23)-+ | | +---------------------------------------------+ | | LTCHD_WRITE_B------+ | | | +->DATA_BUF_DIR | | | +->OCB_DIRECTION | | +-VALID_CYCLE------+-+ | | | +-->OCB_CHIP_SEL_B(0)--------+ +-->OCB_CHIP_SEL_B(1)------+ | +-->OCB_CHIP_SEL_B(2)--+ | | | | | | OCB_ADRS(0,5:17)-+ +---+-+--->OCB_WRITE_STROBE_B | OCB_ADRS(1:4)-------------------------+-+--->CONFIGURE_FPGAS-->CNFG_CCLK | | ENABLE_FPGA_CONFIGURATION-------------+-+--->CNFG_STATUS_SEL | | +-+--->BOARD_STATUS_1_SEL | | +-+--->BOARD_STATUS_2_SEL | | ENABLE_LOADING_DACS-------------------+-+->LOAD_DACS-+->DAC_CHIP_SELECT_B | OCB_DATA(0)------------------------------------------+->DATA_TO_FIRST_DAC_INPUT READ_1 + WRITE_1---------------------------------------->DRV_DTACK ENABLE_FPGA_CONFIGURATION => CNFG_PROB_B ENABLE_LOADING_DACS => DAC_SERIAL_DATA_CLOCK ENABLE_LOADING_DACS => DAC_SELECT_B CRATE_STATUS_B(0:3)---------------------+ | Future_State Not implemented yet--------+-------------->DRV_CRATE_TO_SCLD(0:1) SYSRESET_DEBOUNCED ------------------ Scope: Input Power Up:0 Quiescent:0 Macrocells:3 When the VME_SYSRESET_B signal is asserted, the state machine is forced into the idle state and all signals are set to their quiescent state. To protect from noise on the VME_SYSRESET_B line reseting the Board Control PAL with a nano second spike, a debounce circuit will be used to confirm the signal was asserted for at least one cycle. See timing diagram http://...... +----+ +------|NOT |------+ | +----+ | +---+ | +-----+ +---| | VME_SYSRESET_B-+------|D1 Q1| +---|AND|---+ | | __| | +-| | | +-----+ PAL_BX_CLOCK----------+---|> Q1|-----+ | +---+ +-|D3 Q3|-SYSRESET_DEBOUNCED | | +-----+ | | __| | +-----------------|-----------|> Q3| | | +-----+ | +-----+ | | 1-|D2 Q2| | | | | __| | +------|> Q2|-------+ | | R | | +-----+ | | +------+ Macrocell Usage --------------- A macrocell can input 5 ANDed terms and OR them together. If more than 5 ANDed terms need to be ORed together to define a signal then more than one macrocell needs to be used to implement the signal. A macrocell in the XC95144xl can input OR terms from 2 other macrocells in the same functional block, so that upto 10 AND terms can be ORed together in 2 macrocells and upto 15 AND terms can be ORed together in 3 macrocells. All singals in this design use 15 or less AND terms. If a signal needs to only AND terms together then a macrocell does not need to be used because the signal can be created in each macrocell that uses it. All outputs need at least one macrocell. Macrocell Usage Summary ----------------------- +-----------------+----------+--------------------------------------+ |Condition |Macrocells| Example | | | Needed | | +-----------------+----------+--------------------------------------+ |1 ORed term | 0 | !x*y*z | |2-5 ORed terms| 1 | x*y + w*z | |6-10 ORed terms| 2 | x*y + a*b + c*d*e + f + !a*d + z | |11-15 ORed terms| 3 | x + z*!y + ...at least 9 more terms | |Output Signal | 1 | | +-----------------+----------+--------------------------------------+