"Filter" Description and Issues --------------------------------- Initial Rev: 25-MAY-2005 Current Rev: 8-DEC-2005 What most Physics People have called the "Filter" is a small piece of the logic in the ADF-2 Data Path FPGA. The "Filter" represents less than 10% of the implemented logic in this FPGA. The purpose of the "Filter" is the important function of converting raw ADC data into the best estimate of the energy deposited in that Trigger Tower section (EM or HD) by the Tevatron beam crossing. The intent of this document is to describe the 4 Filters that have been implemented and to describe the remaining issues about how to best "Filter" the ADC data into Et values. Note that the bulk of the logic in the Data Path FPGA is independent of what "Filter" has been implemented in that version of the FPGA. The control and status register interface that the Data Path FPGA presents to the Trigger Control Computer is, by design, independent of what "Filter" has been implemented in a given version of the Data Path FPGA. A block diagram of the principal signal flow through the Data Path FPGA for a single Trigger Tower is shown in: www.pa.msu.edu/hep/d0/ftp/run2b/l1cal/hardware/adf_2/drawings/ data_path_fpga_signal_processing.pdf An overall written description of the Data Path FPGA is presented in: www.pa.msu.edu/hep/d0/ftp/run2b/l1cal/hardware/adf_2/general/ adf_2_data_path_fpga_description.txt A detailed description of the control and status registers instanced in the Data Path FPGA, i.e. the interface to the Trigger Control Computer is presented in files in the Data Path firmware directories. The "Filter" works on the energy "E" signal that it gets from the ADC. The output of the Filter is also in terms of energy "E". Before being sent to the TAB cards the "E" output signal from the Filter passes through the Et Lookup Memory so that the data which is sent to the TAB cards is in terms of the Et energy. To make this note a complete description of the digital processing that is done of the ADF-2 card a description of the Et Lookup Memory is also included in the note. The Et Lookup Memory is located after the Filter and is not part of the Filter. This Filter description document is divided into a number of sections: Description of the Filters Filter Input Values - Technical Details Filter Internal Values - Technical Details Filter Output Values - Technical Details Filter Implementation - Technical Details Et Lookup Memory - Output Data and Technical Details Description of the Filters -------------------------- The first Filter design will provide as the Et Filter output the value of the single ADC sample that was taken at the time of the peak of the BLS signal. The intent of this Filter is that: - Its output data should be simple to understand. - It provides a baseline for comparing the performance of the more complicated Filter. - Of the 4 Filters it is most sensitive to timing adjustment (ADC sampling wrt BLS signals) and thus provides a tool to study and verify this timing. The second Filter design will provide as the Et Filter output the average of the 2 or 4 ADC samples that were taken nearest to the time of the peak of the BLS signal. The intent of this Filter is to use this high frequency cutoff to improve the Et signals sent to TAB. The peak of the BLS signal is fairly flat and basing the Et output on the average of 2 or 4 ADC samples will remove high frequency noise and remove the effect of event to event jitter in the location of the peak of the BLS signal wrt the time of the actual beam crossing. The third Filter design will provide as its Et Filter output the difference between the average of 2 or 4 samples taken right before the beginning of the rise of the BLS signal and the average of the 2 or 4 samples taken at the peak of the BLS signal. The intent of this Filter is to add low frequency cutoff to remove the effect of BLS baseline shifts from the Et signals that are sent to the TAB. These first 3 Filter designs will all be implemented with one straight forward logic design in the Data Path FPGA. That is there is a single version of the Data Path FPGA which implements all 3 of these Filters. The effect of high frequency filtering the peak of the BLS signal and the effect of making the difference between the BLS signal right before the Tevatron energy deposition and the peak of the BLS signal can be judged by looking at samples of the BLS analog signals that we have on the web. Clearly the baseline of the BLS signal moves around at low frequency so the differencing operation should provide a better Et value. The intent of the forth and final version of the "Filter" is to take into consideration the effect of a strong Et signal from beam crossing "N" while the Filter is calculating the Et value for beam crossing "N+1". Note that this version of the word "pile-up" is not a common problem at the current D-Zero luminosities but careful treatment of this condition will prevent making gross mistakes in the Et value and may provide epsilon better overall L1 triggering. A significant energy deposition in the previous crossing has a number of effects on the measurement of Et in the current beam crossing. - Clearly the baseline has moved and is continuing to move during the period that the BLS signal builds up to its peak value for this crossing. - The time at which the BLS signal reaches its peak value for this crossing will shift by some amount. - The response of the BLS signal driver circuit may be different right after it has just handled a large signal on the previous crossing. Once again looking at samples of the BLS signals give one some understand of the magnitude of these different effects. Filter Input Values - Technical Details --------------------------------------- - The Et value per LSBit in the raw ADC data is Eta dependent. - This scale is set partially by the analog summing circuits in the BLS cards, partially set by the fraction of the BLS signal that makes it through the BLS Cable Transition system, and partially by the species of ADF-2 card. - The following document gives the details about BLS analog signal amplitude vs Et and about the species of ADF-2 cards. www.pa.msu.edu/hep/d0/ftp/run2b/l1cal/hardware/adf_2/general/ adf_2_bls_input_signals.txt - The following table represents the best current understanding of the raw ADC Et value per LSB as a function of Eta for both EM and HD sections of the Trigger Towers. This is based on the Summer 2003 calibration by Bob Kehoe et al and upon the measured signal loss going through the BLS Cable Transition System. Expected ADF-2 ADC Response ------------------------------ ADF-2 EM GeV Et per HD GeV Et per TT Eta Species EM ADC LSBit HD ADC LSBit ------ ------- ------------- ------------- 1 A 0.1141 GeV 0.1381 GeV 2 A 0.1095 0.1328 3 A 0.1019 0.1138 4 A 0.0910 0.1031 5 B 0.1063 0.1544 6 B 0.0923 0.1459 7 B 0.0667 0.0651 8 B 0.0597 0.0732 9 C 0.1245 0.1368 10 C 0.1032 0.1148 11 C 0.0852 0.0854 12 C 0.0692 0.0696 13 D 0.0756 0.0765 14 D 0.0615 0.0623 15 D 0.1840 0.1962 16 D 0.1506 0.1606 17 D 0.1096 0.1087 18 D 0.0706 0.0584 - The ADC digital output is offset from zero. That is, with a BLS input signal that represents zero GeV deposited in the Calorimeter, the digital output from the ADC will not be zero but rather is will be a small number that represents about 5% of the full scale range of the ADC. - This offset from zero of the ADCs is called their "Zero Energy Response". - The Zero Energy Response of the ADCs is controlled by the Pedestal DAC's on the ADF-2 cards. - The Zero Energy Response of the ADCs is a constant value for all channels. - Offsetting the ADC by 50 counts, i.e. zero energy deposited in the Calorimeter results in ADC output of 50 is enough to allow all channels to easily see -2.0 GeV of negative noise. Some channels, those that are "less sensitive", i.e. require more GeV per ADC count, could have a smaller ADC offset but the system does not actually gain much/any dynamic range by making the ADC offset a function of TT Eta. Filter Internal Values - Technical Details ------------------------------------------ - All of the internal arithmetic is done as "unsigned binary" in a 16 bit wide accumulator. - Both addition and subtraction operations are used so cases that result in either carry-out or borrow-out need to be tested for. - Examples of cases that need to be tested for: If the BLS signal is a downward sloping baseline with no energy deposit signal then subtracting the pre beam crossing value from the post beam crossing value will result in a number less than zero, i.e. borrow-out. This will set high order bits and look like a large positive energy deposit. This case must be tested for and handled correctly. The general point of the above example is that even though the raw ADC input data is offset from zero, when you do the operation of subtracting the before beam crossing value from the after beam crossing value, this offset is removed. If the BLS signal starts out with negative noise values before the beam crossing and then has full scale ADC values at the peak of the after beam crossing samples, then when you do the operation of subtracting the before beam crossing value from the after beam crossing value, the data can carry-out, resulting in an apparently very small Et signal. This case must be tested for and handled correctly. - Saturating limit values must be enforced by the time an address is sent to the Et Lookup Memory. - Internally all arithmetic is 16 bits wide. The raw ADC data is 10 bits wide. "Averaging" data, e.g. summing 4 ADC samples and dividing by 4 is accomplished by shifting the data at the output of the summer. - The data that is available to the Filter when it is calculating the energy value for beam crossing "N" is the following: The Filter output value for beam crossing "N-1". 12 samples of raw ADC data which cover the range from before the BLS signal begins to rise due to the energy deposit of beam crossing "N" until 2 ADC samples after the peak of the BLS signal due to the energy deposit of beam crossing "N". - For a given channel the energy value of the LSBit of the address that is sent to the Et Lookup Memory will be the same as the energy value of the LSBit of the ADC data for that channel. Filter Output Values - Technical Details ---------------------------------------- - The 10 bit wide energy value that comes out of the Filter goes to the ET Lookup Memory where it functions as the address input to that lookup memory. - The energy value per LSBit of the output data from the Filter is the same as the energy value per LSBit of ADC data for a given channel. - The offset from zero, i.e. the zero energy response, of the output data from the Filter is the same as the zero energy response of the data from the ADC. By convention this is set to 50 decimal counts. Filter Implementation - Technical Details ----------------------------------------- - A drawing of the computational part of the Filter is shown in ?? - Points to note about the operation of the computational part of the Filter. ADC Data only enters the Filter on the X8_Clock edges that are selected by X4_Clk_Enb. Recall that X4_Clk_Enb is lined up with First_X8_Edge_Enb. The output from the computational part of the Filter must be setup and stable at the address input to the Et Memory Lookup which is clocked by X8_Clock edges selected by the Mid_X8_Edge_Enb signal. An implication of the above two points is that it only makes sense to clock the computational part of the Filter on X8_Clock edges that are selected by the X4_Clk_Enb signal. The Filter only needs to make a new output once every 3 ticks. The other 2 ticks will have a Zero Energy Response value of $8 sent out to the TABs as controlled by the TT Cell Output Mux. The adjustment of the delay block in front of the Filter must be set so that the last ADC sample that you want to use for the calculation of the Et for tick "N" enters the Filter no later than the X8_Clock edge selected by the X4_Clk_Enb signal right before the Mid_X8_Edge_Enb signal that enables the Et Lookup Memory to cycle to get the Et value for tick "N". Recall: In the FPGA logic, the edges of the X8_Clock that are selected by X4_Clock_Enb are also selected by First_X8_Edge_Enb and also by Mid_X8_Edge_Enb, i.e. these three enable signals are in "sync". The control signals, e.g. Live_BX and Beginning_of_Turn change states on the edges of the X8_Clock that are selected by the First_X8_Edge_Enb. That is, the first edge of the X8_Clock for which one of these control signals is active is the edge after First_X8_Edge_Enb signal was active. List of the sub-tick numbers on which these signals are active - shown in cronological order. X4_Clock_Enb: 0, 2, 4, 6 First_X8_Edge_Enb: 0 Mid_X8_Edge_Enb: 4 Control e.g. Live_BX: 1, 2, 3, 4, 5, 6, 7, 0 - ADF-2 Timing described in table form The Et Look-Up Memories receive an 11 bit address from the computational section of the Filter. These lookup memories are clocked by edges of the X8_Clock that are selected by the First_X8_Edge_Enb signal. As shown in the next step, this gives a full 132 nsec for the Et lookup to take place and the resulting Et data from the memory to flow through the Output Mux and settle in the Output Shifter. Data from the Et Lookup Memory, that has passed through the Output Multiplexer, is clocked into the Output Shifter on an edge of the X8_Clock that is selected by the First_X8_Edge_Enb signal. Notes: For the Output Shifter to ingest data from the Filter it must be clocked in on an edge of the X8_Clock that is selected by the First_X8_Edge_Enb signal for a tick when the Live_BX signal was asserted. If monitoring data is being recorded in the Final Output Memory Block then it is written on the same edges of the X8_Clock as selected by the First_X8_Edge_Enb signal as are used to load this data into the Output Shifter. Two edges of the X8_Clock later, to allow time for the generation of the parity bit, the first of the data from the Output Shifter is clocked into the Channel Link transmitter chips. The transmission of this frame of ADF to TAB data begins at this point and ends 132 nsec later. - A detailed description of the timing of the Data Path FPGA is presented in the description of the SCLD FPGA in its firmware directory. - Filter Control Signals FILTER_RESET This enable type signal has priority over all other inputs. When asserted it causes the value in the accumulator to be replaced by all zeros on the next edge of the X8_Clock. Filter_Reset does not require the Filter_Clock_Enable signal to be active for it to operate. FILTER_LOAD_CONSTANT This enable type signal causes the value in the accumulator to be replaced by a hardwired constant value on the next edge of the X8_Clock. The hardwired constant value that is Loaded into the accumulator is set in firmware. The Filter_Load_Constant signal does not require the Filter_Clock_Enable signal to be active for the Load operation to take place. The Filter_Load_Constant signal can be used to "pre-load" the accumulator with a large enough positive value so that it can not underflow during the subsiquent processing cycle. FILTER_ADD When the Filter_Add signal is asserted AND the Filter_Clock_Enable signal is active then on the next edge of the X8_Clock the value at the input to the Filter is added to the accumulator. This is the addition operation. When the Filter_Add signal is negatted AND the Filter_Clock_Enable signal is active then on the next edge of the X8_Clock the value at the input to the Filter is subtrated from the accumulator. This is the subtraction operation. The Filter_Add signal is an enable type signal. FILTER_CLOCK_ENABLE The Filter_Clock_Enable is an enable type signal that must be asserted for either an addition or subtraction operation to take place. FILTER_SAVE_OUTPUT The Filter_Save_Output is an enable type signal that causes the current output from the Filter to be captured in a latch on the next edge of the X8_Clock. Note that the value that is captured is not really the output of the full "Filter", i.e. it is not data taken from the output of the Et Lookup Memory Block, but rather the value that is captured is the output from the Filter's accumulator, i.e. the address to the Et Lookup Menory Block. FILTER_USE_SAVED_OUTPUT The Filter_Use_Saved_Output is an enable type signal that causes the previously saved output value from the Filter to be loaded into the accumulator Et Lookup Memory - Output Data and Technical Details ---------------------------------------------------- - Note that the definition of the output data from the Et Lookup Memory is also the definition of the Et data that is sent to the TAB cards for "Live Beam Crossings" by the ADF-2 cards. - The input data (address) to the Et Lookup Memory is the 10 bit wide energy signal output data from the Filter. - The 8 bit Et data that comes out of the Et Lookup Memory and sent to the TAB has the following scale: Zero GeV of Et is represented by 0x08 The most negative value is represented by 0x00 - 2.0 GeV The most positive value is represented by 0xff + 61.75 GeV The scale is 0.25 GeV per LSBit. All Trigger Towers, both the EM and HD sections, will provide Et data to the TAB at the same scale. - The limiting Et values are saturating. That is: If the Et value calculated from the BLS signal is more negative than -2.0 GeV the signal sent to the TAB will be 0x00. If the Et value calculated from the BLS signal is more positive than +61.75 GeV the signal sent to the TAB will be 0xff. - Et Data for Live and for Non-Live Beam Crossings: There are 159 "Ticks" i.e. periods of 132 nsec or 7 RF Buckets, in an Accelerator Turn. These tick are numbered 1:159 and are often referred to as "beam crossings" With the current Tevatron beam structure only 36 of these 159 ticks are "Live Beam Crossings", i.e. actually have proton anti-proton bunches crossing in the center of D-Zero. For details and tick numbering see: www.pa.msu.edu/hep/d0/ftp/l1/framework/timing/ scl_frame_description.txt The ADF-2 Cards send Et data to the TAB cards for all 159 ticks in a turn of the accelerator. For the 123 ticks in a turn that are not "Live Crossings" the Et values sent to the TAB will be all 0x08 i.e. zero Et energy. For the 36 ticks in a turn that are "Live Crossings" the Et values sent to the TAB will be the output data from the Et Lookup Memories. The address input to the Et Lookup Memories is the Filtered energy data based on the BLS signals. Switching between sending the fixed 0x08 data for "Non-Live Beam Crossings" and sending the output of the Et Lookup Memory for "Live Beam Crossings" is taken care of by the Output Multiplexer in the Data Path FPGAs on the ADF-2 cards. The BX_Number that is sent to the TAB, as part of a frame of ADF to TAB Et data, is the number of the accelerator beam crossing that caused the energy deposits in the Calorimeter that are represented by the Et values in this frame of data. - The Et Lookup Memories are 2k locations long, i.e. they are addressed by an 11 bit wide value. At this time only the lower 1024 locations in the Et Lookup Memories will by used. On the hardware side of these dual port memories use of only the lower 1024 locations is enforced by using a 10 bit wide output from the Filter which is connected to the 10 low order bits of the A Port Address to the memory. The 11th address line, i.e. the highest order address line, to the A Port of the Et Lookup Memories is tied low in the hardware. On the VME access B Port of the memory, TCC has access to all 2048 locations in the Et Lookup Memories. It is suggested that TCC never write into the top half of the memory. The Data Path FPGA has been designed so that at power up all 2048 locations in the Et Lookup Memory will contain the data 0x00. - The data in each Et Lookup Memory is defined by two simple parameters and 3 constraints. These are: The Et Lookup Memory data is monotonic but not strictly monotonic. Moving up in addresses, once the data reaches $ff then it remains at $ff for all higher addresses. Moving down in addresses, once the data reaches $0 then it remains at $0 for all lower addresses. The data is defined by a Slope which is a floating point value. The data is defined by the address that corresponds to zero Et energy. This is an integer value. The data stored at this address will be $08. - Note that, unlike in Run I, the Et Lookup Memories do not include a Symmetric Low Energy Cut.