ADF-2 On Card Bus ---------------------- Original Rev. 14-APR-2004 Most Recent Rev. 19-APR-2004 This file is a description of the "On Card Bus" used on the ADF-2 circuit board. The On Card Bus is the path that allows VME communication with registers and memories in the ADF-2's Board Control PAL and in its FPGA's. All net names used for the On Card Bus begin with "OCB". The intent of the design of the On Card Bus is to make it: easy to implement FPGA based registers and memories that connect to it, to make its I/O cycles fail safe, to make it very easy to understand, and to minimize the logic resources that are involved with the connection to the bus. For the On Card Bus, Read and Write are defined with respect to the Trigger Control Computer. The On Card Bus is a synchronous bus. Target registers and memories on the ADF-2 card must be able to complete read and write cycles within a fixed (very generous) amount of time. The ADF-2 card supports only A24 D16 access. The 2 Address Modes to which it will respond are: Standard Non-Privileged Data and Standard Supervisory Data. A A A A A A M M M M M M hex Address mode 5 4 3 2 1 0 code ------------ ----------- ---- Standard Non-Privileged Data Access 1 1 1 0 0 1 39 Standard Supervisory Data Access 1 1 1 1 0 1 3D All VME A24 D16 cycles that correctly target the VME Address range covered by a given ADF-2 card will return DTACK* to the VME Bus Master even if there is no register or memory present at that address on the ADF-2 card. DTACK* is generated by the VME Bus Interface section of the Board Control PAL. The organization of VME address in the ADF-2 crate is covered in the document: www.pa.msu.edu/hep/d0/ftp/run2b/l1cal/hardware/adf_2/general/ adf_2_vme_addressing.txt The On Card Bus data path is 16 bits wide. Not all registers or memories that are connected to the On Card Bus need to work with all 16 bits. TCC's management of resources connected to the On Card Bus will include understanding how many bits wide each resource is and which bits in a given resource are Read only and which are Read/Write. All On Card Bus signals go to defined levels at the end of an I/O cycle to a given ADF-2 card or remain at defined quiescent levels on the ADF-2 cards that were not the target of that VME cycle. No On Card Bus signals are ever left floating, i.e. it is CMOS safe. On-Card Bus Specification ------------------------- The On-Card Bus is composed of the following 5 signals: Input to Output from targets Net Name on ADF-2 Function -------------- ----------- ----------------------------------------- OCB_ADRS(1:23) In These 23 signals are the latched copy of the A24 VME Address lines. These signals only update at the time of the falling edge of VME DS1* signal. Only OCB_ADRS(1:16) are passed to the FPGA's on the ADF-2 card. The higher order 7 address lines are matched with the Geographic Address of the ADF-2 card and used to select which OCB_CHIP_SEL_B(n) signal to assert, i.e. which FPGA or registers internal to the Board Control PAL itself is the target of the I/O cycle. Note that internal to the Board Control PAL it has its own OCB_CHIP_SEL_B line to "wake it up" when the target of the I/O cycle is within the address block reserved for registers within the Board Control PAL. This OCB_ADRS lines are bussed to all devices on the ADF-2 card that are connected to the On Card Bus. OCB_DATA(0:15) In/Out These signals are the 16 bit wide data bus. They default high when no one is driving them. This OCB_DATA lines are bussed to all devices on the ADF-2 card that are connected to the On Card Bus. If a given device that is connected to the On Card Bus contains only 8 bit wide resources then it only needs to connect to the 8 low order OCB_DATA lines. OCB_CHIP_SEL_B(n) In These "chip select bar" signals select a given device as the target for the I/O cycle. These signals are generated in the VME to On Card Bus Interface section of the Board Control PAL by decoding the VME address lines, using the Geographic Address of the ADF-2 card, and breaking the address space up into blocks as defined in the adf_2_vme_addressing.txt document that was referenced above. These "chip select bar" signals are distributed "radially" to all devices on the ADF-2 card that are connected to the On Card Bus. The quiescent state of the "chip select bar" signals is all HIGH. At the end of an I/O cycle on the ADF-2 card that was the target of the VME cycle, all OCB_CHIP_SEL_B(n) signals return HIGH. If a given ADF-2 card was not the target of the VME cycle then none of its OCB_CHIP_SEL_B(n) signals is ever asserted during the cycle. Only a single OCB_CHIP_SEL_B signal is ever asserted at a given time. OCB_CHIP_SEL_B(0) indicates that FPGA "F0" is the target of the I/O cycle OCB_CHIP_SEL_B(1) indicates that FPGA "F1" is the target of the I/O cycle OCB_CHIP_SEL_B(2) indicates that a register within the Board Control PAL itself is the target of the I/O cycle OCB_DIRECTION In This signal differentiates writes from reads on the On Card Bus. It is LOW for Write cycles and HIGH for Read cycles. This signal is generated by the VME to On Card Bus Interface. This signal is bussed to all devices on the ADF-2 card that are connected to the On Card Bus. The quiescent state of this signal is HIGH (Read). OCB_WRITE_STRB_B In This is the low active write strobe signal that is generated by the VME to On Card Bus interface section of the Board Control PAL. This signal is bussed to all devices on the ADF-2 card that are connected to the On Card Bus. The leading (falling) edge of this active-low signal stores data in the selected register during write cycles. This signal is not asserted during read cycles. The quiescent state of this signal is HIGH. On Card Bus Rules and Timing: ------------------------------ 1. All devices should fully decode their address lines. 2. No device may drive data onto the OCB_DATA bus unless OCB_DIRECTION is HIGH. 3. No device may drive data onto the OCB_DATA bus unless its OCB_CHIP_SEL_B signal is in the active state. 4. During a Read cycle, from the time that a device learns that it has been selected (by finding its OCB_CHIP_SEL_B signal is in the active state) until it begins driving the required data onto the OCB_DATA bus is 132 nsec maximum. 5. During a Write cycle, no device should absorb data from the OCB DATA bus unless its OCB_CHIP_SEL_B signal is in the active state. 6. During a Write cycle, the OCB_ADRS, OCB_DATA, OCB_DIRECTION, and OCB_CHIP_SEL_B will be asserted and stable for 132 nsec before a 132 nsec long OCB_WRITE_STRB_B is issued. These signals will continue to remain stable for 132 nsec after the conclusion of the active OCB_WRITE_STRB_B pulse.