SCLD and ADF Crate Control Signals Distribution ------------------------------------------------- Original Rev. 28-APR-2004 Most Recent Rev. 9-JAN-2006 Introduction ------------ The Serial Command Link Distributor Card (SCLD) is connected to the SCL Hub End Crate of the L1 Trigger Framework by the standard set of one SCL coax cable and one associated Status Cable. cf. http://www.pa.msu.edu/hep/d0/l1/scl.html for SCL information. The SCLD Card carries SCL timing and control information to all four separate ADF Crates, and reports status information back to the SCL Hub End. In each ADF Crate one of the twenty ADF-2 cards, called the Crate Maestro ADF-2 Card in Slot #11, is linked to the SCLD card via one dedicated cable that carries 8 LVDS signals. In each crate the Maestro ADF-2 Card drives all SCLD timing and control signals onto a set of VME-64X Reserved Bus Lines in the VME backplane. All twenty ADF-2 Cards in a crate receive the timing and control signals that control their operation from these backplane Reserved Bus Lines There is only one SCLD Card in the Run IIb L1CAL ADF sub-system. This 6U VME card will be located in a separate VME crate shared with other TAB/GAB control cards. The SCLD Card has no connections to the VME bus and only takes power from its host VME crate. cf. l1caliib_communication.gif in http://www.pa.msu.edu/hep/d0/ftp/tcc/vme_access/ (Note that the SCLD is called by its former SCL Fanout Card Name in this drawing). In addition to purely SCL related functions, the SCLD also provides support for any system-wide activities requiring synchronization across the four separate ADF Crates of the system. For example, the SCLD synchronizes the capture of monitoring data simultaneously on all 80 ADF-2 cards to produce a system-wide contemporary snapshot. The SCLD card was originally described in http://www-clued0.fnal.gov/~perez/R2BTRIGGER/ADF_Description/SCL.html SCLD to ADF Connection ---------------------- Each SCLD to ADF dedicated cable carries 8 pairs of differential signals with 2mm Hard Metric 20 pin 5 row connectors plugged into P0 rows #16:19 and columns #A:E in the back of the VME-64X slot for the ADF-2 Meastro Card. Each signal pair carries a Low Voltage Differential Signal (LVDS). In particular, one of the SCLD->ADF signals is the 7.57MHz Beam Crossing Clock (132ns period), which is lock in time with the Accelerator Beam Crossings. The SCLD receives this signal from the Serial Command Link. All SCLD->ADF signals, except the Beam Crossing Clock, will change state a maximum of one time per 132 ns period. At the SCLD output all SCLD->ADF control signals are guaranteed to be stable except when changing state which takes place about 18.8 nsec after the rising edge of the Beam Crossing Clock signal. All SCLD->ADF signals are received on the Maestro ADF-2 side, which drives them directly onto VME backplane Reserved Bus Lines. All 20 ADF-2 Cards in an ADF crate receive the bussed signals which become inputs to both ADF-2 Data Path FPGAs. All SCLD->ADF control signals are latched on the rising edge of the Beam Crossing Clock at receiving Data Path FPGA IO Block before being used inside the FPGA. All ADF->SCLD signals will only change state once per 132ns period, and will be latched when received by the SCLD on the rising edge of the Beam Crossing Clock. Given the length of the ADF to SCLD cables, the Maestro ADF-2 card will simply latch and update the state of its ADF->SCLD signals on the rising edge of its Beam Crossing Clock. This will give very comfortable timing for reception of these signals at the SCLD. SCLD Cable Pin and Signal Allocation for Maestro ADF-2 Card ADF-2 Differential Signal Name P0 Pin Direction Signal Description Polarity ----------------- ------ --------- -------------------------- ------------ CRATE_TO_SCLD_0_P A16 ADF->SCLD Crate to SCLD Signal #0 Direct CRATE_TO_SCLD_0_N B16 ADF->SCLD Crate to SCLD Signal #0 Complement GROUND C16 SCL_LIVE_BX_P D16 SCLD->ADF Live Beam Crossing Direct SCL_LIVE_BX_N E16 SCLD->ADF Live Beam Crossing Complement SCL_INIT_P A17 SCLD->ADF SCL Initialization Request Direct SCL_INIT_N B17 SCLD->ADF SCL Initialization Request Complement GROUND C17 CRATE_TO_SCLD_1_P D17 ADF->SCLD Crate to SCLD Signal #1 Direct CRATE_TO_SCLD_1_N E17 ADF->SCLD Crate to SCLD Signal #1 Complement SCL_BX_CLOCK_P A18 SCLD->ADF 7.57 MHz Beam Crossing Clock Direct SCL_BX_CLOCK_N B18 SCLD->ADF 7.57 MHz Beam Crossing Clock Complement GROUND C18 SCL_BEGIN_TURN_P D18 SCLD->ADF Begin of Turn Marker Direct SCL_BEGIN_TURN_N E18 SCLD->ADF Begin of Turn Marker Complement SAVE_MONIT_DATA_P A19 SCLD->ADF Save Monitoring Data Direct SAVE_MONIT_DATA_N B19 SCLD->ADF Save Monitoring Data Complement GROUND C19 SCLD_SPARE_P D19 SCLD->ADF Spare Signal Direct SCLD_SPARE_N E19 SCLD->ADF Spare Signal Complement Signals from the SCLD to the Maestro ADF's and then to all 20 ADF-2 Cards in a Crate: ------------------------------------------- There are 6 signals that are received by the Maestro ADF-2 Cards and then driven onto VME-64X Reserved Bus Lines. The SCL_BX_CLOCK is differentially driven onto a pair of backplane lines, while the other 5 signals are carried single ended on the backplane. All signals are doubly terminated with 194 Ohm resistors to 3 Volt on each end of the the VME backplane. All 20 ADF-2 Cards in the crate receive these 6 signals from the VME backplane. SCL_BX_CLOCK 7.57 MHz Beam Crossing Clock a.k.a. the 132ns Tick Clock provided by the SCL Receiver Mezzanine Card on the SCLD. This signal is driven on Backplane pins: P1-Z21 VME_64X_RSVBUS(4) for the direct side and P1-Z23 VME_64X_RSVBUS(5) for the complement side. SCL_BEGIN_TURN Marker asserted when this 132ns period is the Beginning of a Turn in the accelerator. This signal is provided by the SCL Receiver Mezzanine Card. The 132ns periods in the machine are called "Ticks" and are numbered from 1 through 159. The 132ns period when SCL_BEGIN_TURN is asserted corresponds to Tick Number 1. The SCL Hub-End delivers the Begin of Turn and all timing information to all Geographic Sections ahead of time as compared to their actual occurrence in the D-Zero Detector. The ADF-2 will need to take this fact into account when it rebuilds the Tick Number contemporary to its input data. When making this association you also need to taking into account all signal and cable latencies coming from the detector and the BLS cards. This signal is driven on Backplane pin P1-Z13 VME_64X_RSVBUS(0). SCL_LIVE_BX Marker asserted when this 132ns period contains a real beam crossing. This signal is provided by the SCL Receiver Mezzanine Card. This signal is driven on Backplane pin P1-Z15 VME_64X_RSVBUS(1). SCL_INIT DZero DAQ-wide SCL Initialize request distributed by the SCL Hub End. This signal is provided by the SCL Receiver Mezzanine Card. The SCLD will handle the SCL initialization protocol by waiting a fixed amount of time and asserting the SCL Init_Ack for a fixed amount of time. All ADF-2 cards will perform all appropriate local reset operations of its internal logic. No firmware will be reloaded, and no real-time activity from TCC is required in response to an SCL_Init request. This signal is driven on Backplane pin P1-Z19 VME_64X_RSVBUS(3). SAVE_MONIT_DATA ADF-2 specific request to save (or capture) current monitoring information. The SCLD logic asserts this signal when it has decided that the ADF-2 Cards should capture or save monitoring information corresponding to recent Beam Crossings. Assertion of the Save_Monit_Data signal causes the Address Generators in the ADF-2 Data Path FPGAs to stop and thus the writting of Monitor data into the Raw ADC and Final Et Output circular memory blocks is stopped. Assertion of this signal for just one Tick will cause the Address Generators to stop. In order to capture useful Monitor Data, it is assumed that before the Save_Monit_Data signal is asserted that the Data Path FPGA Address Generators would have been started up in the correct mode to collect Monitor Data. This signal is driven on Backplane pin P1-Z17 VME_64X_RSVBUS(2). SCLD_SPARE Currently unallocated signal from the SCLD to the ADF Crates and thus to all 80 ADF-2 cards. This signal is driven on Backplane pin P1-Z25 VME_64X_RSVBUS(6). From Each of the Maestro ADF's to the SCLD: ------------------------------------------ Each ADF Crate has its own private cable to the SCLD. Each ADF Crate sends two signals to the SCLD card. This allows up to 8 signals from the ADF-2 Crates to the SCLD Card and each signal can have a separate function. ADF to SCLD ADF ADF ADF ADF Signal Crate 0 Crate 1 Crate 2 Crate 3 -------------- -------------- --------- --------- --------- Assert ADF Crate to Save Monitor Spare Spare Spare SCLD Signal #0 Data on next L1_Accept with L1_Qual "CollectStatus" Asserted ADF Crate to Immediately Spare Spare Spare SCLD Signal #1 Assert Save Monitor Data Use of these ADF to SCLD signals ---------------------------------- Currently we are using only 2 of the 8 possible ADF to SCLD signals. Both of these signals are used to control the collection of Monitor Data in the L1 Cal Trig. These ADF to SCLD signals allow the L1 Cal Trig to collect Monitor Data either asynchronously (e.g. as is needed when no L1_Acpts are being issued by the TFW) or synchronously on the same events as the TFW and the L2 system collect their Monitor Data. The assumption is that before TCC uses either the: "Immediately_Assert_Save_Monitor_Data" signal or the "Assert_Save_Monitor_Data_on_Next_L1_Accept_with_L1_Qual_"CollectStatus"_Asserted" signal, that TCC would first have started the Address Generators for the Monitor Data Memory Blocks in the Data Path FPGAs running in the way that is required for these memory blocks to collect monitor data. These circular buffer memory blocks will then continue to collect monitor data until either TCC manually tells the Address Generators to stop or until the ADF-2 cards receive an asserted "Save_Monit_Data" signal from the SCLD card. There are two scenarios that will cause the SCLD card to send the "Save_Monit_Data" signal to the ADF-2 cards. They are: TCC causes the "Immediately_Assert_Save_Monitor_Data" signal to be sent to the SCLD card or TCC causes the "Assert_Save_Monitor_Data_on_Next_L1_Accept_with_ _L1_Qual_"CollectStatus"_Asserted" signal to be sent to the SCLD card AND the SCLD card receives over the SCL link an L1_Acpt that has the "CollectStatus" L1_Qualifier asserted. To use the "Immediately_Assert_Save_Monitor_Data" signal, TCC should set this signal asserted and then set this signal de-asserted. By this momentary assertion of the "Immediately_Assert_Save_Monitor_Data" signal TCC will cause the SCLD card to immediately send the "Save_Monit_Data" signal to the ADF-2 cards and that will cause the Address Generators in their Data Path FPGAs to immediately stop. TCC can verify that the Address Generators have stopped and then readout the monitor data. To use the "Assert_Save_Monitor_Data_on_Next_L1_Accept_with_L1_Qual_ _"CollectStatus"_Asserted" TCC should set this signal asserted before the TFW is armed to Capture Monitor Data on the next L1_Accept. When the TFW next Captures Monitor Data it will issue an L1_Accept that has the "CollectStatus" L1_Qualifier asserted and because the "Assert_Save_Monitor_Data_on_Next__L1_Accept_with_L1_Qual_"CollectStatus"_Asserted" signal is asserted this will cause the SCLD to send the Save_Monit_Data signal to the ADF-2 cards and that will cause the Address Generators in their Data Path FPGAs to immediately stop. TCC can verify that the Address Generators have stopped and then readout the monitor data. TCC can determine whether or not the Address Generators are running or stopped by reading a register. TCC can determine at what address the Address Generator stops by reading another register. This "last written address" lets TCC know where in the turn of the Tevatron the monitor data stopped being written. Interesting Note: The issue that TCC1 will be arming the TFW to Capture_Monitor_Data and that TCC3 will be controlling the "Assert_Save_Monitor_Data_on_Next_ L1_Accept_with_L1_Qual_"CollectStatus"_Asserted" signal has been ignored. I assume that they will tend to naturally "sync up" when things are running smoothly and will independently force the collection of monitor data when things are not running smoothly. Notes on SCLD <--> ADF signals: ------------------------------- Spare control signals As currently defined, we have: one spare SCLD --> ADF signal and two spare Maestro ADF --> SCLD signal form ADF Crates 1,2,3. ADF-2 on-card Status or Control signals between the Data Path FPGA's and the Board Control PAL ------------------------------------------------ The ADF-2 Card has 4 "status" signals between each Data Path FPGA and the Board Control PAL. For now these 4 lines are all in the direction to carry status information from the FPGA to the Board Control PAL. In the future we could turn some of these lines in the other direction if necessary. For now, in the Board Control PAL, all 4 of these signals are just connected to bits in a read only register. For now, in the FPGA, if we have no other use for these "status" signals then we will drive them from bits in a read-write register. Additionally, if needed, after Configuration, we can re-use: INIT_B and BUSY from each FPGA to carry additional "status" information from the FPGA's to an existing read only register in the Configuration Section of the Board Control PAL and re-use RDWR_B and CS_B to carry additional "control" information from a read-write register in the Configuration Section of the Board Control PAL to the FPGA's. RDWR_B is a common signal to both FPGA's. (the CS_B's are separate to each FPGA). Crate_Status Signals -------------------- Each ADF Crate has 4 open collector backplane Crate_Status lines. Any of the ADF-2 cards can pull one or more of the Crate_Status lines to its low Voltage asserted state. All ADF-2 cards receive the 4 Crate_Status lines. For now the Board Support PAL will be made so that it reads the 4 Crate_Status lines in 4 bits of a read only register and will be made so it can drive the 4 Crate Status lines by setting bits in a separate read-write register. If needed, the Board Support PAL can be made to react to some of the status lines that it receives from each Data Path FPGA and automatically assert a backplane Crate_Status Line. If needed, the Board Support PAL on the Maestro ADF-2 Card, which is able to read the Crate_Status lines (like any other ADF-2 Card in the crate), could also be allowed to automatically assert one of the CRATE_TO_SCLD request signals.