SCLD Operation with the ADF-2 ------------------------------- Original Rev. 29-JUNE-2004 Most Recent Rev. 6-JULY-2004 Although the SCLD circuit board was designed to operate with the ADF prototype circuit board it is also capable of providing all of the timing and control signals that are needed by the production ADF-2 circuit board. To operate with the ADF-2 circuit board different firmware will be needed in the SCLD's FPGA but, by design, this firmware has been kept very straight forward and easy to implement. The rest of this document describes the SCLD functions that are necessary to support the operation of the ADF-2 circuit board. SCLD Timing and Control Signals to the ADF-2 that come directly from the SCL Receiver Mezzanine -------------------------------------------------- The SCLD sends 1 timing signal SCL_BX_CLOCK and 3 control signals SCL_Begin_Turn, SCL_Live_BX, SCL_Initialize to the ADF-2 crates. All of these signals come directly from the SCL Receiver. To assist in the distribution of these signals one additional signal is used from the SCL Receiver - that is clock signal CLK_53. In the SCL Receiver these signals have different names which are: SCL_BX_CLOCK is SCL Receiver signal CLK_7 SCL_Begin_Turn is SCL Receiver signal FIRST_PERIOD SCL_Live_BX is SCL Receiver signal BEAM_PERIOD SCL_Initialize is SCL Receiver signal INIT_SECTION Absolutely identical copies of: SCL_BX_CLOCK, SCL_Begin_Turn, SCL_Live_BX, and SCL_Initialize are sent to all 4 ADF-2 crates. For operation with the ADF-2, the SCLD does not need to provide any timing adjustment in these signals. The timing of these signals as they come out of the SCL Receiver and as they are sent by the SCLD to the ADF-2 crates is shown in: www.pa.msu.edu/hep/d0/ftp/run2b/l1cal/hardware/adf_2/drawings/ scld_signal_timing.pdf and ps The only processing of these signals that is needed in the SCLD's FPGA is shown in the figure: www.pa.msu.edu/hep/d0/ftp/run2b/l1cal/hardware/adf_2/drawings/ scld_logic_block_diagram.pdf and ps The purpose of this processing is to insure that the transitions in the SCL_Begin_Turn, SCL_Live_BX, and SCL_Initialize signals that are send to the ADF-2 crates take place shortly after the positive edge of the SCL_BX_CLOCK signal that is also sent to these crates by the SCLD card. All of these signals are synchronized with respect to "the best clock in the house", i.e. the rising edge of the 53 MHz clock. This synchronization is done in the FPGA's I/O Block output registers to ensure that all copies of the timing and control signals going to the 4 ADF-2 crates are synchronous and as clean possible. The simple logic that generates the Clock Enable signals to these I/O Block output registers ensures that there is no sensitivity to the "coincident rising edges" of the CLK_7 and the CLK_53 signals from the SCL Receiver. The ability of the SCLD's FPGA to very accurately perform this processing has been facilitated by the SCL Receiver's CLK_7 and CLK_53 signals being connected to FPGA pins that tie directly to Global Clock Nets within the SCLD's FPGA. Details about the SCL Receiver are presented in: http://www-ese.fnal.gov/d0trig/SCLR_Spec.pdf See page 16 of that document for a timing diagram of the signals from the SCL Receiver. A short summary is as follows: - Transitions (up and down) in the SCL Receivers CLK_7 output are coincident with rising edges of its CLK_53 output. - Transitions in the other output signals from the SCL Receiver take place beginning with the rising edge of the CLK_7 signal. SCLD Control Signal to the ADF-2 that comes from logic in the SCLD --------------------------------- The SCLD generates one control signal that goes to the ADF cards that does not come from the SCL Receiver. This signal is the SAVE_MONITOR_DATA signal. For the duration of the time that the SMD signal is asserted the ADF-2 cards will stop writting into their circular buffers that hold monitoring data thus permitting readout of this data by the Trigger Control Computer over VME. Three different external conditions can cause the SCLD to begin asserting the SMD signal. These are: - Any one of the 4 ADF-2 crates may request that the SCLD immediately begin asserting the SMD signal. This can be used to capture monitoring data by "self triggering" from any one of the ADF-2 crates. This uses the CRATE_TO_SCLD_0 ADF to SCLD signal from each of the 4 ADF-2 crates. - The SMD generation logic can be enabled so that the next time that an L1 Accept is issued to the SCLD's Geographic Sector then the SCLD will begin asserting the SMD signal. Enabling the SCLD to begin asserting the SMD signal upon receiving the next L1_Acpt is done by asserting the CRATE_TO_SCLD_1 signal from ADF-2 crate number 0. - The SMD generation logic can be enabled so that the next time that an L1 Accept is issued to the SCLD's Geographic Sector AND the L1 Qualifier "Collect Status" is asserted at the same time, then the SCLD will begin asserting the SMD signal. Enabling the SCLD to begin asserting the SMD signal upon receiving the next L1_Acpt with "Collect Status" Qualifier is done by asserting the CRATE_TO_SCLD_1 signal from ADF-2 crate number 1. No matter what caused the SCLD to begin asserting the SMD signal it continues to assert SMD until it is requested to stop asserting it. The request to stop asserting the SMD signal is made by asserting the CRATE_TO_SCLD_1 signal from ADF-2 crate number 2. As with the other control signals from the SCLD to the ADF-2 crates the SMD signal only changes state shortly after the rising edge of the BX_CLOCK signal from the SCLD to the ADF-2 crates. That is the SMD signal must pass through an I/O Block output register just like the other control signals (the ones that come directly from the SCL Receiver). Further explanation of the Save Monitor Data operation can be found in the document: www.pa.msu.edu/hep/d0/ftp/run2b/l1cal/hardware/adf_2/general/ scld_adf_crate_control.txt Signals from the ADF-2 Crates to the SCLD Card ----------------------- Each ADF-2 crate sends 2 signals from the crate to the SCLD. These 2 signals are: CRATE_TO_SCLD_0 and CRATE_TO_SCLD_1. These signals are received by registers at the input to the SCLD's FPGA. These registers are only clocked at the time of the rising edge of the BX_CLOCK signal that is sent from the SCLD to the ADF-2 crates. The CRATE_TO_SCLD_0 and CRATE_TO_SCLD_1 signals only change state at the output of the ADF-2 crate at the time of the rising edge of the BX_CLOCK in that crate. Considering the short SCLD <-> ADF-2 crate cable runs this provides very wide timing margins for the transport of these signals from the ADF-2 crate to the SCLD card. After these ADF-2 crate to SCLD signals pass through the register at the input to the SCLD's FPGA they are used as described above. SCLD Managment of the SCL Receiver ---------------------------------- As described in the referenced document, any card that holds an SCL Receiver needs to provide certain support functions for it. The main function that is required is to tell the SCL Receiver when it should try to lock onto the SCL Serial Data stream. See the document: www.pa.msu.edu/hep/d0/ftp/scl/using_scl_receiver.txt Basically this means watching the SCL_SYNCERROR signal from the SCL Receiver and if it has been asserted for longer than some minimum length of time then you pulse the SCL_ACK signals that goes to the SCL Receiver which will cause it to try to lock or re-lock to the Serial SCL signal. The other support function that the card that holds the SCL Receiver should perform is looping the SCL_SYNCERROR to SYNC_LOST signals. This lets the SCL Hub-End see whether or not the SCL Receiver is locked onto the Serial SCL signal. Any logic on the card that holds the SCL Receiver sould not use the CLK_7 signal from the SCL Receiver to perform these support functions for the SCL Receiver because the CLK_7 will not be running if the SCL Receiver is not locked onto its input SCL Serial Data stream. These support functions are exactly the same whether the SCLD is operating with the Prototype ADF card or the ADF-2 card. SCLD On Card Loop Back Tester Function -------------------------------------- As designed for operation with the Prototype ADF card, the SCLD contained a Loop Back Tester Function. That is the SCLD contained an input connector so that it could "listen" to one of its output channels. This Loop Back Tester is not needed for operation with the ADF-2 card. SCLD 5th Channel ---------------- As designed for operation with the Prototype ADF card, the SCLD included a 5th set of SCLD <--> ADF signals. For operation with the ADF-2, this 5th set of signals may be useful for some testing and it should be painless to include them in the FPGA design. 5th Channel SCLD to ADF-2 signals please include these. They are just exact copies of the SCLD to ADF-2 signals on the other 4 channels. 5th Channel ADF-2 to SCLD signals please ignore these. The SCLD does nothing with the 2 ADF-2 to SCLD signals that it receives on its 5th Channel. SCLD Card LED's --------------- The 8 LED's that are driven by User I/O pins from the FPGA (Delays Loaded, Clock Locked, 5x Cables Connected, and User) are generally not useful when using the SCLD with the ADF-2. This is because: there are no delays to be loaded, there is no use of FPGA clock manages to be locked, and by definition all 4 cables are connected). A different use for these LED's when the SCLD is used with the ADF-2 should be thought about. SCLD User Parameter PROM ------------------------ As designed for operation with the Prototype ADF card, the SCLD included a PROM to hold User Paramters. This is not needed when the SCLD is used with the ADF-2 card. The pins on the FPGA that connect to this PROM should be set at some level so that both the SCLD FPGA and this PROM remain electrically happy. SCLD and ADF Cable Connector Pin Outs for Prototype and ADF-2 -------------------------------------------------------------- ADF Prototype's P0 Connection with the SCLD -------------------------------------------- DIR = direction In or Out with respect to the ADF prototype card. ADF Prototype ADF Prototype Pin Signal Net Name DIR Pin Signal Net Name DIR --- --------------------- --- --- --------------------- --- A13 SCLIF_CABLE_REM_B_F0 Out B13 SCLIF_CABLE_LOC_B_F0 In D13 SCLIF_CLK7_P_F0 In E13 SCLIF_CLK7_N_F0 In A14 SCLIF_CMDD_IN_P_F0 In B14 SCLIF_CMDD_IN_N_F0 In D14 SCLIF_CMDU_OUT_P_F0 Out E14 SCLIF_CMDU_OUT_N_F0 Out A15 SCLIF_BUSY_B_OUT_P_F0 Out B15 SCLIF_BUSY_B_OUT_N_F0 Out D15 SCLIF_STRG_B_P_F0 Out E15 SCLIF_STRG_B_N_F0 Out A16 SCLIF_ERR_B_OUT_P_F0 Out B16 SCLIF_ERR_B_OUT_N_F0 Out D16 SCLIF_SPARE_P_F0 In E16 SCLIF_SPARE_N_F0 In SCLD's Cable Connector When Used with the ADF Prototype --------------------------------------------------------- DIR = direction In or Out with respect to the SCLD. SCLD SCLD Pin Signal Net Name DIR Pin Signal Net Name DIR --- --------------------- --- --- --------------------- --- E2 SCLD_CABLE_LOC_B(0) In D2 SCLD_CABLE_REM_B(0) Out B2 SCLD_CLK7_OUT_P(0) Out A2 SCLD_CLK7_OUT_N(0) Out E3 SCLD_CMDD_OUT_P(0) Out D3 SCLD_CMDD_OUT_N(0) Out B3 SCLD_CMDU_IN_P(0) In A3 SCLD_CMDU_IN_N(0) In E4 SCLD_BUSY_B_IN_P(0) In D4 SCLD_BUSY_B_IN_N(0) In B4 SCLD_STRIG_B_IN_P(0) In A4 SCLD_STRIG_B_IN_N(0) In E5 SCLD_ERR_B_IN_P(0) In D5 SCLD_ERR_B_IN_N(0) In B5 SCLD_SPARE_OUT_P(0) Out A5 SCLD_SPARE_OUT_N(0) Out Note: Section (1) starts with pin row 7 Section (2) starts with pin row 2 of the next connector Section (3) starts with pin row 7 of the next connector Section (4) starts with pin row 2 of the 3rd connector SCLD to ADF Prototype Pin Connections ------------------------------------- SCLD Pin ADF Pin SCLD Pin ADF Pin -------- ------- -------- ------- A2 E13 A4 E15 B2 D13 B4 D15 D2 B13 D4 B15 E2 A13 E4 A15 A3 E14 A5 E16 B3 D14 B5 D16 D3 B14 D5 B16 E3 A14 E5 A16 ADF-2's P0 Connection with the SCLD ------------------------------------ DIR = direction In or Out with respect to the ADF-2 card. Pin ADF-2 Signal Net Name DIR Pin ADF-2 Signal Net Name DIR --- --------------------- --- --- --------------------- --- A16 CRATE_TO_SCLD_0_P Out B16 CRATE_TO_SCLD_0_N Out D16 SCL_LIVE_BX_P In E16 SCL_LIVE_BX_N In A17 SCL_INIT_P In B17 SCL_INIT_N In D17 CRATE_TO_SCLD_1_P Out E17 CRATE_TO_SCLD_1_N Out A18 SCL_BX_CLOCK_P In B18 SCL_BX_CLOCK_N In D18 SCL_BEGIN_TURN_P In E18 SCL_BEGIN_TURN_N In A19 SAVE_MONIT_DATA_P In B19 SAVE_MONIT_DATA_N In D19 SCLD_SPARE_P In E19 SCLD_SPARE_N In SCLD's Cable Connector When Used with the ADF-2 Card ------------------------------------------------------ DIR = direction In or Out with respect to the SCLD. Pin Signal DIR Pin Signal DIR --- --------------------- --- --- --------------------- --- E2 CRATE_TO_SCLD_0_P(0) In D2 CRATE_TO_SCLD_0_N(0) In B2 SCL_LIVE_BX_P(0) Out A2 SCL_LIVE_BX_N(0) Out E3 SCL_INIT_P(0) Out D3 SCL_INIT_N(0) Out B3 CRATE_TO_SCLD_1_P(0) In A3 CRATE_TO_SCLD_1_N(0) In E4 SCL_BX_CLOCK_P(0) Out D4 SCL_BX_CLOCK_N(0) Out B4 SCL_BEGIN_TURN_P(0) Out A4 SCL_BEGIN_TURN_N(0) Out E5 SAVE_MONIT_DATA_P(0) Out D5 SAVE_MONIT_DATA_N(0) Out B5 SCLD_SPARE_P(0) Out A5 SCLD_SPARE_N(0) Out Note: Sections (1) through (4) are pinned out exactly the same as with Prototype ADF operation. SCLD to ADF-2 Pin Connections ----------------------------- SCLD Pin ADF Pin SCLD Pin ADF Pin -------- ------- -------- ------- A2 E16 A4 E18 B2 D16 B4 D18 D2 B16 D4 B18 E2 A16 E4 A18 A3 E17 A5 E19 B3 D17 B5 D19 D3 B17 D5 B19 E3 A17 E5 A19 Hardware Changes on SCLD for Operation with the ADF-2 ----------------------------------------------------- Remove the 100 Ohm Terminator Resistors that are across: A4-B4 D4-E4 D5-E5 Remove the 4.7 k Ohm pull up to 3.3V resistor that is connected to: D2 Install 100 Ohm Terminator Resistors across: D2-E2 No changes to any traces or connections to the FPGA. Reference designators from SCLD print set ???