# This is a Key In Net List file for # the ADF-2 for the Run IIB Cal Trig # Board Control PAL XC95144XL # --------------------------------- # Original Rev. 26-FEB-2004 # Most Recent Rev. 10-AUG-2004 # This file includes all the nets for the Board Control PAL # which is a Xilinx XC95144XL. # This file contains the nets for the following components: # U1101 Xilinx XC95144XL Board Control PAL # C1101 : C1105 VDD_LOGIC bypass capacitors 0.1 uFd ceramic # C1106 : C1110 VDD_LOGIC bypass capacitors 4.7 nFd ceramic # C1111 : C1112 VDD_LOGIC bypass capacitors 10 uFd Tantalum "B" # This file contains the nets that are connected to the Board Control # PAL. To help make this understandable this file starts with just a # list of all of the net names involved with the Board Control PAL, # in rational net name order, and then list the pin connections to # the PAL in order of the Functional Blocks on that device. The power # supply, ground, and bypass capacitors are listed at the end. # List of Net Names that are connected to the Board Control PAL. # # For a full description of each of these signals please refer # to the following document: # # www.pa.msu.edu/hep/d0/ftp/run2b/l1cal/hardware/adf_2/general/ # board_control_pal_description.txt # # # # Into or # Out from # Signal Name wrt PAL Details # --------------- -------- -------------------- # # --- Global --- 1 pin # # PAL_BX_CLOCK In 7.59 MHz Clk common to PAL Global Clk Net # # # --- Board Level Control Section --- 25 pins # # DRV_CRATE_TO_SCLD(0:1) Out Two Crate to SCLD signals # SER_DESKEW_B Out DeSkew command to all Channel Link chips # SER_DC_BALANCE Out DC Balance signal to all Channel Link chips # ADC_ENABLE Out Enable signal to all ADC chips # FPGA_0_STATUS(0:3) In 4 Status lines from FPGA #0 # FPGA_1_STATUS(0:3) In 4 Status lines from FPGA #1 # DRV_CRATE_STATUS(0:3) Out Drive the 4 backplane Crate Status lines # CRATE_STATUS_B(0:3) In Receive the 4 backplane Crate Status lines # DATA_TO_FIRST_DAC_INPUT Out Serial data bit to the first DAC in the chain # DAC_SERIAL_DATA_CLOCK Out Serial Data Clock to all DAC's # DAC_CHIP_SELECT_B Out DAC Chip Select to all DAC's # LAST_DAC_OUTPUT_DATA In Serial data from the last DAC in the chain # # # --- VME Interface Section --- 54 pins # # OCB_ADRS(1:23) In Latched copy of the VME Address # LTCHD_AM(0:5) In Latched copy of the VME Address Modifiers # LTCHD_IACK_B In Latched copy of the VME IACK* # LTCHD_WRITE_B In Latched copy of VME WRITE* # VME_LTCH_CLK Out Clock to above VME latch # VME_GEO_B(0:4) In VME Geographic Address signals # VME_SYSRESET_B In VME SYSRESET* # RCVD_DS1 In Received and inverted copy of VME DS1* # DRV_DTACK Out Signal to the VME DTACK* driver # OCB_DATA(0:7) In/Out OCB Data Bus 8 LSBits # DATA_BUF_DIR Out Control VME Data Buffer Direction # DATA_BUF_ENB_B Out Control VME Data Buffer Enable # OCB_CHIP_SEL_B(0:1) Out Select FPGA Chip for I/O # OCB_WRITE_STRB_B Out On Card Bus Write Strobe Bar # OCB_DIRECTION Out On Card Bus Data Direction # # # --- FPGA Configuration Section --- 12 pins # # CNFG_CCLK Out Configuration Clock # CNFG_RDWR_B Out Configuration RDWR_B # CNFG_PROG_B(0:1) Out per FPGA configuration PROG_B # CNFG_CS_B(0:1) Out per FPGA cofiguration Chip Select # CNFG_INIT_B(0:1) In per FPGA configuration INIT_B # CNFG_BUSY(0:1) In per FPGA configuration Busy # CNFG_DONE(0:1) In per FPGA configuration Busy # # # --- Phase Locked Loop Pins --- 6 pins # # RCVD_BX_CLOCK In Reference clock signal from the backplane Global Net # PAL_BX_X8_CLOCK In BX_X8_CLOCK to the PLL Pre-Scaler Global Net # LOOP_FILTER_REF Out Reference voltage to Loop Filter 1/2 Vdd # PHASE_DET_OUT Out Phase Detector Output to the Loop Filter # PAL_FIRST_X8_EDGE Out FIRST_X8_EDGE signal to the 2 FPGAs # CNT_BIT_VAL_4 Out 7.59 MHz Pre-Scaler output - BX_CLOCK to PAL # # # --- LED and Spare PAL I/O Signals --- # # DRV_PAL_LED_0 Out Sent via a resistor to an LED cathode # DRV_PAL_LED_1 Out Sent via a resistor to an LED cathode # PAL_ACCESS_0 In or Out as needed - to Access Connector - FB 1 MC 4 # PAL_ACCESS_1 In or Out as needed - to Access Connector - FB 3 MC 3 # PAL_ACCESS_2 In or Out as needed - to Access Connector - FB 3 MC 11 # PAL_ACCESS_3 In or Out as needed - to Access Connector - FB 3 MC 4 # PAL_ACCESS_4 In or Out as needed - to Access Connector - FB 3 MC 12 # PAL_ACCESS_5 In or Out as needed - to Access Connector - FB 3 MC 7 # PAL_ACCESS_6 In or Out as needed - to Access Connector - FB 3 MC 10 # PAL_ACCESS_7 In or Out as needed - to Access Connector - FB 3 MC 14 # PAL_ACCESS_8 In or Out as needed - to Access Connector - FB 3 MC 15 # PAL_ACCESS_9 In or Out as needed - to Access Connector - FB 3 MC 17 # PAL_ACCESS_10 In or Out as needed - to Access Connector - FB 5 MC 9 # PAL_ACCESS_11 In or Out as needed - to Access Connector - FB 5 MC 11 # PAL_ACCESS_12 In or Out as needed - to Access Connector - FB 6 MC 5 # PAL_ACCESS_13 In or Out as needed - to Access Connector - FB 6 MC 4 # PAL_ACCESS_14 In or Out as needed - to Access Connector - FB 6 MC 6 # PAL_ACCESS_15 In or Out as needed - to Access Connector - FB 6 MC 8 # PAL_ACCESS_16 In or Out as needed - to Access Connector - FB 6 MC 10 # All 117 user I/O pins have assigned Net Name connections. # Now show the actual connections to the Board Control PAL. # These are listed in Xilinx Functional Block pin order # (not in Macrocell order). Each connection to the Board # Control PAL is listed as being an: Input signal to the # PAL, an Output signal from the PAL, or an I/O signal. # --- Function Block 2 --- 15 User I/O --- NET 'CNFG_PROG_B(1)' U1101-142 # Out Block 2 Macrocell 1 NET 'VME_SYSRESET_B' U1101-143 # In Block 2 Macrocell 2 Global Control GSR NET 'CNFG_CS_B(1)' U1101-2 # Out Block 2 Macrocell 5 Global Control GTS3 NET 'CNFG_INIT_B(1)' U1101-3 # In Block 2 Macrocell 6 Global Control GTS4 NET 'CNFG_BUSY(1)' U1101-4 # In Block 2 Macrocell 4 NET 'DATA_BUF_DIR' U1101-5 # Out Block 2 Macrocell 8 Global Control GTS1 NET 'OCB_DIRECTION' U1101-6 # Out Block 2 Macrocell 9 Global Control GTS2 NET 'CNFG_DONE(1)' U1101-7 # In Block 2 Macrocell 10 NET 'CNFG_CCLK' U1101-9 # Out Block 2 Macrocell 11 NET 'CNFG_RDWR_B' U1101-10 # Out Block 2 Macrocell 12 NET 'CNFG_PROG_B(0)' U1101-11 # Out Block 2 Macrocell 14 NET 'CNFG_CS_B(0)' U1101-12 # Out Block 2 Macrocell 13 NET 'CNFG_INIT_B(0)' U1101-13 # In Block 2 Macrocell 15 NET 'CNFG_BUSY(0)' U1101-14 # In Block 2 Macrocell 16 NET 'CNFG_DONE(0)' U1101-15 # In Block 2 Macrocell 17 # --- Function Block 1 --- 15 User I/O --- NET 'FPGA_1_STATUS(0)' U1101-16 # In Block 1 Macrocell 2 NET 'FPGA_1_STATUS(1)' U1101-17 # In Block 1 Macrocell 3 NET 'FPGA_1_STATUS(2)' U1101-19 # In Block 1 Macrocell 5 NET 'FPGA_1_STATUS(3)' U1101-20 # In Block 1 Macrocell 6 NET 'FPGA_0_STATUS(0)' U1101-21 # In Block 1 Macrocell 8 NET 'FPGA_0_STATUS(1)' U1101-22 # In Block 1 Macrocell 9 NET 'FPGA_0_STATUS(2)' U1101-23 # In Block 1 Macrocell 1 NET 'FPGA_0_STATUS(3)' U1101-24 # In Block 1 Macrocell 11 NET 'PAL_ACCESS_0' U1101-25 # I/O Block 1 Macrocell 4 NET 'ADC_ENABLE' U1101-26 # Out Block 1 Macrocell 12 NET 'SER_DC_BALANCE' U1101-27 # Out Block 1 Macrocell 14 NET 'SER_DESKEW_B' U1101-28 # Out Block 1 Macrocell 15 NET 'PAL_BX_CLOCK' U1101-30 # In Block 1 Macrocell 17 Global Pin GCK1 NET 'DRV_CRATE_TO_SCLD(0)' U1101-31 # Out Block 1 Macrocell 10 NET 'DRV_CRATE_TO_SCLD(1)' U1101-35 # Out Block 1 Macrocell 16 # --- Function Block 3 --- 15 User I/O --- NET 'RCVD_BX_CLOCK' U1101-32 # In Block 3 Macrocell 2 Global Control GCK2 NET 'CNT_BIT_VAL_4' U1101-33 # Out Block 3 Macrocell 5 NET 'PAL_FIRST_X8_EDGE' U1101-34 # Out Block 3 Macrocell 6 NET 'PAL_BX_X8_CLOCK' U1101-38 # In Block 3 Macrocell 8 Global Control GCK3 NET 'LOOP_FILTER_REF' U1101-39 # Out Block 3 Macrocell 1 NET 'PHASE_DET_OUT' U1101-40 # Out Block 3 Macrocell 9 NET 'PAL_ACCESS_1' U1101-41 # I/O Block 3 Macrocell 3 NET 'PAL_ACCESS_2' U1101-43 # I/O Block 3 Macrocell 11 NET 'PAL_ACCESS_3' U1101-44 # I/O Block 3 Macrocell 4 NET 'PAL_ACCESS_4' U1101-45 # I/O Block 3 Macrocell 12 NET 'PAL_ACCESS_5' U1101-46 # I/O Block 3 Macrocell 7 NET 'PAL_ACCESS_6' U1101-48 # I/O Block 3 Macrocell 10 NET 'PAL_ACCESS_7' U1101-49 # I/O Block 3 Macrocell 14 NET 'PAL_ACCESS_8' U1101-50 # I/O Block 3 Macrocell 15 NET 'PAL_ACCESS_9' U1101-51 # I/O Block 3 Macrocell 17 # --- Function Block 5 --- 14 User I/O --- NET 'DATA_BUF_ENB_B' U1101-52 # Out Block 5 Macrocell 2 NET 'VME_LTCH_CLK' U1101-53 # Out Block 5 Macrocell 5 NET 'DRV_DTACK' U1101-54 # Out Block 5 Macrocell 6 NET 'RCVD_DS1' U1101-56 # In Block 5 Macrocell 8 NET 'PAL_ACCESS_10' U1101-57 # I/O Block 5 Macrocell 9 NET 'PAL_ACCESS_11' U1101-58 # I/O Block 5 Macrocell 11 NET 'LTCHD_AM(4)' U1101-59 # In Block 5 Macrocell 3 NET 'LTCHD_IACK_B' U1101-60 # In Block 5 Macrocell 12 NET 'LTCHD_AM(3)' U1101-61 # In Block 5 Macrocell 14 NET 'LTCHD_AM(2)' U1101-64 # In Block 5 Macrocell 15 NET 'LTCHD_AM(1)' U1101-66 # In Block 5 Macrocell 7 NET 'LTCHD_AM(0)' U1101-68 # In Block 5 Macrocell 10 NET 'LTCHD_WRITE_B' U1101-69 # In Block 5 Macrocell 17 NET 'LTCHD_AM(5)' U1101-70 # In Block 5 Macrocell 13 # --- Function Block 7 --- 15 User I/O --- NET 'OCB_ADRS(23)' U1101-71 # In Block 7 Macrocell 2 NET 'OCB_DATA(7)' U1101-75 # I/O Block 7 Macrocell 3 NET 'OCB_ADRS(22)' U1101-74 # In Block 7 Macrocell 5 NET 'OCB_ADRS(21)' U1101-76 # In Block 7 Macrocell 6 NET 'OCB_DATA(6)' U1101-77 # I/O Block 7 Macrocell 7 NET 'OCB_ADRS(20)' U1101-78 # In Block 7 Macrocell 8 NET 'OCB_ADRS(18)' U1101-80 # In Block 7 Macrocell 9 NET 'OCB_ADRS(19)' U1101-79 # In Block 7 Macrocell 10 NET 'OCB_ADRS(16)' U1101-82 # In Block 7 Macrocell 11 NET 'OCB_DATA(4)' U1101-85 # I/O Block 7 Macrocell 12 NET 'OCB_ADRS(17)' U1101-81 # In Block 7 Macrocell 13 NET 'OCB_ADRS(15)' U1101-86 # In Block 7 Macrocell 14 NET 'OCB_ADRS(14)' U1101-87 # In Block 7 Macrocell 15 NET 'OCB_DATA(5)' U1101-83 # I/O Block 7 Macrocell 16 NET 'OCB_ADRS(13)' U1101-88 # In Block 7 Macrocell 17 # --- Function Block 8 --- 15 User I/O --- NET 'OCB_ADRS(12)' U1101-91 # In Block 8 Macrocell 2 NET 'OCB_DATA(2)' U1101-95 # I/O Block 8 Macrocell 3 NET 'OCB_ADRS(8)' U1101-97 # In Block 8 Macrocell 4 NET 'OCB_ADRS(11)' U1101-92 # In Block 8 Macrocell 5 NET 'OCB_ADRS(10)' U1101-93 # In Block 8 Macrocell 6 NET 'OCB_DATA(3)' U1101-94 # I/O Block 8 Macrocell 8 NET 'OCB_ADRS(9)' U1101-96 # In Block 8 Macrocell 9 NET 'OCB_ADRS(6)' U1101-101 # In Block 8 Macrocell 10 NET 'OCB_ADRS(7)' U1101-98 # In Block 8 Macrocell 11 NET 'OCB_DATA(1)' U1101-100 # I/O Block 8 Macrocell 12 NET 'OCB_ADRS(4)' U1101-103 # In Block 8 Macrocell 13 NET 'OCB_ADRS(5)' U1101-102 # In Block 8 Macrocell 14 NET 'OCB_ADRS(3)' U1101-104 # In Block 8 Macrocell 15 NET 'OCB_DATA(0)' U1101-107 # I/O Block 8 Macrocell 16 NET 'OCB_ADRS(2)' U1101-105 # In Block 8 Macrocell 17 # --- Function Block 6 --- 13 User I/O --- NET 'OCB_ADRS(1)' U1101-106 # In Block 6 Macrocell 2 NET 'PAL_ACCESS_12' U1101-110 # I/O Block 6 Macrocell 5 NET 'PAL_ACCESS_13' U1101-111 # I/O Block 6 Macrocell 4 NET 'PAL_ACCESS_14' U1101-112 # I/O Block 6 Macrocell 6 NET 'PAL_ACCESS_15' U1101-113 # I/O Block 6 Macrocell 8 NET 'PAL_ACCESS_16' U1101-115 # I/O Block 6 Macrocell 10 NET 'DRV_PAL_LED_0' U1101-116 # Out Block 6 Macrocell 9 NET 'DRV_CRATE_STATUS(0)' U1101-117 # Out Block 6 Macrocell 16 NET 'DRV_CRATE_STATUS(1)' U1101-119 # Out Block 6 Macrocell 11 NET 'DRV_CRATE_STATUS(2)' U1101-120 # Out Block 6 Macrocell 12 NET 'DRV_CRATE_STATUS(3)' U1101-121 # Out Block 6 Macrocell 14 NET 'CRATE_STATUS_B(0)' U1101-124 # In Block 6 Macrocell 15 NET 'CRATE_STATUS_B(1)' U1101-125 # In Block 6 Macrocell 17 # --- Function Block 4 --- 15 User I/O --- NET 'CRATE_STATUS_B(2)' U1101-118 # In Block 4 Macrocell 1 NET 'CRATE_STATUS_B(3)' U1101-126 # In Block 4 Macrocell 2 NET 'DRV_PAL_LED_1' U1101-128 # Out Block 4 Macrocell 5 NET 'VME_GEO_B(0)' U1101-129 # In Block 4 Macrocell 6 NET 'VME_GEO_B(1)' U1101-130 # In Block 4 Macrocell 8 NET 'VME_GEO_B(2)' U1101-131 # In Block 4 Macrocell 9 NET 'VME_GEO_B(3)' U1101-132 # In Block 4 Macrocell 11 NET 'VME_GEO_B(4)' U1101-133 # In Block 4 Macrocell 3 NET 'DATA_TO_FIRST_DAC_INPUT' U1101-134 # Out Block 4 Macrocell 12 NET 'DAC_SERIAL_DATA_CLOCK' U1101-135 # Out Block 4 Macrocell 10 NET 'DAC_CHIP_SELECT_B' U1101-136 # Out Block 4 Macrocell 14 NET 'LAST_DAC_OUTPUT_DATA' U1101-137 # In Block 4 Macrocell 13 NET 'OCB_CHIP_SEL_B(1)' U1101-138 # Out Block 4 Macrocell 15 NET 'OCB_CHIP_SEL_B(0)' U1101-139 # Out Block 4 Macrocell 16 NET 'OCB_WRITE_STRB_B' U1101-140 # Out Block 4 Macrocell 17 # The JTAG net connections to the XC95144XL TQ144 are: NET 'JTAG_TDI_BC_PAL' U1101-63 # TDI test data into the BC PAL NET 'JTAG_TMS' U1101-65 # TMS signal to BC PAL and to both FPGAs NET 'JTAG_TCK' U1101-67 # TCK signal to BC PAL and to both FPGAs NET 'JTAG_TDO_BC_PAL' U1101-122 # TDO test data output from the BC PAL # Now include all the nets for the power supplies and grounds. # U1101 is a XC95144XL NET 'VDD_LOGIC' U1101-8 U1101-84 # VDD to Internal PAL Logic NET 'VDD_LOGIC' U1101-42 U1101-141 # VDD to Internal PAL Logic NET 'VDD_LOGIC' U1101-1 U1101-55 U1101-109 # VDD to I/O NET 'VDD_LOGIC' U1101-37 U1101-73 U1101-127 # VDD to I/O NET 'GROUND' U1101-18 U1101-72 U1101-108 # Grounds NET 'GROUND' U1101-29 U1101-89 U1101-114 # Grounds NET 'GROUND' U1101-36 U1101-90 U1101-123 # Grounds NET 'GROUND' U1101-47 U1101-99 U1101-144 # Grounds NET 'GROUND' U1101-62 # Grounds # Now include all the nets for the bypass capacitors. # 0.1 uFd Ceramic NET 'VDD_LOGIC' C1101-1 C1102-1 C1103-1 C1104-1 C1105-1 NET 'GROUND' C1101-2 C1102-2 C1103-2 C1104-2 C1105-2 # 4.7 nFd Ceramic NET 'VDD_LOGIC' C1106-1 C1107-1 C1108-1 C1109-1 C1110-1 NET 'GROUND' C1106-2 C1107-2 C1108-2 C1109-2 C1110-2 # 10 uFd Tantalum NET 'VDD_LOGIC' C1111-1 C1112-1 NET 'GROUND' C1111-2 C1112-2