# This is a Key In Net List file for # the ADF-2 for the Run IIB Cal Trig # Channel Link Output Chips # --------------------------------- # # Original Rev. 24-FEB-2004 # Most Recent Rev. 26-AUG-2004 # This file includes all the nets for the 3 National Semiconductor # Channel Link serial data output ports. # This file contains the nets for the following components: # # U1201, U1202, U1203 DS90CR483 Channel Link Transmitters # for ADF -> TAB links 0, 1, 2 # # C1201 : C1230 VDD_LOGIC bypass capacitors 0.1 uFd ceramic # C1241 : C1246 VDD_LOGIC bypass capacitors 10 uFd Tantalum "B" # C1251 : C1262 VDD_LOGIC bypass capacitors 4.7 nFd ceramic # # R1201, R1202, R1203 100 Ohm resistors to terminate the # unused serial data output TxOUT7 # # R1204, R1205, R1206 Pre-Emphasis Select Resistor 1 Meg Ohm # # First will be listed all of the nets that are the common to all 3 # Channel Links, i.e. connect in parallel to all 3 Channel Link chips. # Start with the common parallel input data bits. NET 'SER_CH_0_EM' U1201-10 U1202-10 U1203-10 # TxIN_0 Data Input NET 'SER_CH_0_HD' U1201-9 U1202-9 U1203-9 # TxIN_1 Data Input NET 'SER_CH_1_EM' U1201-8 U1202-8 U1203-8 # TxIN_2 Data Input NET 'SER_CH_1_HD' U1201-7 U1202-7 U1203-7 # TxIN_3 Data Input NET 'SER_CH_2_EM' U1201-6 U1202-6 U1203-6 # TxIN_4 Data Input NET 'SER_CH_2_HD' U1201-5 U1202-5 U1203-5 # TxIN_5 Data Input NET 'SER_CH_3_EM' U1201-4 U1202-4 U1203-4 # TxIN_6 Data Input NET 'SER_CH_3_HD' U1201-3 U1202-3 U1203-3 # TxIN_7 Data Input NET 'SER_CH_4_EM' U1201-2 U1202-2 U1203-2 # TxIN_8 Data Input NET 'SER_CH_4_HD' U1201-1 U1202-1 U1203-1 # TxIN_9 Data Input NET 'SER_CH_5_EM' U1201-100 U1202-100 U1203-100 # TxIN_10 Data Input NET 'SER_CH_5_HD' U1201-99 U1202-99 U1203-99 # TxIN_11 Data Input NET 'SER_CH_6_EM' U1201-96 U1202-96 U1203-96 # TxIN_12 Data Input NET 'SER_CH_6_HD' U1201-95 U1202-95 U1203-95 # TxIN_13 Data Input NET 'SER_CH_7_EM' U1201-94 U1202-94 U1203-94 # TxIN_14 Data Input NET 'SER_CH_7_HD' U1201-93 U1202-93 U1203-93 # TxIN_15 Data Input NET 'SER_CH_8_EM' U1201-92 U1202-92 U1203-92 # TxIN_16 Data Input NET 'SER_CH_8_HD' U1201-91 U1202-91 U1203-91 # TxIN_17 Data Input NET 'SER_CH_9_EM' U1201-90 U1202-90 U1203-90 # TxIN_18 Data Input NET 'SER_CH_9_HD' U1201-89 U1202-89 U1203-89 # TxIN_19 Data Input NET 'SER_CH_10_EM' U1201-88 U1202-88 U1203-88 # TxIN_20 Data Input NET 'SER_CH_10_HD' U1201-87 U1202-87 U1203-87 # TxIN_21 Data Input NET 'SER_CH_11_EM' U1201-86 U1202-86 U1203-86 # TxIN_22 Data Input NET 'SER_CH_11_HD' U1201-85 U1202-85 U1203-85 # TxIN_23 Data Input NET 'SER_CH_12_EM' U1201-84 U1202-84 U1203-84 # TxIN_24 Data Input NET 'SER_CH_12_HD' U1201-81 U1202-81 U1203-81 # TxIN_25 Data Input NET 'SER_CH_13_EM' U1201-80 U1202-80 U1203-80 # TxIN_26 Data Input NET 'SER_CH_13_HD' U1201-79 U1202-79 U1203-79 # TxIN_27 Data Input NET 'SER_CH_14_EM' U1201-78 U1202-78 U1203-78 # TxIN_28 Data Input NET 'SER_CH_14_HD' U1201-77 U1202-77 U1203-77 # TxIN_29 Data Input NET 'GROUND' U1201-76 U1202-76 U1203-76 # TxIN_30 Data Input NET 'GROUND' U1201-75 U1202-75 U1203-75 # TxIN_31 Data Input NET 'SER_CH_15_EM' U1201-74 U1202-74 U1203-74 # TxIN_32 Data Input NET 'SER_CH_15_HD' U1201-73 U1202-73 U1203-73 # TxIN_33 Data Input NET 'SER_BX_COUNT_F0' U1201-72 U1202-72 U1203-72 # TxIN_34 Data Input NET 'SER_RSVD_F0(3)' U1201-71 U1202-71 U1203-71 # TxIN_35 Data Input NET 'SER_FRAME_F0' U1201-70 U1202-70 U1203-70 # TxIN_36 Data Input NET 'SER_PARITY_F0' U1201-69 U1202-69 U1203-69 # TxIN_37 Data Input NET 'GROUND' U1201-66 U1202-66 U1203-66 # TxIN_38 Data Input NET 'GROUND' U1201-65 U1202-65 U1203-65 # TxIN_39 Data Input NET 'SER_RSVD_F0(0)' U1201-64 U1202-64 U1203-64 # TxIN_40 Data Input NET 'SER_RSVD_F0(1)' U1201-63 U1202-63 U1203-63 # TxIN_41 Data Input NET 'SER_RSVD_F0(2)' U1201-62 U1202-62 U1203-62 # TxIN_42 Data Input NET 'SER_RSVD_F1(0)' U1201-61 U1202-61 U1203-61 # TxIN_43 Data Input NET 'SER_RSVD_F1(1)' U1201-60 U1202-60 U1203-60 # TxIN_44 Data Input NET 'SER_RSVD_F1(2)' U1201-59 U1202-59 U1203-59 # TxIN_45 Data Input NET 'GROUND' U1201-58 U1202-58 U1203-58 # TxIN_46 Data Input NET 'GROUND' U1201-57 U1202-57 U1203-57 # TxIN_47 Data Input # The "8th" serial data cable, i.e. TxOut7, is not connected between the # ADF and the TAB. This serial data cable carries Channel Link bits: # 30, 31, 38, 39, 46, 47 so those Channel Link bits are not transported. # Now list the nets of the control signals that are # common to all 3 Channel Link chips. NET 'SER_DESKEW_B' U1201-56 U1202-56 U1203-56 # DS_OPT Low -> perform # cable deskew NET 'SER_DC_BALANCE' U1201-24 U1202-24 U1203-24 # BAL Open or Low -> # disable DC Balance NET 'VDD_LOGIC' U1201-22 U1202-22 U1203-22 # PD* Low -> Power Down NET 'VDD_LOGIC' U1201-15 U1202-15 U1203-15 # PLL_SEL PLL Range Select # Must be tied Vdd # Now list the control input nets that are # specific to each Channel Link chip. # First the Pre-Emphasis control input. NET 'PRE_LINK_1' U1201-14 R1204-1 # PRE Pre-Emphasis level Select # Pull up towards Vdd. # open -> normal LVDS NET 'VDD_LOGIC' R1204-2 # Far side of resistor is at Vdd. NET 'PRE_LINK_2' U1202-14 R1205-1 # PRE Pre-Emphasis level Select # Pull up towards Vdd. # open -> normal LVDS NET 'VDD_LOGIC' R1205-2 # Far side of resistor is at Vdd. NET 'PRE_LINK_3' U1203-14 R1206-1 # PRE Pre-Emphasis level Select # Pull up towards Vdd. # open -> normal LVDS NET 'VDD_LOGIC' R1206-2 # Far side of resistor is at Vdd. # Now the nets for the Transmit Clock Input. NET 'BX_X8_CLOCK_LINK_1' U1201-11 # TxCLKIN Transmit Clk Input # Rising edge is data strobe. NET 'BX_X8_CLOCK_LINK_2' U1202-11 # TxCLKIN Transmit Clk Input # Rising edge is data strobe. NET 'BX_X8_CLOCK_LINK_3' U1203-11 # TxCLKIN Transmit Clk Input # Rising edge is data strobe. # Now list the nets that are the Channel Link Serial Data Output # and the the Channel Link Serial Clock. These are separate for # each of the 3 Channel Link chips. # Link 0 NET 'L0_TX0_P' U1201-49 # TxOUTP0 Link 0 Serial Data 0 Direct NET 'L0_TX0_N' U1201-50 # TxOUTM0 Link 0 Serial Data 0 Complement NET 'L0_TX1_P' U1201-46 # TxOUTP1 Link 0 Serial Data 1 Direct NET 'L0_TX1_N' U1201-47 # TxOUTM1 Link 0 Serial Data 1 Complement NET 'L0_TX2_P' U1201-44 # TxOUTP2 Link 0 Serial Data 2 Direct NET 'L0_TX2_N' U1201-45 # TxOUTM2 Link 0 Serial Data 2 Complement NET 'L0_TXC_P' U1201-41 # TxCLKP Link 0 Serial Clock Direct NET 'L0_TXC_N' U1201-42 # TxCLKM Link 0 Serial Clock Complement NET 'L0_TX3_P' U1201-38 # TxOUTP3 Link 0 Serial Data 3 Direct NET 'L0_TX3_N' U1201-39 # TxOUTM3 Link 0 Serial Data 3 Complement NET 'L0_TX4_P' U1201-36 # TxOUTP4 Link 0 Serial Data 4 Direct NET 'L0_TX4_N' U1201-37 # TxOUTM4 Link 0 Serial Data 4 Complement NET 'L0_TX5_P' U1201-33 # TxOUTP5 Link 0 Serial Data 5 Direct NET 'L0_TX5_N' U1201-34 # TxOUTM5 Link 0 Serial Data 5 Complement NET 'L0_TX6_P' U1201-31 # TxOUTP6 Link 0 Serial Data 6 Direct NET 'L0_TX6_N' U1201-32 # TxOUTM6 Link 0 Serial Data 6 Complement NET 'L0_TX7_P' U1201-28 R1201-1 # TxOUTP7 Link 0 Term Resistor Not sent NET 'L0_TX7_N' U1201-29 R1201-2 # TxOUTM7 Link 0 Term Resistor Not sent # Link 1 NET 'L1_TX0_P' U1202-49 # TxOUTP0 Link 1 Serial Data 0 Direct NET 'L1_TX0_N' U1202-50 # TxOUTM0 Link 1 Serial Data 0 Complement NET 'L1_TX1_P' U1202-46 # TxOUTP1 Link 1 Serial Data 1 Direct NET 'L1_TX1_N' U1202-47 # TxOUTM1 Link 1 Serial Data 1 Complement NET 'L1_TX2_P' U1202-44 # TxOUTP2 Link 1 Serial Data 2 Direct NET 'L1_TX2_N' U1202-45 # TxOUTM2 Link 1 Serial Data 2 Complement NET 'L1_TXC_P' U1202-41 # TxCLKP Link 1 Serial Clock Direct NET 'L1_TXC_N' U1202-42 # TxCLKM Link 1 Serial Clock Complement NET 'L1_TX3_P' U1202-38 # TxOUTP3 Link 1 Serial Data 3 Direct NET 'L1_TX3_N' U1202-39 # TxOUTM3 Link 1 Serial Data 3 Complement NET 'L1_TX4_P' U1202-36 # TxOUTP4 Link 1 Serial Data 4 Direct NET 'L1_TX4_N' U1202-37 # TxOUTM4 Link 1 Serial Data 4 Complement NET 'L1_TX5_P' U1202-33 # TxOUTP5 Link 1 Serial Data 5 Direct NET 'L1_TX5_N' U1202-34 # TxOUTM5 Link 1 Serial Data 5 Complement NET 'L1_TX6_P' U1202-31 # TxOUTP6 Link 1 Serial Data 6 Direct NET 'L1_TX6_N' U1202-32 # TxOUTM6 Link 1 Serial Data 6 Complement NET 'L1_TX7_P' U1202-28 R1202-1 # TxOUTP7 Link 1 Term Resistor Not sent NET 'L1_TX7_N' U1202-29 R1202-2 # TxOUTM7 Link 1 Term Resistor Not sent # Link 2 NET 'L2_TX0_P' U1203-49 # TxOUTP0 Link 2 Serial Data 0 Direct NET 'L2_TX0_N' U1203-50 # TxOUTM0 Link 2 Serial Data 0 Complement NET 'L2_TX1_P' U1203-46 # TxOUTP1 Link 2 Serial Data 1 Direct NET 'L2_TX1_N' U1203-47 # TxOUTM1 Link 2 Serial Data 1 Complement NET 'L2_TX2_P' U1203-44 # TxOUTP2 Link 2 Serial Data 2 Direct NET 'L2_TX2_N' U1203-45 # TxOUTM2 Link 2 Serial Data 2 Complement NET 'L2_TXC_P' U1203-41 # TxCLKP Link 2 Serial Clock Direct NET 'L2_TXC_N' U1203-42 # TxCLKM Link 2 Serial Clock Complement NET 'L2_TX3_P' U1203-38 # TxOUTP3 Link 2 Serial Data 3 Direct NET 'L2_TX3_N' U1203-39 # TxOUTM3 Link 2 Serial Data 3 Complement NET 'L2_TX4_P' U1203-36 # TxOUTP4 Link 2 Serial Data 4 Direct NET 'L2_TX4_N' U1203-37 # TxOUTM4 Link 2 Serial Data 4 Complement NET 'L2_TX5_P' U1203-33 # TxOUTP5 Link 2 Serial Data 5 Direct NET 'L2_TX5_N' U1203-34 # TxOUTM5 Link 2 Serial Data 5 Complement NET 'L2_TX6_P' U1203-31 # TxOUTP6 Link 2 Serial Data 6 Direct NET 'L2_TX6_N' U1203-32 # TxOUTM6 Link 2 Serial Data 6 Complement NET 'L2_TX7_P' U1203-28 R1203-1 # TxOUTP7 Link 2 Term Resistor Not sent NET 'L2_TX7_N' U1203-29 R1203-2 # TxOUTM7 Link 2 Term Resistor Not sent # Pins 26, 27, 54, 55 on the DS90CR483 are "make no connection". # i.e. not just "no internal connection but # make no connection to this pin. # Now include all the nets for the power supplies and grounds. # U1201 is a DS90CR483 NET 'VDD_LOGIC' U1201-20 U1201-21 U1201-23 # VDD to Logic NET 'VDD_LOGIC' U1201-53 U1201-67 U1201-82 # VDD to Logic NET 'VDD_LOGIC' U1201-97 # VDD to Logic NET 'VDD_LOGIC' U1201-12 U1201-18 # VDD to PLL NET 'VDD_LOGIC' U1201-30 U1201-40 U1201-48 # VDD to LVDS NET 'GROUND' U1201-13 U1201-52 U1201-68 # Logic Grounds NET 'GROUND' U1201-83 U1201-98 # Logic Grounds NET 'GROUND' U1201-16 U1201-17 U1201-19 # PLL Grounds NET 'GROUND' U1201-25 U1201-35 # LVDS Grounds NET 'GROUND' U1201-43 U1201-51 # LVDS Grounds # U1202 is a DS90CR483 NET 'VDD_LOGIC' U1202-20 U1202-21 U1202-23 # VDD to Logic NET 'VDD_LOGIC' U1202-53 U1202-67 U1202-82 # VDD to Logic NET 'VDD_LOGIC' U1202-97 # VDD to Logic NET 'VDD_LOGIC' U1202-12 U1202-18 # VDD to PLL NET 'VDD_LOGIC' U1202-30 U1202-40 U1202-48 # VDD to LVDS NET 'GROUND' U1202-13 U1202-52 U1202-68 # Logic Grounds NET 'GROUND' U1202-83 U1202-98 # Logic Grounds NET 'GROUND' U1202-16 U1202-17 U1202-19 # PLL Grounds NET 'GROUND' U1202-25 U1202-35 # LVDS Grounds NET 'GROUND' U1202-43 U1202-51 # LVDS Grounds # U1203 is a DS90CR483 NET 'VDD_LOGIC' U1203-20 U1203-21 U1203-23 # VDD to Logic NET 'VDD_LOGIC' U1203-53 U1203-67 U1203-82 # VDD to Logic NET 'VDD_LOGIC' U1203-97 # VDD to Logic NET 'VDD_LOGIC' U1203-12 U1203-18 # VDD to PLL NET 'VDD_LOGIC' U1203-30 U1203-40 U1203-48 # VDD to LVDS NET 'GROUND' U1203-13 U1203-52 U1203-68 # Logic Grounds NET 'GROUND' U1203-83 U1203-98 # Logic Grounds NET 'GROUND' U1203-16 U1203-17 U1203-19 # PLL Grounds NET 'GROUND' U1203-25 U1203-35 # LVDS Grounds NET 'GROUND' U1203-43 U1203-51 # LVDS Grounds # Now include all the nets for the bypass capacitors. # 0.1 uFd Ceramic NET 'VDD_LOGIC' C1201-1 C1202-2 C1203-2 C1204-1 C1205-2 NET 'GROUND' C1201-2 C1202-1 C1203-1 C1204-2 C1205-1 NET 'VDD_LOGIC' C1206-2 C1207-2 C1208-1 C1209-2 C1210-2 NET 'GROUND' C1206-1 C1207-1 C1208-2 C1209-1 C1210-1 NET 'VDD_LOGIC' C1211-1 C1212-2 C1213-2 C1214-1 C1215-2 NET 'GROUND' C1211-2 C1212-1 C1213-1 C1214-2 C1215-1 NET 'VDD_LOGIC' C1216-2 C1217-2 C1218-1 C1219-2 C1220-2 NET 'GROUND' C1216-1 C1217-1 C1218-2 C1219-1 C1220-1 NET 'VDD_LOGIC' C1221-1 C1222-2 C1223-2 C1224-1 C1225-2 NET 'GROUND' C1221-2 C1222-1 C1223-1 C1224-2 C1225-1 NET 'VDD_LOGIC' C1226-2 C1227-2 C1228-1 C1229-2 C1230-2 NET 'GROUND' C1226-1 C1227-1 C1228-2 C1229-1 C1230-1 # 10 uFd Tantalum "B" case NET 'VDD_LOGIC' C1241-1 C1242-1 NET 'GROUND' C1241-2 C1242-2 NET 'VDD_LOGIC' C1243-1 C1244-1 NET 'GROUND' C1243-2 C1244-2 NET 'VDD_LOGIC' C1245-1 C1246-1 NET 'GROUND' C1245-2 C1246-2 # Now additional 4.7 nfd ceramic bypass capacitors NET 'VDD_LOGIC' C1251-1 C1252-1 C1253-1 C1254-1 NET 'GROUND' C1251-2 C1252-2 C1253-2 C1254-2 NET 'VDD_LOGIC' C1255-1 C1256-1 C1257-1 C1258-1 NET 'GROUND' C1255-2 C1256-2 C1257-2 C1258-2 NET 'VDD_LOGIC' C1259-1 C1260-1 C1261-1 C1262-1 NET 'GROUND' C1259-2 C1260-2 C1261-2 C1262-2 # Supply Bypass Recommendations: # # Bypass capacitors must be used on the power supply pins. Different # pins supply different portions of the circuit, therefore capacitors # should be nearby all power supply pins except as noted in the pin # description table. Use high frequency ceramic (surface mount # recommended) 0.1 uF capacitors close to each supply pin. If space # allows, a 0.01 uF capacitor should be used in parallel, with the # smallest value closest to the device pin. Additional scattered # capacitors over the printed circuit board will improve # decoupling. Multiple (large) via should be used to connect the # decoupling capacitors to the power plane. A 4.7 to 10 uF bulk cap # is recommended near the PLLVCC pins and also the LVDSVCC (pin #40) # on the Transmitter. Connections between the caps and the pin should # use wide traces. # # The pin list says that bypass is not required on pins 20 and 21.