Data Path FPGA Signals for FPGA F0 -------------------------------------- (cf. appendix for comparison of FPGA F0 vs F1 Net Names) Original Rev. 14-APR-2004 Current Rev. 2-JAN-2005 Into or Signal Out From FPGA Pin Net Name wrt FPGA Name & Number Function -------------------- ------- --------------------- ----------------------- ## Beam Crossing Clock 2 clock net pins BX_X8_CLOCK_F0 In Y11 IO_L96P_5/GCLK6P 8x Beam Crossing Clock FIRST_X8_EDGE_F0 In AB12 IO_L96P_4/GCLK0P Identify First 8x Rising Edge of each BX ## ADC Data 10 x 2 x 8 = 160 user I/O pins CH_0_EM_ADC_DATA(0) In L2 IO_L96P_7 EM Channel #0 ADC bit #0 CH_0_EM_ADC_DATA(1) In K2 IO_L93N_7/VRP_0 EM Channel #0 ADC bit #1 CH_0_EM_ADC_DATA(2) In J2 IO_L51N_7 EM Channel #0 ADC bit #2 CH_0_EM_ADC_DATA(3) In H2 IO_L48N_7 EM Channel #0 ADC bit #3 CH_0_EM_ADC_DATA(4) In G2 IO_L43N_7 EM Channel #0 ADC bit #4 CH_0_EM_ADC_DATA(5) In F2 IO_L22N_7 EM Channel #0 ADC bit #5 CH_0_EM_ADC_DATA(6) In E2 IO_L06N_7 EM Channel #0 ADC bit #6 CH_0_EM_ADC_DATA(7) In D2 IO_L03N_7 EM Channel #0 ADC bit #7 CH_0_EM_ADC_DATA(8) In C1 IO_L02P_7/VRN_7 EM Channel #0 ADC bit #8 CH_0_EM_ADC_DATA(9) In C2 IO_L02N_7/VRP_7P EM Channel #0 ADC bit #9 CH_0_HD_ADC_DATA(0) In C11 IO_L95P_0/GCLK6S HD Channel #0 ADC bit #0 CH_0_HD_ADC_DATA(1) In C10 IO_L92P_0 HD Channel #0 ADC bit #1 CH_0_HD_ADC_DATA(2) In C9 IO_L52P_0 HD Channel #0 ADC bit #2 CH_0_HD_ADC_DATA(3) In A8 IO_L49P_0 HD Channel #0 ADC bit #3 CH_0_HD_ADC_DATA(4) In C8 IO_L24P_0 HD Channel #0 ADC bit #4 CH_0_HD_ADC_DATA(5) In C7 IO_L21P_0/VREF_0 HD Channel #0 ADC bit #5 CH_0_HD_ADC_DATA(6) In C6 IO_L04P_0 HD Channel #0 ADC bit #6 CH_0_HD_ADC_DATA(7) In C5 IO_L02P_0 HD Channel #0 ADC bit #7 CH_0_HD_ADC_DATA(8) In A4 IO_L01P_0 HD Channel #0 ADC bit #8 CH_0_HD_ADC_DATA(9) In C4 IO_L02N_0 HD Channel #0 ADC bit #9 CH_1_EM_ADC_DATA(0) In F11 IO_L94P_0/GCLK6S EM Channel #1 ADC bit #0 CH_1_EM_ADC_DATA(1) In F10 IO_L91P_0 EM Channel #1 ADC bit #1 CH_1_EM_ADC_DATA(2) In F9 IO_L51P_0/VREF_0 EM Channel #1 ADC bit #2 CH_1_EM_ADC_DATA(3) In G5 IO_L19P_7/VREF_0 EM Channel #1 ADC bit #3 CH_1_EM_ADC_DATA(4) In F5 IO_L19N_7 EM Channel #1 ADC bit #4 CH_1_EM_ADC_DATA(5) In E5 IO_L01P_7 EM Channel #1 ADC bit #5 CH_1_EM_ADC_DATA(6) In H1 IO_L48P_7 EM Channel #1 ADC bit #6 CH_1_EM_ADC_DATA(7) In K6 IO_L54N_7 EM Channel #1 ADC bit #7 CH_1_EM_ADC_DATA(8) In J6 IO_L45P_7/VREF_7 EM Channel #1 ADC bit #8 CH_1_EM_ADC_DATA(9) In L6 IO_L54P_7 EM Channel #1 ADC bit #9 CH_1_HD_ADC_DATA(0) In B11 IO_L96N_0/GCLK5P HD Channel #1 ADC bit #0 CH_1_HD_ADC_DATA(1) In A10 IO_L93P_0 HD Channel #1 ADC bit #1 CH_1_HD_ADC_DATA(2) In B10 IO_L93N_0 HD Channel #1 ADC bit #2 CH_1_HD_ADC_DATA(3) In B9 IO_L54N_0 HD Channel #1 ADC bit #3 CH_1_HD_ADC_DATA(4) In B8 IO_L49N_0 HD Channel #1 ADC bit #4 CH_1_HD_ADC_DATA(5) In B7 IO_L22N_0 HD Channel #1 ADC bit #5 CH_1_HD_ADC_DATA(6) In A6 IO_L05P_0 HD Channel #1 ADC bit #6 CH_1_HD_ADC_DATA(7) In B6 IO_L05N_0 HD Channel #1 ADC bit #7 CH_1_HD_ADC_DATA(8) In B5 IO_L03N_0/VRP_0 HD Channel #1 ADC bit #8 CH_1_HD_ADC_DATA(9) In B4 IO_L01N_0 HD Channel #1 ADC bit #9 CH_2_EM_ADC_DATA(0) In A11 IO_L96P_0/GCLK4S EM Channel #2 ADC bit #0 CH_2_EM_ADC_DATA(1) In D11 IO_L95N_0/GCLK7P EM Channel #2 ADC bit #1 CH_2_EM_ADC_DATA(2) In D10 IO_L92N_0 EM Channel #2 ADC bit #2 CH_2_EM_ADC_DATA(3) In A7 IO_L22P_0 EM Channel #2 ADC bit #3 CH_2_EM_ADC_DATA(4) In D9 IO_L52N_0 EM Channel #2 ADC bit #4 CH_2_EM_ADC_DATA(5) In A9 IO_L54P_0 EM Channel #2 ADC bit #5 CH_2_EM_ADC_DATA(6) In D8 IO_L24N_0 EM Channel #2 ADC bit #6 CH_2_EM_ADC_DATA(7) In D6 IO_L04N_0/VREF_0 EM Channel #2 ADC bit #7 CH_2_EM_ADC_DATA(8) In D7 IO_L21N_0 EM Channel #2 ADC bit #8 CH_2_EM_ADC_DATA(9) In A5 IO_L03P_0/VRN_0 EM Channel #2 ADC bit #9 CH_2_HD_ADC_DATA(0) In E11 IO_L94N_0/VREF_0 HD Channel #2 ADC bit #0 CH_2_HD_ADC_DATA(1) In E10 IO_L91N_0/VREF_0 HD Channel #2 ADC bit #1 CH_2_HD_ADC_DATA(2) In E9 IO_L51N_0 HD Channel #2 ADC bit #2 CH_2_HD_ADC_DATA(3) In E8 IO_L06P_0 HD Channel #2 ADC bit #3 CH_2_HD_ADC_DATA(4) In E7 IO_L06N_0 HD Channel #2 ADC bit #4 CH_2_HD_ADC_DATA(5) In E6 IO_L01N_7 HD Channel #2 ADC bit #5 CH_2_HD_ADC_DATA(6) In H5 IO_L45N_7 HD Channel #2 ADC bit #6 CH_2_HD_ADC_DATA(7) In J5 IO_L52N_7 HD Channel #2 ADC bit #7 CH_2_HD_ADC_DATA(8) In K5 IO_L52P_7/VRP_0 HD Channel #2 ADC bit #8 CH_2_HD_ADC_DATA(9) In L5 IO_L94N_7 HD Channel #2 ADC bit #9 CH_3_EM_ADC_DATA(0) In D1 IO_L03P_7/VREF_7 EM Channel #3 ADC bit #0 CH_3_EM_ADC_DATA(1) In E3 IO_L04P_7 EM Channel #3 ADC bit #1 CH_3_EM_ADC_DATA(2) In F3 IO_L21P_7/VREF_7 EM Channel #3 ADC bit #2 CH_3_EM_ADC_DATA(3) In H3 IO_L46P_7/VREF_0 EM Channel #3 ADC bit #3 CH_3_EM_ADC_DATA(4) In G3 IO_L24P_7 EM Channel #3 ADC bit #4 CH_3_EM_ADC_DATA(5) In F1 IO_L22P_7 EM Channel #3 ADC bit #5 CH_3_EM_ADC_DATA(6) In J3 IO_L49P_7 EM Channel #3 ADC bit #6 CH_3_EM_ADC_DATA(7) In K3 IO_L91P_7 EM Channel #3 ADC bit #7 CH_3_EM_ADC_DATA(8) In J1 IO_L51P_7/VREF_7 EM Channel #3 ADC bit #8 CH_3_EM_ADC_DATA(9) In L3 IO_L96N_7 EM Channel #3 ADC bit #9 CH_3_HD_ADC_DATA(0) In E4 IO_L04N_7/GCLK6S HD Channel #3 ADC bit #0 CH_3_HD_ADC_DATA(1) In E1 IO_L06P_7 HD Channel #3 ADC bit #1 CH_3_HD_ADC_DATA(2) In F4 IO_L21N_7 HD Channel #3 ADC bit #2 CH_3_HD_ADC_DATA(3) In G4 IO_L24N_7 HD Channel #3 ADC bit #3 CH_3_HD_ADC_DATA(4) In G1 IO_L43P_7 HD Channel #3 ADC bit #4 CH_3_HD_ADC_DATA(5) In H4 IO_L46N_7/VREF_0 HD Channel #3 ADC bit #5 CH_3_HD_ADC_DATA(6) In J4 IO_L49N_7 HD Channel #3 ADC bit #6 CH_3_HD_ADC_DATA(7) In K4 IO_L91N_7 HD Channel #3 ADC bit #7 CH_3_HD_ADC_DATA(8) In K1 IO_L93P_7/VREF_7 HD Channel #3 ADC bit #8 CH_3_HD_ADC_DATA(9) In L4 IO_L94P_7 HD Channel #3 ADC bit #9 CH_4_EM_ADC_DATA(0) In L22 IO_L96P_2 EM Channel #4 ADC bit #0 CH_4_EM_ADC_DATA(1) In L21 IO_L96N_2 EM Channel #4 ADC bit #1 CH_4_EM_ADC_DATA(2) In K21 IO_L91N_2 EM Channel #4 ADC bit #2 CH_4_EM_ADC_DATA(3) In J21 IO_L51N_2 EM Channel #4 ADC bit #3 CH_4_EM_ADC_DATA(4) In H21 IO_L46N_2 EM Channel #4 ADC bit #4 CH_4_EM_ADC_DATA(5) In G21 IO_L43N_2 EM Channel #4 ADC bit #5 CH_4_EM_ADC_DATA(6) In F21 IO_L21N_2 EM Channel #4 ADC bit #6 CH_4_EM_ADC_DATA(7) In E21 IO_L06N_2 EM Channel #4 ADC bit #7 CH_4_EM_ADC_DATA(8) In D21 IO_L03N_2 EM Channel #4 ADC bit #8 CH_4_EM_ADC_DATA(9) In C21 IO_L01N_2 EM Channel #4 ADC bit #9 CH_4_HD_ADC_DATA(0) In C18 IO_L02N_1 HD Channel #4 ADC bit #0 CH_4_HD_ADC_DATA(1) In A19 IO_L01N_1/GCLK6S HD Channel #4 ADC bit #1 CH_4_HD_ADC_DATA(2) In C17 IO_L04N_1 HD Channel #4 ADC bit #2 CH_4_HD_ADC_DATA(3) In A17 IO_L05N_1 HD Channel #4 ADC bit #3 CH_4_HD_ADC_DATA(4) In C16 IO_L21N_1/VREF_1 HD Channel #4 ADC bit #4 CH_4_HD_ADC_DATA(5) In C15 IO_L49N_1/VREF_0 HD Channel #4 ADC bit #5 CH_4_HD_ADC_DATA(6) In C14 IO_L52N_1 HD Channel #4 ADC bit #6 CH_4_HD_ADC_DATA(7) In A14 IO_L54N_1 HD Channel #4 ADC bit #7 CH_4_HD_ADC_DATA(8) In C13 IO_L92N_1 HD Channel #4 ADC bit #8 CH_4_HD_ADC_DATA(9) In C12 IO_L94N_1 HD Channel #4 ADC bit #9 CH_5_EM_ADC_DATA(0) In L17 IO_L93N_2/GCLK6S EM Channel #5 ADC bit #0 CH_5_EM_ADC_DATA(1) In K17 IO_L52N_2 EM Channel #5 ADC bit #1 CH_5_EM_ADC_DATA(2) In J17 IO_L48N_2 EM Channel #5 ADC bit #2 CH_5_EM_ADC_DATA(3) In F18 IO_L02P_2/VRN_20 EM Channel #5 ADC bit #3 CH_5_EM_ADC_DATA(4) In G18 IO_L22N_2 EM Channel #5 ADC bit #4 CH_5_EM_ADC_DATA(5) In H22 IO_L46P_2 EM Channel #5 ADC bit #5 CH_5_EM_ADC_DATA(6) In E18 IO_L02N_2/VRP_2 EM Channel #5 ADC bit #6 CH_5_EM_ADC_DATA(7) In F13 IO_L96P_1/GCLK2S EM Channel #5 ADC bit #7 CH_5_EM_ADC_DATA(8) In F14 IO_L24N_1 EM Channel #5 ADC bit #8 CH_5_EM_ADC_DATA(9) In F12 IO_L96N_1/GCLK3P EM Channel #5 ADC bit #9 CH_5_HD_ADC_DATA(0) In B19 IO_L01P_1/GCLK5P HD Channel #5 ADC bit #0 CH_5_HD_ADC_DATA(1) In B18 IO_L03P_1/VRN_1 HD Channel #5 ADC bit #1 CH_5_HD_ADC_DATA(2) In B17 IO_L05P_1 HD Channel #5 ADC bit #2 CH_5_HD_ADC_DATA(3) In B16 IO_L22P_1 HD Channel #5 ADC bit #3 CH_5_HD_ADC_DATA(4) In A16 IO_L22N_1 HD Channel #5 ADC bit #4 CH_5_HD_ADC_DATA(5) In B15 IO_L51P_1 HD Channel #5 ADC bit #5 CH_5_HD_ADC_DATA(6) In B14 IO_L54P_1 HD Channel #5 ADC bit #6 CH_5_HD_ADC_DATA(7) In B13 IO_L93P_1 HD Channel #5 ADC bit #7 CH_5_HD_ADC_DATA(8) In A13 IO_L93N_1/VRP_0 HD Channel #5 ADC bit #8 CH_5_HD_ADC_DATA(9) In B12 IO_L94P_1/VREF_1 HD Channel #5 ADC bit #9 CH_6_EM_ADC_DATA(0) In E19 IO_L04N_2/GCLK5P EM Channel #6 ADC bit #0 CH_6_EM_ADC_DATA(1) In D18 IO_L02P_1 EM Channel #6 ADC bit #1 CH_6_EM_ADC_DATA(2) In A18 IO_L03N_1/VRP_1 EM Channel #6 ADC bit #2 CH_6_EM_ADC_DATA(3) In D15 IO_L49P_1 EM Channel #6 ADC bit #3 CH_6_EM_ADC_DATA(4) In D16 IO_L21P_1 EM Channel #6 ADC bit #4 CH_6_EM_ADC_DATA(5) In D17 IO_L04P_1/VREF_1 EM Channel #6 ADC bit #5 CH_6_EM_ADC_DATA(6) In A15 IO_L51N_1/VREF_1 EM Channel #6 ADC bit #6 CH_6_EM_ADC_DATA(7) In D13 IO_L92P_1/VRP_0 EM Channel #6 ADC bit #7 CH_6_EM_ADC_DATA(8) In D14 IO_L52P_1 EM Channel #6 ADC bit #8 CH_6_EM_ADC_DATA(9) In D12 IO_L95P_1/GCLK0S EM Channel #6 ADC bit #9 CH_6_HD_ADC_DATA(0) In L18 IO_L93P_2/VREF_2 HD Channel #6 ADC bit #0 CH_6_HD_ADC_DATA(1) In K18 IO_L52P_2 HD Channel #6 ADC bit #1 CH_6_HD_ADC_DATA(2) In J18 IO_L48P_2 HD Channel #6 ADC bit #2 CH_6_HD_ADC_DATA(3) In H18 IO_L22P_2 HD Channel #6 ADC bit #3 CH_6_HD_ADC_DATA(4) In E17 IO_L06P_1 HD Channel #6 ADC bit #4 CH_6_HD_ADC_DATA(5) In E16 IO_L06N_1 HD Channel #6 ADC bit #5 CH_6_HD_ADC_DATA(6) In E15 IO_L24P_1 HD Channel #6 ADC bit #6 CH_6_HD_ADC_DATA(7) In E14 IO_L91P_1/VREF_1 HD Channel #6 ADC bit #7 CH_6_HD_ADC_DATA(8) In E13 IO_L91N_1/VRP_0 HD Channel #6 ADC bit #8 CH_6_HD_ADC_DATA(9) In E12 IO_L95N_1/GCLK1P HD Channel #6 ADC bit #9 CH_7_EM_ADC_DATA(0) In L20 IO_L94P_2 EM Channel #7 ADC bit #0 CH_7_EM_ADC_DATA(1) In K20 IO_L54P_2 EM Channel #7 ADC bit #1 CH_7_EM_ADC_DATA(2) In J22 IO_L51P_2/VREF_2 EM Channel #7 ADC bit #2 CH_7_EM_ADC_DATA(3) In G20 IO_L24P_2 EM Channel #7 ADC bit #3 CH_7_EM_ADC_DATA(4) In H20 IO_L45P_2/VREF_2 EM Channel #7 ADC bit #4 CH_7_EM_ADC_DATA(5) In J20 IO_L49P_2 EM Channel #7 ADC bit #5 CH_7_EM_ADC_DATA(6) In F22 IO_L21P_2/VREF_2 EM Channel #7 ADC bit #6 CH_7_EM_ADC_DATA(7) In E20 IO_L04P_2 EM Channel #7 ADC bit #7 CH_7_EM_ADC_DATA(8) In F20 IO_L19P_2 EM Channel #7 ADC bit #8 CH_7_EM_ADC_DATA(9) In D22 IO_L03P_2/VREF_2 EM Channel #7 ADC bit #9 CH_7_HD_ADC_DATA(0) In L19 IO_L94N_2/GCLK6S HD Channel #7 ADC bit #0 CH_7_HD_ADC_DATA(1) In K22 IO_L91P_2 HD Channel #7 ADC bit #1 CH_7_HD_ADC_DATA(2) In K19 IO_L54N_2 HD Channel #7 ADC bit #2 CH_7_HD_ADC_DATA(3) In J19 IO_L49N_2 HD Channel #7 ADC bit #3 CH_7_HD_ADC_DATA(4) In H19 IO_L45N_2 HD Channel #7 ADC bit #4 CH_7_HD_ADC_DATA(5) In G22 IO_L43P_2/VREF_0 HD Channel #7 ADC bit #5 CH_7_HD_ADC_DATA(6) In G19 IO_L24N_2 HD Channel #7 ADC bit #6 CH_7_HD_ADC_DATA(7) In F19 IO_L19N_2 HD Channel #7 ADC bit #7 CH_7_HD_ADC_DATA(8) In E22 IO_L06P_2 HD Channel #7 ADC bit #8 CH_7_HD_ADC_DATA(9) In C22 IO_L01P_2 HD Channel #7 ADC bit #9 ## ADC Clock Signals 16 user IO pins DRV_CH_0_EM_ADC_CLK Out W1 IO_L04N_6 EM Chan #0 ADC Clock DRV_CH_0_HD_ADC_CLK Out V1 IO_L19N_6 HD Chan #0 ADC Clock DRV_CH_1_EM_ADC_CLK Out U1 IO_L21N_6/VREF_6 EM Chan #1 ADC Clock DRV_CH_1_HD_ADC_CLK Out T1 IO_L43N_6 HD Chan #1 ADC Clock DRV_CH_2_EM_ADC_CLK Out R1 IO_L46N_6 EM Chan #2 ADC Clock DRV_CH_2_HD_ADC_CLK Out P1 IO_L51N_6/VREF_6 HD Chan #2 ADC Clock DRV_CH_3_EM_ADC_CLK Out N1 IO_L91N_6 EM Chan #3 ADC Clock DRV_CH_3_HD_ADC_CLK Out M1 IO_L96N_6 HD Chan #3 ADC Clock DRV_CH_4_EM_ADC_CLK Out N22 IO_L91N_3 EM Chan #4 ADC Clock DRV_CH_4_HD_ADC_CLK Out P22 IO_L51N_3/VREF_3 HD Chan #4 ADC Clock DRV_CH_5_EM_ADC_CLK Out R22 IO_L48N_3 EM Chan #5 ADC Clock DRV_CH_5_HD_ADC_CLK Out T22 IO_L43N_3 HD Chan #5 ADC Clock DRV_CH_6_EM_ADC_CLK Out U22 IO_L22N_3 EM Chan #6 ADC Clock DRV_CH_6_HD_ADC_CLK Out V22 IO_L06N_3 HD Chan #6 ADC Clock DRV_CH_7_EM_ADC_CLK Out W22 IO_L03N_3/VREF_3 EM Chan #7 ADC Clock DRV_CH_7_HD_ADC_CLK Out Y22 IO_L02N_3/VRP_3 HD Chan #7 ADC Clock ## Configuration Signals 7 dedicated pins and 4 user IO pins CNFG_CCLK In Y19 CCLK (dedicated) Config Clock generated by Brd Ctrl PAL CNFG_PROG_B(0) In A2 PROG_B (dedicated) Config Prog_B from a Brd Ctrl PAL Reg Bit CNFG_DONE(0) Out AB20 DONE (dedicated) Config Done to a Brd Ctrl PAL Reg Bit CNFG_M0 In AB2 M0 (dedicated) Config Mode Bit#0 CNFG_M1 In W3 M1 (dedicated) Config Mode Bit#1 CNFG_M2 In AB3 M2 (dedicated) Config Mode Bit#2 CNFG_HSWAP_EN In B3 HSWAP_EN (dedicated) Control IO pins during configuration CNFG_RDWR_B In Y4 IO_L01N_5/RDWR_B Config RDWR_B from a Brd Ctrl PAL Reg Bit CNFG_CS_B(0) In AA3 IO_L01P_5/CS_B Config CS_B from a Brd Ctrl PAL Reg Bit CNFG_INIT_B(0) Out AA19 IO_L01P_4/INIT_B Config Init_B to a Brd Ctrl PAL Reg Bit CNFG_BUSY(0) Out AB19 IO_L01N_4/BUSY/DOUT Config Busy to a Brd Ctrl PAL Reg Bit ## JTAG Signals 4 user IO pins JTAG_TCK C19 TCK (dedicated) JTAG Test Data Clock JTAG_TDI_F0 D3 TDI (dedicated) JTAG Test Data In (From Brd Ctrl PAL to F0) JTAG_TDO_F0 D20 TDO (dedicated) JTAG Test Data Out (From F0 to F1) JTAG_TMS B20 TMS (dedicated) JTAG Test Mode Select ## On Card Bus 35 user IO pins OCB_DATA(0) In/Out V18 IO_L02N_4/D0/DIN Card Bus Data Bit #0 OCB_DATA(1) In/Out V17 IO_L02P_4/D1 Card Bus Data Bit #1 OCB_DATA(2) In/Out W18 IO_L03N_4/D2/ALT_VRP_4 Card Bus Data Bit #2 OCB_DATA(3) In/Out Y18 IO_L03P_4/D3/ALT_VRN_4 Card Bus Data Bit #3 OCB_DATA(4) In/Out Y5 IO_L03N_5/D4/ALT_VRP_5 Card Bus Data Bit #4 OCB_DATA(5) In/Out W5 IO_L03P_5/D5/ALT-VRN_5 Card Bus Data Bit #5 OCB_DATA(6) In/Out AB4 IO_L02N_5/D6 Card Bus Data Bit #6 OCB_DATA(7) In/Out AA4 IO_L02P_5/D7 Card Bus Data Bit #7 OCB_DATA(8) In/Out V15 IO_L19P_4 Card Bus Data Bit #8 OCB_DATA(9) In/Out U14 IO_L51N_4 Card Bus Data Bit #9 OCB_DATA(10) In/Out U13 IO_L91N_4/VREF_4 Card Bus Data Bit #10 OCB_DATA(11) In/Out U12 IO_L94N_4/VREF_4 Card Bus Data Bit #11 OCB_DATA(12) In/Out U11 IO_L94N_5 Card Bus Data Bit #12 OCB_DATA(13) In/Out U10 IO_L94P_5/VREF_5 Card Bus Data Bit #13 OCB_DATA(14) In/Out U9 IO_L24N_5 Card Bus Data Bit #14 OCB_DATA(15) In/Out V8 IO_L24P_5 Card Bus Data Bit #15 OCB_ADRS(1) In V6 IO_L05P_5/VRN_5 Card Bus Addr Bit #1 OCB_ADRS(2) In V7 IO_L05N_5/VRP_5 Card Bus Addr Bit #2 OCB_ADRS(3) In V9 IO_L91P_5/VREF_5 Card Bus Addr Bit #3 OCB_ADRS(4) In V10 IO_L91N_5 Card Bus Addr Bit #4 OCB_ADRS(5) In V12 IO_L94P_4 Card Bus Addr Bit #5 OCB_ADRS(6) In V13 IO_L91P_4 Card Bus Addr Bit #6 OCB_ADRS(7) In V14 IO_L51P_4/VREF_4 Card Bus Addr Bit #7 OCB_ADRS(8) In V16 IO_L19N_4 Card Bus Addr Bit #8 OCB_ADRS(9) In W6 IO_L06P_5 Card Bus Addr Bit #9 OCB_ADRS(10) In W7 IO_L21P_5 Card Bus Addr Bit #10 OCB_ADRS(11) In W8 IO_L49P_5 Card Bus Addr Bit #11 OCB_ADRS(12) In W9 IO_L52P_5 Card Bus Addr Bit #12 OCB_ADRS(13) In W10 IO_L92P_5 Card Bus Addr Bit #13 OCB_ADRS(14) In W13 IO_L92N_4 Card Bus Addr Bit #14 OCB_ADRS(15) In W14 IO_L52N_4 Card Bus Addr Bit #15 OCB_ADRS(16) In W15 IO_L24N_4 Card Bus Addr Bit #16 OCB_CHIP_SEL_B(0) In W17 IO_L05N_4/VRP_4 Card Bus Chip Select OCB_DIRECTION In W16 IO_L21N_4 Card Bus Direction OCB_WRITE_STRB_B In Y6 IO_L06N_5 Card Bus Write Strobe ## FPGA ID Signal 1 user IO pin FPGA_ID_F0 In N20 IO_L54N_3 Low for F0, High for F1 ## Status Lines to the Board Control PAL 4 pins FPGA_0_STATUS(0) Out AB18 IO_L04P_4 Status bit #0 to Brd Ctrl PAL FPGA_0_STATUS(1) Out AB17 IO_L06P_4 Status bit #1 to Brd Ctrl PAL FPGA_0_STATUS(2) Out AB16 IO_L22P_4 Status bit #2 to Brd Ctrl PAL FPGA_0_STATUS(3) Out AB15 IO_L49P_4 Status bit #3 to Brd Ctrl PAL ## SCLD Control Signals 5 user IO pins RCVD_BEGIN_TURN In AB10 IO_L93N_5 Begin of Turn from SCLD RCVD_LIVE_BX In AB9 IO_L54N_5 Live Beam Crossing from SCLD RCVD_SAVE_MONIT_DATA In AB8 IO_L51N_5/VREF_5 Save Monit Data from SCLD RCVD_SCL_INIT In AB7 IO_L22N_5 SCL Initialize from SCLD RCVD_SCLD_SPARE In AB6 IO_L19N_5 Spare Signal from SCLD ## Signals for the Channel Link 25 user IO pins SER_CH_0_EM Out M2 IO_L96P_6 EM Chan #0 Et Serial Output SER_CH_0_HD Out N2 IO_L91P_6 HD Chan #0 Et Serial Output SER_CH_1_EM Out P2 IO_L51P_6 EM Chan #1 Et Serial Output SER_CH_1_HD Out R2 IO_L46P_6 HD Chan #1 Et Serial Output SER_CH_2_EM Out T2 IO_L43P_6 EM Chan #2 Et Serial Output SER_CH_2_HD Out U2 IO_L21P_6 HD Chan #2 Et Serial Output SER_CH_3_EM Out V2 IO_L19P_6 EM Chan #3 Et Serial Output SER_CH_3_HD Out W2 IO_L04P_6 HD Chan #3 Et Serial Output SER_CH_4_EM Out W21 IO_L03P_3 EM Chan #4 Et Serial Output SER_CH_4_HD Out V21 IO_L06P_3 HD Chan #4 Et Serial Output SER_CH_5_EM Out U21 IO_L22P_3 EM Chan #5 Et Serial Output SER_CH_5_HD Out T21 IO_L43P_3 HD Chan #5 Et Serial Output SER_CH_6_EM Out R21 IO_L48P_3 EM Chan #6 Et Serial Output SER_CH_6_HD Out P21 IO_L51P_3 HD Chan #6 Et Serial Output SER_CH_7_EM Out N21 IO_L91P_3 EM Chan #7 Et Serial Output SER_CH_7_HD Out M21 IO_L96N_3 HD Chan #7 Et Serial Output SER_FRAME_F0 Out U3 IO_L06N_6 Begin of Frame Serial Output SER_BX_COUNT_F0 Out T3 IO_L24N_6 Beam Cross ID Serial Output SER_RSVD_F0(0) Out V20 IO_L04N_3 Reserved Serial Output SER_RSVD_F0(1) Out T20 IO_L24N_3 Reserved Serial Output SER_RSVD_F0(2) Out R20 IO_L46N_3 Reserved Serial Output SER_RSVD_F0(3) Out W20 IO_L01N_3 Reserved Serial Output SER_PARITY_F0 Out V3 IO_L03N_6/VREF_6 Parity Bit Serial Output LOC_PARITY_OUT_F0 Out P3 IO_L49N_6 \ LOC_PARITY_OUT_F1 connected LOC_PARITY_IN_F0 In P20 IO_L49N_3 / to LOC_PARITY_IN_F0 ## LED pins 4 user IO pins F0_LED_0 Out AA8 IO_L51P_5 FPGA F0 LED 0 F0_LED_1 Out AA11 IO_L96N_5/GCLK7S FPGA F0 LED 1 F0_LED_2 Out AA16 IO_L22N_4 FPGA F0 LED 2 F0_LED_3 Out AA17 IO_L06N_4 FPGA F0 LED 3 ## Access Connector pins 12 user IO pins 4 clock net pins F0_ACCESS_0 I/O N4 IO_L54P_6 F0_ACCESS_1 I/O N3 IO_L54N_6 F0_ACCESS_2 I/O R4 IO_L45P_6 F0_ACCESS_3 I/O R3 IO_L45N_6/VREF_6 F0_ACCESS_4 I/O AA5 IO_L04P_5/VREF_5 F0_ACCESS_5 I/O AB5 IO_L04N_5 F0_ACCESS_6 I/O V11 IO_L95P_5/GCLK4P F0_ACCESS_7 I/O W11 IO_L95N_5/GCLK5S F0_ACCESS_8 I/O W12 IO_L95N_4/GCLK3S F0_ACCESS_9 I/O Y12 IO_L95P_4/GCLK2P F0_ACCESS_10 I/O AA14 IO_L54N_4 F0_ACCESS_11 I/O AB14 IO_L54P_4 F0_ACCESS_12 I/O U20 IO_L21N_3/VREF_3 F0_ACCESS_13 I/O U19 IO_L21P_3 F0_ACCESS_14 I/O R18 IO_L45N_3/VREF_3 F0_ACCESS_15 I/O P17 IO_L45P_3 ============================================================================== general clock input user /IO dedicated pins pins pins ## Clock Inputs 2 ## ADC Data 10 x 2 x 8 = 160 ## ADC Clock Signals 16 ## Configuration Signals 4 7 ## JTAG Signals 4 ## On Card Bus 35 ## FPGA ID Signal 1 ## Status Lines to the Board Control PAL 4 ## SCLD Control Signals 5 ## Signals to the Channel Link 25 ## LED pins 4 ## Access Connector pins 4 12 ------------------------------------------ Total 6 266 10 The XC2V1000-4FG456C has 324 user I/O pins including 16 clock input pins ============================================================================== Comparison of FPGA F0 vs F1 Net Names -------------------------------------- Original Rev. 18-MAY-2004 FPGA F0 FPGA F1 Net Name Net Name Difference --------------------- --------------------- ------------------------- ## Beam Crossing Clock BX_X8_CLK_F0 BX_X8_CLK_F1 Separate Copies of Same FIRST_X8_EDGE_F0 FIRST_X8_EDGE_F1 Separate Copies of Same ## ADC Data CH_0_EM_ADC_DATA(0) CH_8_EM_ADC_DATA(0) Different Channels CH_0_EM_ADC_DATA(1) CH_8_EM_ADC_DATA(1) Different Channels CH_0_EM_ADC_DATA(2) CH_8_EM_ADC_DATA(2) Different Channels CH_0_EM_ADC_DATA(3) CH_8_EM_ADC_DATA(3) Different Channels CH_0_EM_ADC_DATA(4) CH_8_EM_ADC_DATA(4) Different Channels CH_0_EM_ADC_DATA(5) CH_8_EM_ADC_DATA(5) Different Channels CH_0_EM_ADC_DATA(6) CH_8_EM_ADC_DATA(6) Different Channels CH_0_EM_ADC_DATA(7) CH_8_EM_ADC_DATA(7) Different Channels CH_0_EM_ADC_DATA(8) CH_8_EM_ADC_DATA(8) Different Channels CH_0_EM_ADC_DATA(9) CH_8_EM_ADC_DATA(9) Different Channels CH_0_HD_ADC_DATA(0) CH_8_HD_ADC_DATA(0) Different Channels CH_0_HD_ADC_DATA(1) CH_8_HD_ADC_DATA(1) Different Channels CH_0_HD_ADC_DATA(2) CH_8_HD_ADC_DATA(2) Different Channels CH_0_HD_ADC_DATA(3) CH_8_HD_ADC_DATA(3) Different Channels CH_0_HD_ADC_DATA(4) CH_8_HD_ADC_DATA(4) Different Channels CH_0_HD_ADC_DATA(5) CH_8_HD_ADC_DATA(5) Different Channels CH_0_HD_ADC_DATA(6) CH_8_HD_ADC_DATA(6) Different Channels CH_0_HD_ADC_DATA(7) CH_8_HD_ADC_DATA(7) Different Channels CH_0_HD_ADC_DATA(8) CH_8_HD_ADC_DATA(8) Different Channels CH_0_HD_ADC_DATA(9) CH_8_HD_ADC_DATA(9) Different Channels CH_1_EM_ADC_DATA(0) CH_9_EM_ADC_DATA(0) Different Channels CH_1_EM_ADC_DATA(1) CH_9_EM_ADC_DATA(1) Different Channels CH_1_EM_ADC_DATA(2) CH_9_EM_ADC_DATA(2) Different Channels CH_1_EM_ADC_DATA(3) CH_9_EM_ADC_DATA(3) Different Channels CH_1_EM_ADC_DATA(4) CH_9_EM_ADC_DATA(4) Different Channels CH_1_EM_ADC_DATA(5) CH_9_EM_ADC_DATA(5) Different Channels CH_1_EM_ADC_DATA(6) CH_9_EM_ADC_DATA(6) Different Channels CH_1_EM_ADC_DATA(7) CH_9_EM_ADC_DATA(7) Different Channels CH_1_EM_ADC_DATA(8) CH_9_EM_ADC_DATA(8) Different Channels CH_1_EM_ADC_DATA(9) CH_9_EM_ADC_DATA(9) Different Channels CH_1_HD_ADC_DATA(0) CH_9_HD_ADC_DATA(0) Different Channels CH_1_HD_ADC_DATA(1) CH_9_HD_ADC_DATA(1) Different Channels CH_1_HD_ADC_DATA(2) CH_9_HD_ADC_DATA(2) Different Channels CH_1_HD_ADC_DATA(3) CH_9_HD_ADC_DATA(3) Different Channels CH_1_HD_ADC_DATA(4) CH_9_HD_ADC_DATA(4) Different Channels CH_1_HD_ADC_DATA(5) CH_9_HD_ADC_DATA(5) Different Channels CH_1_HD_ADC_DATA(6) CH_9_HD_ADC_DATA(6) Different Channels CH_1_HD_ADC_DATA(7) CH_9_HD_ADC_DATA(7) Different Channels CH_1_HD_ADC_DATA(8) CH_9_HD_ADC_DATA(8) Different Channels CH_1_HD_ADC_DATA(9) CH_9_HD_ADC_DATA(9) Different Channels CH_2_EM_ADC_DATA(0) CH_10_EM_ADC_DATA(0) Different Channels CH_2_EM_ADC_DATA(1) CH_10_EM_ADC_DATA(1) Different Channels CH_2_EM_ADC_DATA(2) CH_10_EM_ADC_DATA(2) Different Channels CH_2_EM_ADC_DATA(3) CH_10_EM_ADC_DATA(3) Different Channels CH_2_EM_ADC_DATA(4) CH_10_EM_ADC_DATA(4) Different Channels CH_2_EM_ADC_DATA(5) CH_10_EM_ADC_DATA(5) Different Channels CH_2_EM_ADC_DATA(6) CH_10_EM_ADC_DATA(6) Different Channels CH_2_EM_ADC_DATA(7) CH_10_EM_ADC_DATA(7) Different Channels CH_2_EM_ADC_DATA(8) CH_10_EM_ADC_DATA(8) Different Channels CH_2_EM_ADC_DATA(9) CH_10_EM_ADC_DATA(9) Different Channels CH_2_HD_ADC_DATA(0) CH_10_HD_ADC_DATA(0) Different Channels CH_2_HD_ADC_DATA(1) CH_10_HD_ADC_DATA(1) Different Channels CH_2_HD_ADC_DATA(2) CH_10_HD_ADC_DATA(2) Different Channels CH_2_HD_ADC_DATA(3) CH_10_HD_ADC_DATA(3) Different Channels CH_2_HD_ADC_DATA(4) CH_10_HD_ADC_DATA(4) Different Channels CH_2_HD_ADC_DATA(5) CH_10_HD_ADC_DATA(5) Different Channels CH_2_HD_ADC_DATA(6) CH_10_HD_ADC_DATA(6) Different Channels CH_2_HD_ADC_DATA(7) CH_10_HD_ADC_DATA(7) Different Channels CH_2_HD_ADC_DATA(8) CH_10_HD_ADC_DATA(8) Different Channels CH_2_HD_ADC_DATA(9) CH_10_HD_ADC_DATA(9) Different Channels CH_3_EM_ADC_DATA(0) CH_11_EM_ADC_DATA(0) Different Channels CH_3_EM_ADC_DATA(1) CH_11_EM_ADC_DATA(1) Different Channels CH_3_EM_ADC_DATA(2) CH_11_EM_ADC_DATA(2) Different Channels CH_3_EM_ADC_DATA(3) CH_11_EM_ADC_DATA(3) Different Channels CH_3_EM_ADC_DATA(4) CH_11_EM_ADC_DATA(4) Different Channels CH_3_EM_ADC_DATA(5) CH_11_EM_ADC_DATA(5) Different Channels CH_3_EM_ADC_DATA(6) CH_11_EM_ADC_DATA(6) Different Channels CH_3_EM_ADC_DATA(7) CH_11_EM_ADC_DATA(7) Different Channels CH_3_EM_ADC_DATA(8) CH_11_EM_ADC_DATA(8) Different Channels CH_3_EM_ADC_DATA(9) CH_11_EM_ADC_DATA(9) Different Channels CH_3_HD_ADC_DATA(0) CH_11_HD_ADC_DATA(0) Different Channels CH_3_HD_ADC_DATA(1) CH_11_HD_ADC_DATA(1) Different Channels CH_3_HD_ADC_DATA(2) CH_11_HD_ADC_DATA(2) Different Channels CH_3_HD_ADC_DATA(3) CH_11_HD_ADC_DATA(3) Different Channels CH_3_HD_ADC_DATA(4) CH_11_HD_ADC_DATA(4) Different Channels CH_3_HD_ADC_DATA(5) CH_11_HD_ADC_DATA(5) Different Channels CH_3_HD_ADC_DATA(6) CH_11_HD_ADC_DATA(6) Different Channels CH_3_HD_ADC_DATA(7) CH_11_HD_ADC_DATA(7) Different Channels CH_3_HD_ADC_DATA(8) CH_11_HD_ADC_DATA(8) Different Channels CH_3_HD_ADC_DATA(9) CH_11_HD_ADC_DATA(9) Different Channels CH_4_EM_ADC_DATA(0) CH_12_EM_ADC_DATA(0) Different Channels CH_4_EM_ADC_DATA(1) CH_12_EM_ADC_DATA(1) Different Channels CH_4_EM_ADC_DATA(2) CH_12_EM_ADC_DATA(2) Different Channels CH_4_EM_ADC_DATA(3) CH_12_EM_ADC_DATA(3) Different Channels CH_4_EM_ADC_DATA(4) CH_12_EM_ADC_DATA(4) Different Channels CH_4_EM_ADC_DATA(5) CH_12_EM_ADC_DATA(5) Different Channels CH_4_EM_ADC_DATA(6) CH_12_EM_ADC_DATA(6) Different Channels CH_4_EM_ADC_DATA(7) CH_12_EM_ADC_DATA(7) Different Channels CH_4_EM_ADC_DATA(8) CH_12_EM_ADC_DATA(8) Different Channels CH_4_EM_ADC_DATA(9) CH_12_EM_ADC_DATA(9) Different Channels CH_4_HD_ADC_DATA(0) CH_12_HD_ADC_DATA(0) Different Channels CH_4_HD_ADC_DATA(1) CH_12_HD_ADC_DATA(1) Different Channels CH_4_HD_ADC_DATA(2) CH_12_HD_ADC_DATA(2) Different Channels CH_4_HD_ADC_DATA(3) CH_12_HD_ADC_DATA(3) Different Channels CH_4_HD_ADC_DATA(4) CH_12_HD_ADC_DATA(4) Different Channels CH_4_HD_ADC_DATA(5) CH_12_HD_ADC_DATA(5) Different Channels CH_4_HD_ADC_DATA(6) CH_12_HD_ADC_DATA(6) Different Channels CH_4_HD_ADC_DATA(7) CH_12_HD_ADC_DATA(7) Different Channels CH_4_HD_ADC_DATA(8) CH_12_HD_ADC_DATA(8) Different Channels CH_4_HD_ADC_DATA(9) CH_12_HD_ADC_DATA(9) Different Channels CH_5_EM_ADC_DATA(0) CH_13_EM_ADC_DATA(0) Different Channels CH_5_EM_ADC_DATA(1) CH_13_EM_ADC_DATA(1) Different Channels CH_5_EM_ADC_DATA(2) CH_13_EM_ADC_DATA(2) Different Channels CH_5_EM_ADC_DATA(3) CH_13_EM_ADC_DATA(3) Different Channels CH_5_EM_ADC_DATA(4) CH_13_EM_ADC_DATA(4) Different Channels CH_5_EM_ADC_DATA(5) CH_13_EM_ADC_DATA(5) Different Channels CH_5_EM_ADC_DATA(6) CH_13_EM_ADC_DATA(6) Different Channels CH_5_EM_ADC_DATA(7) CH_13_EM_ADC_DATA(7) Different Channels CH_5_EM_ADC_DATA(8) CH_13_EM_ADC_DATA(8) Different Channels CH_5_EM_ADC_DATA(9) CH_13_EM_ADC_DATA(9) Different Channels CH_5_HD_ADC_DATA(0) CH_13_HD_ADC_DATA(0) Different Channels CH_5_HD_ADC_DATA(1) CH_13_HD_ADC_DATA(1) Different Channels CH_5_HD_ADC_DATA(2) CH_13_HD_ADC_DATA(2) Different Channels CH_5_HD_ADC_DATA(3) CH_13_HD_ADC_DATA(3) Different Channels CH_5_HD_ADC_DATA(4) CH_13_HD_ADC_DATA(4) Different Channels CH_5_HD_ADC_DATA(5) CH_13_HD_ADC_DATA(5) Different Channels CH_5_HD_ADC_DATA(6) CH_13_HD_ADC_DATA(6) Different Channels CH_5_HD_ADC_DATA(7) CH_13_HD_ADC_DATA(7) Different Channels CH_5_HD_ADC_DATA(8) CH_13_HD_ADC_DATA(8) Different Channels CH_5_HD_ADC_DATA(9) CH_13_HD_ADC_DATA(9) Different Channels CH_6_EM_ADC_DATA(0) CH_14_EM_ADC_DATA(0) Different Channels CH_6_EM_ADC_DATA(1) CH_14_EM_ADC_DATA(1) Different Channels CH_6_EM_ADC_DATA(2) CH_14_EM_ADC_DATA(2) Different Channels CH_6_EM_ADC_DATA(3) CH_14_EM_ADC_DATA(3) Different Channels CH_6_EM_ADC_DATA(4) CH_14_EM_ADC_DATA(4) Different Channels CH_6_EM_ADC_DATA(5) CH_14_EM_ADC_DATA(5) Different Channels CH_6_EM_ADC_DATA(6) CH_14_EM_ADC_DATA(6) Different Channels CH_6_EM_ADC_DATA(7) CH_14_EM_ADC_DATA(7) Different Channels CH_6_EM_ADC_DATA(8) CH_14_EM_ADC_DATA(8) Different Channels CH_6_EM_ADC_DATA(9) CH_14_EM_ADC_DATA(9) Different Channels CH_6_HD_ADC_DATA(0) CH_14_HD_ADC_DATA(0) Different Channels CH_6_HD_ADC_DATA(1) CH_14_HD_ADC_DATA(1) Different Channels CH_6_HD_ADC_DATA(2) CH_14_HD_ADC_DATA(2) Different Channels CH_6_HD_ADC_DATA(3) CH_14_HD_ADC_DATA(3) Different Channels CH_6_HD_ADC_DATA(4) CH_14_HD_ADC_DATA(4) Different Channels CH_6_HD_ADC_DATA(5) CH_14_HD_ADC_DATA(5) Different Channels CH_6_HD_ADC_DATA(6) CH_14_HD_ADC_DATA(6) Different Channels CH_6_HD_ADC_DATA(7) CH_14_HD_ADC_DATA(7) Different Channels CH_6_HD_ADC_DATA(8) CH_14_HD_ADC_DATA(8) Different Channels CH_6_HD_ADC_DATA(9) CH_14_HD_ADC_DATA(9) Different Channels CH_7_EM_ADC_DATA(0) CH_15_EM_ADC_DATA(0) Different Channels CH_7_EM_ADC_DATA(1) CH_15_EM_ADC_DATA(1) Different Channels CH_7_EM_ADC_DATA(2) CH_15_EM_ADC_DATA(2) Different Channels CH_7_EM_ADC_DATA(3) CH_15_EM_ADC_DATA(3) Different Channels CH_7_EM_ADC_DATA(4) CH_15_EM_ADC_DATA(4) Different Channels CH_7_EM_ADC_DATA(5) CH_15_EM_ADC_DATA(5) Different Channels CH_7_EM_ADC_DATA(6) CH_15_EM_ADC_DATA(6) Different Channels CH_7_EM_ADC_DATA(7) CH_15_EM_ADC_DATA(7) Different Channels CH_7_EM_ADC_DATA(8) CH_15_EM_ADC_DATA(8) Different Channels CH_7_EM_ADC_DATA(9) CH_15_EM_ADC_DATA(9) Different Channels CH_7_HD_ADC_DATA(0) CH_15_HD_ADC_DATA(0) Different Channels CH_7_HD_ADC_DATA(1) CH_15_HD_ADC_DATA(1) Different Channels CH_7_HD_ADC_DATA(2) CH_15_HD_ADC_DATA(2) Different Channels CH_7_HD_ADC_DATA(3) CH_15_HD_ADC_DATA(3) Different Channels CH_7_HD_ADC_DATA(4) CH_15_HD_ADC_DATA(4) Different Channels CH_7_HD_ADC_DATA(5) CH_15_HD_ADC_DATA(5) Different Channels CH_7_HD_ADC_DATA(6) CH_15_HD_ADC_DATA(6) Different Channels CH_7_HD_ADC_DATA(7) CH_15_HD_ADC_DATA(7) Different Channels CH_7_HD_ADC_DATA(8) CH_15_HD_ADC_DATA(8) Different Channels CH_7_HD_ADC_DATA(9) CH_15_HD_ADC_DATA(9) Different Channels ## ADC Clock Signals CH_0_EM_ADC_CLK CH_8_EM_ADC_CLK Different Channels CH_0_HD_ADC_CLK CH_8_HD_ADC_CLK Different Channels CH_1_EM_ADC_CLK CH_9_EM_ADC_CLK Different Channels CH_1_HD_ADC_CLK CH_9_HD_ADC_CLK Different Channels CH_2_EM_ADC_CLK CH_10_EM_ADC_CLK Different Channels CH_2_HD_ADC_CLK CH_10_HD_ADC_CLK Different Channels CH_3_EM_ADC_CLK CH_11_EM_ADC_CLK Different Channels CH_3_HD_ADC_CLK CH_11_HD_ADC_CLK Different Channels CH_4_EM_ADC_CLK CH_12_EM_ADC_CLK Different Channels CH_4_HD_ADC_CLK CH_12_HD_ADC_CLK Different Channels CH_5_EM_ADC_CLK CH_13_EM_ADC_CLK Different Channels CH_5_HD_ADC_CLK CH_13_HD_ADC_CLK Different Channels CH_6_EM_ADC_CLK CH_14_EM_ADC_CLK Different Channels CH_6_HD_ADC_CLK CH_14_HD_ADC_CLK Different Channels CH_7_EM_ADC_CLK CH_15_EM_ADC_CLK Different Channels CH_7_HD_ADC_CLK CH_15_HD_ADC_CLK Different Channels ## Configuration Signal CNFG_CCLK CNFG_CCLK Bussed Signal from PAL CNFG_PROG_B(0) CNFG_PROG_B(1) Private Signal from PAL CNFG_DONE(0) CNFG_DONE(1) Private Signal to PAL CNFG_M0 CNFG_M0 Same Constant Level Bussed CNFG_M1 CNFG_M1 Same Constant Level Bussed CNFG_M2 CNFG_M2 Same Constant Level Bussed CNFG_HSWAP_EN CNFG_HSWAP_EN Bussed Signal from PAL CNFG_RDWR_B CNFG_RDWR_B Bussed Signal from PAL CNFG_CS_B(0) CNFG_CS_B(1) Private Signal from PAL CNFG_INIT_B(0) CNFG_INIT_B(1) Private Signal to PAL CNFG_BUSY(0) CNFG_BUSY(1) Private Signal to PAL ## JTAG Signals JTAG_TCK JTAG_TCK Same Signal Bussed JTAG_TDI_F0 JTAG_TDI_F1 \ Externally JTAG_TDO_F0 JTAG_TDO_F1 / Daisy Chained JTAG_TMS JTAG_TMS Same Signal Bussed ## On Card Bus OCB_DATA(0) OCB_DATA(0) Same Signal Bussed OCB_DATA(1) OCB_DATA(1) Same Signal Bussed OCB_DATA(2) OCB_DATA(2) Same Signal Bussed OCB_DATA(3) OCB_DATA(3) Same Signal Bussed OCB_DATA(4) OCB_DATA(4) Same Signal Bussed OCB_DATA(5) OCB_DATA(5) Same Signal Bussed OCB_DATA(6) OCB_DATA(6) Same Signal Bussed OCB_DATA(7) OCB_DATA(7) Same Signal Bussed OCB_DATA(8) OCB_DATA(8) Same Signal Bussed OCB_DATA(9) OCB_DATA(9) Same Signal Bussed OCB_DATA(10) OCB_DATA(10) Same Signal Bussed OCB_DATA(11) OCB_DATA(11) Same Signal Bussed OCB_DATA(12) OCB_DATA(12) Same Signal Bussed OCB_DATA(13) OCB_DATA(13) Same Signal Bussed OCB_DATA(14) OCB_DATA(14) Same Signal Bussed OCB_DATA(15) OCB_DATA(15) Same Signal Bussed OCB_ADDR(1) OCB_ADDR(1) Same Signal Bussed OCB_ADDR(2) OCB_ADDR(2) Same Signal Bussed OCB_ADDR(3) OCB_ADDR(3) Same Signal Bussed OCB_ADDR(4) OCB_ADDR(4) Same Signal Bussed OCB_ADDR(5) OCB_ADDR(5) Same Signal Bussed OCB_ADDR(6) OCB_ADDR(6) Same Signal Bussed OCB_ADDR(7) OCB_ADDR(7) Same Signal Bussed OCB_ADDR(8) OCB_ADDR(8) Same Signal Bussed OCB_ADDR(9) OCB_ADDR(9) Same Signal Bussed OCB_ADDR(10) OCB_ADDR(10) Same Signal Bussed OCB_ADDR(11) OCB_ADDR(11) Same Signal Bussed OCB_ADDR(12) OCB_ADDR(12) Same Signal Bussed OCB_ADDR(13) OCB_ADDR(13) Same Signal Bussed OCB_ADDR(14) OCB_ADDR(14) Same Signal Bussed OCB_ADDR(15) OCB_ADDR(15) Same Signal Bussed OCB_ADDR(16) OCB_ADDR(16) Same Signal Bussed OCB_CHIP_SEL_B(0) OCB_CHIP_SEL_B(1) Same Signal Bussed OCB_DIRECTION OCB_DIRECTION Same Signal Bussed OCB_WRITE_STRB_B OCB_WRITE_STRB_B Same Signal Bussed ## FPGA ID Signal FPGA_ID_F0 FPGA_ID_F1 Separate Constant Level ## Status Lines to the Board Control PAL FPGA_0_STATUS(0) FPGA_1_STATUS(0) Private Signal to PAL FPGA_0_STATUS(1) FPGA_1_STATUS(1) Private Signal to PAL FPGA_0_STATUS(2) FPGA_1_STATUS(2) Private Signal to PAL FPGA_0_STATUS(3) FPGA_1_STATUS(3) Private Signal to PAL ## SCLD Control Signals RCVD_BEGIN_TURN RCVD_BEGIN_TURN Same Signal Bussed RCVD_LIVE_BX RCVD_LIVE_BX Same Signal Bussed RCVD_SAVE_MONIT_DATA RCVD_SAVE_MONIT_DATA Same Signal Bussed RCVD_SCL_INIT RCVD_SCL_INIT Same Signal Bussed RCVD_SPARE RCVD_SPARE Same Signal Bussed ## Signals for the Channel Link Transmitter SER_CH_0_EM SER_CH_8_EM Different Channels SER_CH_0_HD SER_CH_8_HD Different Channels SER_CH_1_EM SER_CH_9_EM Different Channels SER_CH_1_HD SER_CH_9_HD Different Channels SER_CH_2_EM SER_CH_10_EM Different Channels SER_CH_2_HD SER_CH_10_HD Different Channels SER_CH_3_EM SER_CH_11_EM Different Channels SER_CH_3_HD SER_CH_11_HD Different Channels SER_CH_4_EM SER_CH_12_EM Different Channels SER_CH_4_HD SER_CH_12_HD Different Channels SER_CH_5_EM SER_CH_13_EM Different Channels SER_CH_5_HD SER_CH_13_HD Different Channels SER_CH_6_EM SER_CH_14_EM Different Channels SER_CH_6_HD SER_CH_14_HD Different Channels SER_CH_7_EM SER_CH_15_EM Different Channels SER_CH_7_HD SER_CH_15_HD Different Channels SER_FRAME_F0 SER_FRAME_F1 (NC) Only F0 Signal Used SER_BX_COUNT_F0 SER_BX_COUNT_F1 (NC) Only F0 Signal Used SER_RSVD_F0(0:3) SER_RSVD_F1(0:3) SER_RSVD_F1(3) Unused SER_PARITY_F0 SER_PARITY_F1 (NC) Only F0 Signal Used LOC_PARITY_OUT_F0 (NC) LOC_PARITY_OUT_F1 \ LOC_PARITY_OUT_F1 goes LOC_PARITY_IN_F0 LOC_PARITY_IN_F1 (GND) / to LOC_PARITY_IN_F0 ## LED pins about 6 LED's about 6 LED's ## DeBug Connector pins about 16 signal about 16 signal