# This is a Key In Net List file for # the ADF-2 for the Run IIB Cal Trig # Drive the Crate Status to the Backplane # and Driver Status to SCLD Nets # ------------------------------------------- # # Original Rev. 10-JUNE-2004 # Most Recent Rev. 9-SEPT-2004 # This file includes the nets that take the Crate Status signals # from the Board Control PAL and drive them onto the backplane as # open collector signals. That driving is done by U1031. # Connection of the Crate Status nets to the VME-64X Reserved Bused # backplane pins is taken care of in the P1 net list file. # # This file also contains the nets for driving the VLDS Crate to # SCLD signals back to the SCLD. That driving is done by U1061. # Connection of nets to the P0 connector is taken care of in the # P0 (P3) net list file. # # These circuits are shown in the drawing: # # www.pa.msu.edu/hep/d0/ftp/run2b/l1cal/hardware/adf_2/drawings/ # board_control_pal_board_level_control.ps # board_control_pal_board_level_control.pdf # This file contains the nets for the following components: # # U1031 SN74AS756 Inverting O.C. Driver Octal # # U1071 SN65LVDS31 Quad LVDS Driver 2 of 4 drivers used # # C1071 0.1 uFd bypass capacitors to Vdd_Logic # # C1072 4.7 nFd bypass capacitors to Vdd_Logic # # W1071, W1072 Zero Ohm 0603 control input to unused LVDS Drivers # # R1073, R1074 100 Ohm 0603 terminators for the unused LVDS Drivers # Note that other sections of U1031 are used in the net files: # # vme_to_board_control_pal_nets.txt # receive_scld_drive_backplane_nets.txt # power_up_supervisor_nets.txt # Crate Status # # Connect the Crate Wide Status signals coming out of the Board # Control PAL to the inputs of the open collector drivers. Then # connect the output from these drivers to the backplane pins for # the VME-64X Reserved Bused lines that carry the Crate Status signals. NET 'DRV_CRATE_STATUS(0)' U1031-4 # Connect the Board Control PAL drive # control signal for Crate Status 0 # to the driver input. NET 'CRATE_STATUS_B(0)' U1031-16 # Connect the driver output for # the Crate Status 0 signal to # the P1 backplane pin. NET 'DRV_CRATE_STATUS(1)' U1031-6 # Connect the Board Control PAL drive # control signal for Crate Status 1 # to the driver input. NET 'CRATE_STATUS_B(1)' U1031-14 # Connect the driver output for # the Crate Status 1 signal to # the P1 backplane pin. NET 'DRV_CRATE_STATUS(2)' U1031-13 # Connect the Board Control PAL drive # control signal for Crate Status 2 # to the driver input. NET 'CRATE_STATUS_B(2)' U1031-7 # Connect the driver output for # the Crate Status 2 signal to # the P1 backplane pin. NET 'DRV_CRATE_STATUS(3)' U1031-11 # Connect the Board Control PAL drive # control signal for Crate Status 3 # to the driver input. NET 'CRATE_STATUS_B(3)' U1031-9 # Connect the driver output for # the Crate Status 3 signal to # the P1 backplane pin. # Status to SCLD # # The followind nets are used to drive the Status to SCLD signals. # These status signals come from the Board Control PAL and are # converted to LVDS by U1071 the LBDS driver chip. There are 2 # of these Status to SCLD signal. The other 2 channels of the quad # LVDS driver are not used but terminator resistors are provided # for these 2 unused sections of the driver chip. NET 'DRV_CRATE_TO_SCLD(0)' U1071-15 # Connect the drive control signal # from the Board Control PAL to the # LVDS driver intput. NET 'CRATE_TO_SCLD_0_P' U1071-14 # Connect the direct and the NET 'CRATE_TO_SCLD_0_N' U1071-13 # complement driver outputs # to their P0 backplane pins. NET 'DRV_CRATE_TO_SCLD(1)' U1071-9 # Connect the drive control signal # from the Board Control PAL to the # LVDS driver intput. NET 'CRATE_TO_SCLD_1_P' U1071-10 # Connect the direct and the NET 'CRATE_TO_SCLD_1_N' U1071-11 # complement driver outputs # to their P0 backplane pins. # Connect the pins to Enable the LVDS Driver Outputs. NET 'GROUND' U1071-4 U1071-12 # Ground both the G and the G_B Enable # pins. Because G_B Enable is grounded # the outputs will be enabled. # Connect the power and ground supplies to the LVDS driver chip. NET 'VDD_LOGIC' U1071-16 # +3.3 Volt supply NET 'GROUND' U1071-8 # Ground connection # Bypass capacitors for the LVDS driver chip. NET 'VDD_LOGIC' C1071-2 C1072-2 # +3.3 Volt supply NET 'GROUND' C1071-1 C1072-1 # Ground connection # Two unused sections of U1071 the LVDS Driver # Connect the inputs to the unused LVDS Driver sections to Gnd. This # connection to Gnd is done through zero Ohm jumpers W1071 and W1072. # In an emergency this gives access to these driver inputs. NET 'LFBT_LVDS_DRV_1_IN' U1071-1 W1071-2 # Input to the #1 unused # LVDS Driver. NET 'GROUND' W1071-1 # Ground it. NET 'LFBT_LVDS_DRV_2_IN' U1071-7 W1072-2 # Input to the #2 unused # LVDS Driver. NET 'GROUND' W1072-1 # Ground it. # Connect terminator resistors across the output of the unused LVDS Drivers. # I'm not certain that these terminators are needed to guarantee the # operation of the 2 used sections but including these resistors gives # a place to make emergency connections. NET 'LFBT_LVDS_DRV_1_OUT_DIR' U1071-2 R1073-1 # Terminator accross un- NET 'LFBT_LVDS_DRV_1_OUT_CMP' U1071-3 R1073-2 # used LVDS Driver #1. NET 'LFBT_LVDS_DRV_2_OUT_DIR' U1071-6 R1074-2 # Terminator accross un- NET 'LFBT_LVDS_DRV_2_OUT_CMP' U1071-5 R1074-1 # used LVDS Driver #2.