#             This is a Key In  Net List  file for
#             the  ADF-2  for the Run IIB Cal Trig

#                   FPGA  Chip Specific  Nets
#               ---------------------------------


#                                                 Original Rev.   4-MAR-2004
#                                              Most Recent Rev. 29-SEPT-2004


#  This file contains the nets that are specific to a given FPGA.
#  It also includes some other nets and components that are not
#  appropriate for the fpga template files but are directly
#  associated with the FPGA circuits.

#  This nets file contains connections to components:
#
#    R803, R903  is  M0 mode resistor  0603  150 Ohm
#    R804, R904  is  M1 mode resistor  0603  150 Ohm
#    R805, R905  is  M2 mode resistor  0603  150 Ohm
#
#    R806, R906  is  HSWAP_EN  pull up  0603 4.99 k Ohm
#
#          R907  is  "F1" U901 ID Pin pull up  0603 4.99 k Ohm
#
#    W801    JTAG Data from BC PAL to F0      zero Ohm 0603 jumper
#    W802    JTAG Data from F0 to F1          zero Ohm 0603 jumper
#    W803    JTAG Data from F1 to off card    zero Ohm 0603 jumper



#  JTAG  Data Path
#  ---------------
#
#  Note the JTAG Scan Chain is:
#
#      P4 TDI  -->  Board_Control_PAL  -->  F0  -->  F1  -->  P4 TDO
#
#
#  The TDI signal received on the ADF-2 card goes first to the
#  Board Control PAL's TDI input.  The TDO signal from the BC PAL
#  connects,  via jumper W801,  to F0's TDI input.
#
#  The TDO signal from F0 connects,  via jumper W802,  to F1's TDI input.
#
#  The TDO signal from F1 connects,  via jumper W803,  to JTAG connector.


NET 'JTAG_TDO_BC_PAL'        W801-1     # TDO signal from the BC PAL  to W801.

NET 'JTAG_TDI_F0'  W801-2    U801-D3    # W801 sigal to FPGA F0 TDI pin.

NET 'JTAG_TDO_F0'  U801-D20  W802-1     # TDO signal from FPGA F0  to W802

NET 'JTAG_TDI_F1'  W802-2    U901-D3    # W802 sigal to FPGA F1 TDI pin.

NET 'JTAG_TDO_F1'  U901-D20  W803-1     # TDO signal from FPGA F1  to W803.

NET 'JTAG_TDO'     W803-2               # W803 signal to connector P4.




#  FPGA Configuration MODE Pins  -  Resistors R803, R804, R805
#                                         and R903, R904, R905
#
#  The Mode Select pins of the 2 FPGA's are handled separately.
#  FPGA Mode Select pins for U801 "F0" are handled through resistors
#  R803, R804, R805 which connect to the required default logic level.
#  The same setup is used for U901 "F1" through resistors R903, R904,
#  and R905.    Recall that this ADF-2 uses the  Slave SELECTMAP
#  Configuration mode.  Selecting this requires Mode Bits:  M0 to be LOW
#  and M1, M2 to be HIGH.


NET  'CNFG_F0_M0'   R803-1     # Pull resistor on the  M0  Mode Select
NET  'GROUND'       R803-2     # Resistor to GND.   M0 is LOW.

NET  'CNFG_F0_M1'   R804-1     # Pull resistor on the  M1  Mode Select
NET  'VDD_LOGIC'    R804-2     # Resistor to Vdd.   M1 is HIGH.

NET  'CNFG_F0_M2'   R805-1     # Pull resistor on the  M2  Mode Select
NET  'VDD_LOGIC'    R805-2     # Resistor to Vdd.   M2 is HIGH.


NET  'CNFG_F1_M0'   R903-1     # Pull resistor on the  M0  Mode Select
NET  'GROUND'       R903-2     # Resistor to GND.   M0 is LOW.

NET  'CNFG_F1_M1'   R904-1     # Pull resistor on the  M1  Mode Select
NET  'VDD_LOGIC'    R904-2     # Resistor to Vdd.   M1 is HIGH.

NET  'CNFG_F1_M2'   R905-1     # Pull resistor on the  M2  Mode Select
NET  'VDD_LOGIC'    R905-2     # Resistor to Vdd.   M2 is HIGH.




#  FPGA  HSWAP_EN  input signal  Pull Up  Resistor R806  and  R906
#
#  The HSWAP_EN input pin on each of the 2 FPGA's is pulled up.
#  F0 U801 is pulled up by R806  -  F1 U901 is pulled up by R906.
#  This just sets the default state for the FPGA HSWAP_EN input.


NET  'CNFG_F0_HSWAP_EN' R806-1     # Pull up resistor on the  HSWAP_EN
NET  'VDD_LOGIC'        R806-2     # Pull up resistor to Vdd.

NET  'CNFG_F1_HSWAP_EN' R906-1     # Pull up resistor on the  HSWAP_EN
NET  'VDD_LOGIC'        R906-2     # Pull up resistor to Vdd.




#  FPGA ID Pin connection  -  Resistor R807
#
#  Each of the two Data Path FPGAs has an ID Pin so that
#  the firmware can know which FPGA it is operating in.
#  The ID Pin on Data Path FPGA F0 is grounded.
#  the ID Pin on Data Path FPGA F1 is pulled up to Vdd_Logic.

NET 'GROUND'     U801-N20           # IO_L54N_3   Ground the ID Pin on FPGA F0

NET 'ID_PIN_F1'  U901-N20  R907-1   # Pull Up to VDD the
NET 'VDD_LOGIC'            R907-2   # ID Pin on FPGA F1





#  Local Parity Signal Connection between the Data Path FPGAs
#
#    F1 Local Parity Input is grounded.
#    F1 Local Parity Output is connected to F0 Local Parity Input.
#    F0 Local Parity Output is not connected.
#
#  The Local Parity Input pin  on each Data Path FPGA is in I/O Bank 3.
#  The Local Parity Output pin on each Data Path FPGA is in I/O Bank 6.
#  The Local Parity In/Out pins are assigned here in this net list
#  file and not in their I/O Bank net list file.

#  Ground Local Parity Input F1.

NET 'GROUND'   U901-P20   # F0 Local Parity Input

#  Connect  F1 Local Parity Output  to  F0 Local Parity Input.

NET 'LOC_PARITY_OUT_F1_TO_LOC_PARITY_IN_F0'  U901-P3  U801-P20  # Local Parity
                                                                # F1 to F0
#  No connection to LOC_PARITY_OUT_F0   U901-P3