#             This is a Key In  Net List  file for
#             the  ADF-2  for the Run IIB Cal Trig

#                    FPGA Bypass Capacitor Nets
#                ----------------------------------


#                                                 Original Rev. 25-MAR-2004
#                                              Most Recent Rev. 25-OCT-2004


#  This file is either the template file for the FPGA Bypass Capacitor nets
#  on the ADF-2 card  or  a net list file generated from that template
#  using the Multiple Instance Generator Tool.  Documentation about these
#  files and the Multiple Instance Generator Tool is on the web at:

#    www.pa.msu.edu/hep/d0/ftp/run2b/l1cal/hardware/adf_2/net_lists/
#                                      multiple_instance_generator_tool.txt


#  Modification on 25-OCT-2004.
#
#    Remove the 22 uFd Aluminum Electrolytics  C801, C901  from VDD_LOGIC.
#
#    Change the 4.7 uFd "A" case Tantalum  C802, C803, C902, C903
#    on VDD_LOGIC to a  10 uFd "B" case Tantalum.
#
#    Change the 22 uFd Aluminum Electrolytic  C833, C933  on VCCINT
#    to a 10 uFd "B" case Tantalum.
#
#    Change the 4.7 uFd "A" case Tantalum  C834, C934
#    on VCCINT to a  10 uFd "B" case Tantalum.
#
#    Overall change is that the small Aluminum Electrolytic caps are
#    gone from both  VDD_LOGIC and VCCINT    and    now both VDD_LOGIC
#    and VCCINT each have two 10 uFd "B" case Tantalum caps.



# Design of the FPGA Bypass Capacitors  (original design):
#
#   Bypass Capacitors on the VDD_LOGIC supply:
#
#   The VDD_LOGIC supply is used for:
#
#      VDD_LOGIC power for the I/O Banks which have a total of 40 Vcco pins
#      VDD_LOGIC power for the Auxiliary supply pins, total of  8 Vccaux pins
#
#   There is a total of 48 pins using the VDD_LOGIC supply:
#
#                                                              66% SSO
#                                               Full Usage    Pro-Rating
#                                             -------------   ----------
#             22 uFd Aluminum Electrolytic     3% x 48 =  1        1
#             4.7 uFd Tantalum   case A        6% x 48 =  3        2
#             0.47 uFd   Ceramic smd 0805     16% x 48 =  8        5
#             0.047 uFd  Ceramic smd 0603     25% x 48 = 12        8
#             0.0047 uFd Ceramic smd 0603     50% x 48 = 24       16
#
#
#   Bypass Capacitors on the VCCINT supply:
#
#   There is a total of 16 pins using the VCCINT supply:
#
#                                              Full Usage
#                                             ------------
#             22uFd Aluminum Electrolytic      3% x 16 = 1
#             4.7 uFd Tantalum   case A        6% x 16 = 1
#             0.47 uFd   Ceramic smd 0805     16% x 16 = 3
#             0.047 uFd  Ceramic smd 0603     25% x 16 = 4
#             0.0047 uFd Ceramic smd 0603     50% x 16 = 8
#
#
#   Total bypass capacitors per FPGA is:  49
#   32 capacitors on VDD_LOGIC  and  17 capacitors on VCCINT




#  FPGA Bypass Capacitor Nets on the VDD_LOGIC Supply


#    2x Tantalum Capacitors  10 uFd  "B" Case  on VDD_LOGIC
#    Capacitors  C 02  03

NET  'VDD_LOGIC'  C<key_802_100>-1    # Positive Terminal
NET  'GROUND'     C<key_802_100>-2    # Negative Terminal

NET  'VDD_LOGIC'  C<key_803_100>-1    # Positive Terminal
NET  'GROUND'     C<key_803_100>-2    # Negative Terminal



#    5x Ceramic Cap's  0.47 uFd  on VDD_LOGIC
#    Capacitors  C 04  05  06   07  08

NET  'VDD_LOGIC'  C<key_804_100>-1    C<key_805_100>-1    C<key_806_100>-1
NET  'GROUND'     C<key_804_100>-2    C<key_805_100>-2    C<key_806_100>-2

NET  'VDD_LOGIC'  C<key_807_100>-1    C<key_808_100>-1
NET  'GROUND'     C<key_807_100>-2    C<key_808_100>-2



#    8x Ceramic Cap's  0.047 uFd  on VDD_LOGIC
#    Capacitors  C 09  10  11    12  13  14    15  16

NET  'VDD_LOGIC'  C<key_809_100>-1    C<key_810_100>-1    C<key_811_100>-1
NET  'GROUND'     C<key_809_100>-2    C<key_810_100>-2    C<key_811_100>-2

NET  'VDD_LOGIC'  C<key_812_100>-1    C<key_813_100>-1    C<key_814_100>-1
NET  'GROUND'     C<key_812_100>-2    C<key_813_100>-2    C<key_814_100>-2

NET  'VDD_LOGIC'  C<key_815_100>-1    C<key_816_100>-1
NET  'GROUND'     C<key_815_100>-2    C<key_816_100>-2



#    16x Ceramic Cap's  0.0047 uFd  on VDD_LOGIC
#    Capacitors  C 17  18  19    20  21  22    23  24  25
#    Capacitors  C 26  27  28    29  30  31    32

NET  'VDD_LOGIC'  C<key_817_100>-1    C<key_818_100>-1    C<key_819_100>-1
NET  'GROUND'     C<key_817_100>-2    C<key_818_100>-2    C<key_819_100>-2

NET  'VDD_LOGIC'  C<key_820_100>-1    C<key_821_100>-1    C<key_822_100>-1
NET  'GROUND'     C<key_820_100>-2    C<key_821_100>-2    C<key_822_100>-2

NET  'VDD_LOGIC'  C<key_823_100>-1    C<key_824_100>-1    C<key_825_100>-1
NET  'GROUND'     C<key_823_100>-2    C<key_824_100>-2    C<key_825_100>-2

NET  'VDD_LOGIC'  C<key_826_100>-1    C<key_827_100>-1    C<key_828_100>-1
NET  'GROUND'     C<key_826_100>-2    C<key_827_100>-2    C<key_828_100>-2

NET  'VDD_LOGIC'  C<key_829_100>-1    C<key_830_100>-1    C<key_831_100>-1
NET  'GROUND'     C<key_829_100>-2    C<key_830_100>-2    C<key_831_100>-2

NET  'VDD_LOGIC'  C<key_832_100>-1
NET  'GROUND'     C<key_832_100>-2




#  FPGA Bypass Capacitor Nets on the VCCINT Supply


#    2x Tantalum Capacitors  10 uFd  "B" Case  on VCCINT
#    Capacitors  C 33  34

NET  'VCCINT'     C<key_833_100>-1    # Positive Terminal
NET  'GROUND'     C<key_833_100>-2    # Negative Terminal

NET  'VCCINT'     C<key_834_100>-1    # Positive Terminal
NET  'GROUND'     C<key_834_100>-2    # Negative Terminal



#    3x Ceramic Cap's  0.47 uFd  on VCCINT
#    Capacitors  C 35  36  37

NET  'VCCINT'     C<key_835_100>-1    C<key_836_100>-1    C<key_837_100>-1
NET  'GROUND'     C<key_835_100>-2    C<key_836_100>-2    C<key_837_100>-2



#    4x Ceramic Cap's  0.047 uFd  on VCCINT
#    Capacitors  C 38  39  40   41

NET  'VCCINT'     C<key_838_100>-1    C<key_839_100>-1    C<key_840_100>-1
NET  'GROUND'     C<key_838_100>-2    C<key_839_100>-2    C<key_840_100>-2

NET  'VCCINT'     C<key_841_100>-1
NET  'GROUND'     C<key_841_100>-2



#    8x Ceramic Cap's  0.0047 uFd  on VCCINT
#    Capacitors  C 42  43  44    45  46  47    48  49

NET  'VCCINT'     C<key_842_100>-1    C<key_843_100>-1    C<key_844_100>-1
NET  'GROUND'     C<key_842_100>-2    C<key_843_100>-2    C<key_844_100>-2

NET  'VCCINT'     C<key_845_100>-1    C<key_846_100>-1    C<key_847_100>-1
NET  'GROUND'     C<key_845_100>-2    C<key_846_100>-2    C<key_847_100>-2

NET  'VCCINT'     C<key_848_100>-1    C<key_849_100>-1
NET  'GROUND'     C<key_848_100>-2    C<key_849_100>-2