#
#             This is a Key In  Net List  file for
#             the  ADF-2  for the Run IIB Cal Trig

#                    FPGA  I/O Bank  3  Nets
#                -------------------===---------


#                                                 Original Rev.  27-FEB-2004
#                                              Most Recent Rev.  7-SEPT-2004


#  This file is either the template file for the FPGA  I/O Bank  nets
#  on the ADF-2 card  or  a net list file generated from that template
#  using the Multiple Instance Generator Tool.  Documentation about these
#  files and the Multiple Instance Generator Tool is on the web at:

#    www.pa.msu.edu/hep/d0/ftp/run2b/l1cal/hardware/adf_2/net_lists/
#                                      multiple_instance_generator_tool.txt



#  This net list contains connections to the following components:
#
#     U801  (U901)  FPGA
#
#     N801, N802   (N901, N902)    100 Ohm   8 pin   4 resistor array




#  FPGA  I/O Bank 3  Nets.    Bank 3 has 42 User I/O Pins.


#  ADC Clock Signals that come from the Data Path FPGA
#
#  Bank 3 on the upper lefthand side of the FPGA drives the
#  ADC Clock signals to channels 4:7 (12:15) EM and HD.


NET  'DRV_CH_<key_4_8>_EM_ADC_CLK'  U<key_801_100>-N22     # IO_L91N_3
NET  'DRV_CH_<key_4_8>_HD_ADC_CLK'  U<key_801_100>-P22     # IO_L51N_3/VREF_3


NET  'DRV_CH_<key_5_8>_EM_ADC_CLK'  U<key_801_100>-R22     # IO_L48N_3
NET  'DRV_CH_<key_5_8>_HD_ADC_CLK'  U<key_801_100>-T22     # IO_L43N_3


NET  'DRV_CH_<key_6_8>_EM_ADC_CLK'  U<key_801_100>-U22     # IO_L22N_3
NET  'DRV_CH_<key_6_8>_HD_ADC_CLK'  U<key_801_100>-V22     # IO_L06N_3


NET  'DRV_CH_<key_7_8>_EM_ADC_CLK'  U<key_801_100>-W22     # IO_L03N_3/VREF_3
NET  'DRV_CH_<key_7_8>_HD_ADC_CLK'  U<key_801_100>-Y22     # IO_L02N_3/VRP_3


#  Series Terminator Resistors in the ADC Clock Lines.

NET 'DRV_CH_<key_4_8>_EM_ADC_CLK'  N<key_802_100>-5   # Clock signal from FPGA
NET     'CH_<key_4_8>_EM_ADC_CLK'  N<key_802_100>-4   # Clock signal to ADC

NET 'DRV_CH_<key_4_8>_HD_ADC_CLK'  N<key_802_100>-6   # Clock signal from FPGA
NET     'CH_<key_4_8>_HD_ADC_CLK'  N<key_802_100>-3   # Clock signal to ADC

NET 'DRV_CH_<key_5_8>_EM_ADC_CLK'  N<key_802_100>-7   # Clock signal from FPGA
NET     'CH_<key_5_8>_EM_ADC_CLK'  N<key_802_100>-2   # Clock signal to ADC

NET 'DRV_CH_<key_5_8>_HD_ADC_CLK'  N<key_802_100>-8   # Clock signal from FPGA
NET     'CH_<key_5_8>_HD_ADC_CLK'  N<key_802_100>-1   # Clock signal to ADC


NET 'DRV_CH_<key_6_8>_EM_ADC_CLK'  N<key_801_100>-5   # Clock signal from FPGA
NET     'CH_<key_6_8>_EM_ADC_CLK'  N<key_801_100>-4   # Clock signal to ADC

NET 'DRV_CH_<key_6_8>_HD_ADC_CLK'  N<key_801_100>-6   # Clock signal from FPGA
NET     'CH_<key_6_8>_HD_ADC_CLK'  N<key_801_100>-3   # Clock signal to ADC

NET 'DRV_CH_<key_7_8>_EM_ADC_CLK'  N<key_801_100>-7   # Clock signal from FPGA
NET     'CH_<key_7_8>_EM_ADC_CLK'  N<key_801_100>-2   # Clock signal to ADC

NET 'DRV_CH_<key_7_8>_HD_ADC_CLK'  N<key_801_100>-8   # Clock signal from FPGA
NET     'CH_<key_7_8>_HD_ADC_CLK'  N<key_801_100>-1   # Clock signal to ADC




#  Now include the nets that operate the serial Channel Link chips

NET 'SER_CH_<key_4_8>_EM'   U<key_801_100>-W21   # EM Chan #4 Et Serial Output
NET 'SER_CH_<key_4_8>_HD'   U<key_801_100>-V21   # HD Chan #4 Et Serial Output

NET 'SER_CH_<key_5_8>_EM'   U<key_801_100>-U21   # EM Chan #5 Et Serial Output
NET 'SER_CH_<key_5_8>_HD'   U<key_801_100>-T21   # HD Chan #5 Et Serial Output

NET 'SER_CH_<key_6_8>_EM'   U<key_801_100>-R21   # EM Chan #6 Et Serial Output
NET 'SER_CH_<key_6_8>_HD'   U<key_801_100>-P21   # HD Chan #6 Et Serial Output

NET 'SER_CH_<key_7_8>_EM'   U<key_801_100>-N21   # EM Chan #7 Et Serial Output
NET 'SER_CH_<key_7_8>_HD'   U<key_801_100>-M21   # HD Chan #7 Et Serial Output

NET 'SER_RSVD_F<key_0_1>(0)'  U<key_801_100>-V20   # Rsrvd Serial F<key_0_1>(0)
NET 'SER_RSVD_F<key_0_1>(1)'  U<key_801_100>-T20   # Rsrvd Serial F<key_0_1>(1)
NET 'SER_RSVD_F<key_0_1>(2)'  U<key_801_100>-R20   # Rsrvd Serial F<key_0_1>(2)
NET 'SER_RSVD_F<key_0_1>(3)'  U<key_801_100>-W20   # Rsrvd Serial F<key_0_1>(3)

#  The Local Parity Input pin is in I/O Bank 3 but it is not
#  assigned in this net list file.  It is assigned in the FPGA
#  Specific Chip net list file.
##
##NET 'LOC_PARITY_IN_F<key_0_1>'  U<key_801_100>-P20   # Local Parity Input
##



#  Now include the FPGA ID Pin
#
#  The FPGA ID Pin is in I/O Bank 3 but it is not
#  assigned in this net list file.  It is assigned
#  in the FPGA Specific Chip net list file.
##
##NET  'FPGA_ID_F<key_0_1>'  U<key_801_100>-N20     # IO_L54N_3
##



#  Access connections via Access Connector P5
#  to I/O Bank 3 of the Data Path FPGAs

NET  'F<key_0_1>_ACCESS_14'   U<key_801_100>-R18     # IO_L45N_3/VREF_3
NET  'F<key_0_1>_ACCESS_15'   U<key_801_100>-P17     # IO_L45P_3
NET  'F<key_0_1>_ACCESS_12'   U<key_801_100>-U20     # IO_L21N_3/VREF_3
NET  'F<key_0_1>_ACCESS_13'   U<key_801_100>-U19     # IO_L21P_3





#  Remaining  (not currently assigned)  FPGA  I/O Bank 3  Nets

#NET  ''  U<key_801_100>-M20     # IO_L96P_3
#NET  ''  U<key_801_100>-M19     # IO_L94N_3
#NET  ''  U<key_801_100>-M18     # IO_L94P_3
#NET  ''  U<key_801_100>-M17     # IO_L93N_3/VREF_3
#NET  ''  U<key_801_100>-N19     # IO_L54P_3

#NET  ''  U<key_801_100>-N18     # IO_L52N_3
#NET  ''  U<key_801_100>-N17     # IO_L93P_3
#NET  ''  U<key_801_100>-P18     # IO_L52P_3
#NET  ''  U<key_801_100>-P19     # IO_L49P_3
#NET  ''  U<key_801_100>-R19     # IO_L46P_3

#NET  ''  U<key_801_100>-T19     # IO_L24P_3
#NET  ''  U<key_801_100>-T18     # IO_L19N_3
#NET  ''  U<key_801_100>-U18     # IO_L19P_3
#NET  ''  U<key_801_100>-V19     # IO_L04P_3
#NET  ''  U<key_801_100>-Y21     # IO_L02P_3/VRN_3

#NET  ''  U<key_801_100>-AA20    # IO_L01P_3