#             This is a Key In  Net List  file for
#             the  ADF-2  for the Run IIB Cal Trig

#                    FPGA  I/O Bank 4  Nets
#                ------------------===---------


#                                                 Original Rev.   1-MAR-2004
#                                              Most Recent Rev. 29-SEPT-2004


#  This file is either the template file for the FPGA  I/O Bank  nets
#  on the ADF-2 card  or  a net list file generated from that template
#  using the Multiple Instance Generator Tool.  Documentation about these
#  files and the Multiple Instance Generator Tool is on the web at:

#    www.pa.msu.edu/hep/d0/ftp/run2b/l1cal/hardware/adf_2/net_lists/
#                                      multiple_instance_generator_tool.txt


#  FPGA  I/O Bank 4  Nets      I/O Bank 4 has 40 User I/O Pins.

#  This net list includes the pull up Resistors R801 and R901.


#  FPGA Pins with a special function during Configuration


#  Configuration BUSY
#  During Configuration pin AB19 is the  BUSY  signal which is used to
#  indicate when the FPGA can accept the next byte of Configuration Data.
#  When BUSY is asserted HI it means that the FPGA is not ready to accept
#  another byte of Configuration Data.  BUSY is not an open drain signal.
#  After Configuration this pin is available for User I/O. 

NET  'CNFG_BUSY(<key_0_1>)'  U<key_801_100>-AB19   # IO_L01N_4/BUSY/DOUT



#  Configuration INIT_B
#  During Configuration pin AA19 is the open drain  INIT_B  signal which is
#  used to indicate when the FPGA's Configuration Memory is being cleared.
#  Once Configuration has started this pin remains  LOW  until the
#  Configuration Memory has been cleared and then the FPGA's Configuration
#  logic releases this open drain output signal.   After Configuration this
#  pin is available for User I/O.   On the ADF-2 card this pin from each
#  FPGA is connected to a separate input pin on the Board Control PAL.
#  The pull up resistors for these open drain signals are included
#  in the following nets.

NET  'CNFG_INIT_B(<key_0_1>)'  U<key_801_100>-AA19   # IO_L01P_4/INIT_B

NET  'CNFG_INIT_B(<key_0_1>)'  R<key_801_100>-1      # Pull up resistor on
                                                     # the INIT_B  signal
                                                     # from the FPGA
NET  'VDD_LOGIC'               R<key_801_100>-2      # Pull up resistor to Vdd



#  Configuration DATA D0,D1,D2,D3
#  During Configuration the following 4 pins are used for the lower
#  4 bits of Configuration Data.  The lower 4 bits of Configuration
#  Data is delivered to the FPGA on the low 4 bits of the 16 bit
#  On Card Data Bus.  After Configuration these pins are available for
#  User I/O and they are used as the low 4 bits of the On Card Data Bus.

NET  'OCB_DATA(0)'  U<key_801_100>-V18    # IO_L02N_4/D0/DIN
NET  'OCB_DATA(1)'  U<key_801_100>-V17    # IO_L02P_4/D1
NET  'OCB_DATA(2)'  U<key_801_100>-W18    # IO_L03N_4/D2/ALT_VRP_4
NET  'OCB_DATA(3)'  U<key_801_100>-Y18    # IO_L03P_4/D3/ALT_VRN_4


#  This completes the pins in Bank 4 that have a special
#  function during Configuration



#  Connect 4 more lines of the On Card Data Bus  i.e. bits 8:11

NET  'OCB_DATA(8)'   U<key_801_100>-V15    # IO_L19P_4
NET  'OCB_DATA(9)'   U<key_801_100>-U14    # IO_L51N_4
NET  'OCB_DATA(10)'  U<key_801_100>-U13    # IO_L91N_4/VREF_4
NET  'OCB_DATA(11)'  U<key_801_100>-U12    # IO_L94N_4/VREF_4


#  Connect 4 of the  On Card Address Bus lines  i.e. 5:8

NET  'OCB_ADRS(5)'  U<key_801_100>-V12    # IO_L94P_4
NET  'OCB_ADRS(6)'  U<key_801_100>-V13    # IO_L91P_4
NET  'OCB_ADRS(7)'  U<key_801_100>-V14    # IO_L51P_4/VREF_4
NET  'OCB_ADRS(8)'  U<key_801_100>-V16    # IO_L19N_4


#  Connect 3 more of the  On Card Address Bus lines  i.e. 14:16

NET  'OCB_ADRS(14)'  U<key_801_100>-W13    # IO_L92N_4
NET  'OCB_ADRS(15)'  U<key_801_100>-W14    # IO_L52N_4
NET  'OCB_ADRS(16)'  U<key_801_100>-W15    # IO_L24N_4



#  Connect 2 of the  On Card Bus Control Lines  i.e. Direction & Chip_SEL_B

NET  'OCB_DIRECTION'               U<key_801_100>-W16    # IO_L21N_4
NET  'OCB_CHIP_SEL_B(<key_0_1>)'   U<key_801_100>-W17    # IO_L05N_4/VRP_4 




#  Connect the FIRST_X8_EDGE_F0/1 signal

NET  'FIRST_X8_EDGE_F<key_0_1>'  U<key_801_100>-AB12   # IO_L96P_4/GCLK0P




#  Connect the FPGA_0/1_STATUS(3:0) signals that run to the Brd Cntrl PAL

NET  'FPGA_<key_0_1>_STATUS(3)'  U<key_801_100>-AB15   # IO_L49P_4
NET  'FPGA_<key_0_1>_STATUS(2)'  U<key_801_100>-AB16   # IO_L22P_4
NET  'FPGA_<key_0_1>_STATUS(1)'  U<key_801_100>-AB17   # IO_L06P_4
NET  'FPGA_<key_0_1>_STATUS(0)'  U<key_801_100>-AB18   # IO_L04P_4




#  Access connections via Access Connector P5
#  to I/O Bank 4 of the Data Path FPGAs

NET  'F<key_0_1>_ACCESS_8'    U<key_801_100>-W12    # IO_L95N_4/GCLK3S
NET  'F<key_0_1>_ACCESS_9'    U<key_801_100>-Y12    # IO_L95P_4/GCLK2P
NET  'F<key_0_1>_ACCESS_10'   U<key_801_100>-AA14   # IO_L54N_4
NET  'F<key_0_1>_ACCESS_11'   U<key_801_100>-AB14   # IO_L54P_4




#  Connect two of the LEDs to pins in I/O Bank 4.

NET  'F<key_0_1>_LED_2'    U<key_801_100>-AA16   # IO_L22N_4
NET  'F<key_0_1>_LED_3'    U<key_801_100>-AA17   # IO_L06N_4





#  Remaining  (not currently assigned)  FPGA  I/O Bank 4  Nets

# NET  ''  U<key_801_100>-Y13    # IO_L92P_4
# NET  ''  U<key_801_100>-Y14    # IO_L52P_4
# NET  ''  U<key_801_100>-Y15    # IO_L24P_4
# NET  ''  U<key_801_100>-Y16    # IO_L21P_4/VREF_4
# NET  ''  U<key_801_100>-Y17    # IO_L05P_4/VRN_4 

# NET  ''  U<key_801_100>-AA12   # IO_L96N_4/GCLK1S
# NET  ''  U<key_801_100>-AA13   # IO_L93N_4
# NET  ''  U<key_801_100>-AA15   # IO_L49N_4
# NET  ''  U<key_801_100>-AA18   # IO_L04N_4/VREF_4
# NET  ''  U<key_801_100>-AB13   # IO_L93P_4