# # This is a Key In Net List file for # the ADF-2 for the Run IIB Cal Trig # FPGA I/O Bank 6 Nets # -------------------===--------- # Original Rev. 1-MAR-2004 # Most Recent Rev. 7-SEPT-2004 # This file is either the template file for the FPGA I/O Bank nets # on the ADF-2 card or a net list file generated from that template # using the Multiple Instance Generator Tool. Documentation about these # files and the Multiple Instance Generator Tool is on the web at: # www.pa.msu.edu/hep/d0/ftp/run2b/l1cal/hardware/adf_2/net_lists/ # multiple_instance_generator_tool.txt # This net list contains connections to the following components: # # U801 (U901) FPGA # # N803, N804 (N903, N904) 100 Ohm 8 pin 4 resistor array # FPGA I/O Bank 6 Nets. Bank 6 has 42 User I/O Pins. # ADC Clock Signals that come from the Data Path FPGA # # Bank 6 on the upper righthand side of the FPGA drives the # ADC Clock signals to channels 0:3 (8:11) EM and HD. NET 'DRV_CH__EM_ADC_CLK' U-W1 # IO_L04N_6 NET 'DRV_CH__HD_ADC_CLK' U-V1 # IO_L19N_6 NET 'DRV_CH__EM_ADC_CLK' U-U1 # IO_L21N_6/VREF_6 NET 'DRV_CH__HD_ADC_CLK' U-T1 # IO_L43N_6 NET 'DRV_CH__EM_ADC_CLK' U-R1 # IO_L46N_6 NET 'DRV_CH__HD_ADC_CLK' U-P1 # IO_L51N_6/VREF_6 NET 'DRV_CH__EM_ADC_CLK' U-N1 # IO_L91N_6 NET 'DRV_CH__HD_ADC_CLK' U-M1 # IO_L96N_6 # Series Terminator Resistors in the ADC Clock Lines. NET 'DRV_CH__EM_ADC_CLK' N-5 # Clock signal from FPGA NET 'CH__EM_ADC_CLK' N-4 # Clock signal to ADC NET 'DRV_CH__HD_ADC_CLK' N-6 # Clock signal from FPGA NET 'CH__HD_ADC_CLK' N-3 # Clock signal to ADC NET 'DRV_CH__EM_ADC_CLK' N-7 # Clock signal from FPGA NET 'CH__EM_ADC_CLK' N-2 # Clock signal to ADC NET 'DRV_CH__HD_ADC_CLK' N-8 # Clock signal from FPGA NET 'CH__HD_ADC_CLK' N-1 # Clock signal to ADC NET 'DRV_CH__EM_ADC_CLK' N-5 # Clock signal from FPGA NET 'CH__EM_ADC_CLK' N-4 # Clock signal to ADC NET 'DRV_CH__HD_ADC_CLK' N-6 # Clock signal from FPGA NET 'CH__HD_ADC_CLK' N-3 # Clock signal to ADC NET 'DRV_CH__EM_ADC_CLK' N-7 # Clock signal from FPGA NET 'CH__EM_ADC_CLK' N-2 # Clock signal to ADC NET 'DRV_CH__HD_ADC_CLK' N-8 # Clock signal from FPGA NET 'CH__HD_ADC_CLK' N-1 # Clock signal to ADC # Now include the nets that operate the serial Channel Link chips NET 'SER_CH__EM' U-M2 # EM Chan #0 Et Serial Output NET 'SER_CH__HD' U-N2 # HD Chan #0 Et Serial Output NET 'SER_CH__EM' U-P2 # EM Chan #1 Et Serial Output NET 'SER_CH__HD' U-R2 # HD Chan #1 Et Serial Output NET 'SER_CH__EM' U-T2 # EM Chan #2 Et Serial Output NET 'SER_CH__HD' U-U2 # HD Chan #2 Et Serial Output NET 'SER_CH__EM' U-V2 # EM Chan #3 Et Serial Output NET 'SER_CH__HD' U-W2 # HD Chan #3 Et Serial Output NET 'SER_FRAME_F' U-U3 # Serial Frame F NET 'SER_BX_COUNT_F' U-T3 # Serial BX Count F NET 'SER_PARITY_F' U-V3 # Serial Parity F # The Local Parity Output pin is in I/O Bank 6 but it is not # assigned in this net list file. It is assigned in the FPGA # Specific Chip net list file. ## ##NET 'LOC_PARITY_OUT_F' U-P3 # Local Parity Output ## # Access connections via Access Connector P5 # to I/O Bank 6 of the Data Path FPGAs NET 'F_ACCESS_2' U-R4 # IO_L45P_6 NET 'F_ACCESS_3' U-R3 # IO_L45N_6/VREF_6 NET 'F_ACCESS_0' U-N4 # IO_L54P_6 NET 'F_ACCESS_1' U-N3 # IO_L54N_6 # Remaining (not currently assigned) FPGA I/O Bank 6 Nets #NET '' U-V5 # IO_L01P_6 #NET '' U-U5 # IO_L01N_6 #NET '' U-Y2 # IO_L02P_6/VRN_6 #NET '' U-Y1 # IO_L02N_6/VRP_6 #NET '' U-V4 # IO_L03P_6 #NET '' U-U4 # IO_L06P_6 #NET '' U-T5 # IO_L22P_6 #NET '' U-R5 # IO_L22N_6 #NET '' U-T4 # IO_L24P_6 #NET '' U-P6 # IO_L48P_6 #NET '' U-P5 # IO_L48N_6 #NET '' U-P4 # IO_L49P_6 #NET '' U-N6 # IO_L52P_6 #NET '' U-N5 # IO_L52N_6 #NET '' U-M6 # IO_L93P_6 #NET '' U-M5 # IO_L93N_6/VREF_6 #NET '' U-M4 # IO_L94P_6 #NET '' U-M3 # IO_L94N_6