#             This is a Key In  Net List  file for
#             the  ADF-2  for the Run IIB Cal Trig

#                    FPGA  Non I/O Bank  Nets
#                --------------------------------


#                                                 Original Rev.   4-MAR-2004
#                                              Most Recent Rev. 29-SEPT-2004


#  This file is either the template file for the FPGA  Non I/O Bank  nets
#  on the ADF-2 card  or  a net list file generated from that template
#  using the Multiple Instance Generator Tool.  Documentation about these
#  files and the Multiple Instance Generator Tool is on the web at:

#    www.pa.msu.edu/hep/d0/ftp/run2b/l1cal/hardware/adf_2/net_lists/
#                                      multiple_instance_generator_tool.txt


#  FPGA  Non I/O Bank  Nets

#  This file contains reference to components:
#
#     R802, R902  the FPGA Configuration   DONE   signal pull up resistors



#  Dedicated Configuration pins

#  Note that the ADF card uses Slave SelectMAP Configuration.


#  Configuration_Clock
#  The Configuration Clock comes from the Board Control PAL.
#  It is connected to both FPGA's in parallel.

NET  'CNFG_CCLK'  U<key_801_100>-Y19    # CCLK  to FPGA's



#  PROG_B
#  The PROG_B signal is the active low asynchronous signal that tells
#  the FPGA to begin the configuration process.  There is a separate
#  PROG_B signal for each of the FPGA's.  These signals come from the
#  Board Control PAL.

NET  'CNFG_PROG_B(<key_0_1>)'  U<key_801_100>-A2     # PROG_B  to FPGA's



#  DONE
#  The active High open drain DONE signal from each of the FPGA's
#  is routed to individual input pins on the Board Control PAL.
#  The pull up resistors for the DONE signals are: R801, R901.

NET 'CNFG_DONE(<key_0_1>)'  U<key_801_100>-AB20   # DONE  from FPGA

NET 'CNFG_DONE(<key_0_1>)'  R<key_802_100>-1      # Pull up resistor on
                                                  # the  FPGA  DONE  signal.

NET 'VDD_LOGIC'             R<key_802_100>-2      # Pull up resistor to Vdd.



#  Configuration MODE pins
#  Set the Configuration Mode pins for  Slave SelectMAP Mode.
#  In case a change is needed the control signals to these pins
#  comes from resistors,  i.e. these pins are not tied directly
#  to the Gnd and Vdd planes right under the FPGA's where you can
#  not get at them.   These resistors  R803, R804, R805  and  R903
#  R904, R905  are in the fpga_specific_chip nets file.

NET  'CNFG_F<key_0_1>_M0'  U<key_801_100>-AB2    # M0  input to FPGA's
NET  'CNFG_F<key_0_1>_M1'  U<key_801_100>-W3     # M1  input to FPGA's
NET  'CNFG_F<key_0_1>_M2'  U<key_801_100>-AB3    # M2  input to FPGA's



#  Configuration HSWAP_EN
#  The HSWAP_EN pin is a dedicated input pin that controls the
#  pull up resistors on the User I/O pins during Configuration.
#  If HSWAP_EN is HI then during Configuration the User I/O pull
#  up resistors are turned OFF.  By default HSWAP_EN is pulled HI
#  by an internal pull up.  On ADF-2 card it is also pulled HI by
#  and external resistor R806 which is included in the
#  fpga_specific_chip nets file.

NET  'CNFG_F<key_0_1>_HSWAP_EN'  U<key_801_100>-B3     # HSWAP_EN  input



# This ends the nets that are associated with the
# Dedicated Configuration pins.

#  Note that there are additional pins and nets involved in
#  Configuration of the FPGA's.   These are:
#
#     D0:D7      in the nets file for I/O Banks 4 and 5
#     CS_B       in the nets file for I/O Bank 5
#     RDWR_B     in the nets file for I/O Bank 5
#     BUSY       in the nets file for I/O Bank 4
#     INIT_B     in the nets file for I/O Bank 4






#  JTAG nets to the FPGA's

#  The JTAG  TCK and TMS nets run from the JTAG connector
#  to both FPGA's and to the Board Control PAL.

NET  'JTAG_TCK'  U<key_801_100>-C19    # TCK  signal to the BC PAL and FPGAs
NET  'JTAG_TMS'  U<key_801_100>-B20    # TMS  signal to the BC PAL and FPGAs

#  The TDI and TDO nets for the 2 FPGA's are shown in the
#  fpga_per_chip_nets file.





#  The following 2 pins are the temperature monitor diode pins.
#  "P" is the anode  "N" is the Cathode.  ADF does not use this
#  monitor diode.

###  Make No Connection to this Pin  NET  ''  U<key_801_100>-D5     # DXN
###  Make No Connection to this Pin  NET  ''  U<key_801_100>-A3     # DXP



#  The  PWRDWN_B  and  VBATT  pins are covered in the
#  FPGA Power Supply Nets File.


###  Make No Connection to this Pin  NET  ''  U<key_801_100>-A20    # RSVD