#             This is a Key In  Net List  file for
#             the  ADF-2  for the Run IIB Cal Trig

#                   Power Up Supervisor Nets
#               --------------------------------


#                                                 Original Rev.   8-APR-2004
#                                              Most Recent Rev. 10-JUNE-2004


#  This file contains the nets that are the Power Up Supervisor Circuit
#  on the ADF-2 card.  The details about the operation of this circuit
#  are described in text on the drawing:

#  www.pa.msu.edu/hep/d0/ftp/run2b/l1cal/hardware/adf_2/drawings/
#                                      adf_2_power_up_supervisor.pdf  or  .ps


#  This key in nets file contains components:

#    U1031           74AS756  one section for receiving RESIN from backplane
#    U1351           TI  TLC 7705 IPWR  supervisor IC
#    C1351           0.1 uFd ceramic   Vcc_Logic bypass
#    C1352, C1353    10 uFd Tant "B" case  Cap_Time and Sense Filter
#    R1351           20k Ohm
#    R1352           2.15k Ohm



#  Begin the Power Up Supervisor Net List.


#  TLC 7705  Control Input Pin.

NET 'GROUND'     U1351-1              # TLC 7705  Control Input



#  Bring the RESIN signal onto the card and invert it to make the RESIN*
#  signal that goes to the TLC-7705 supervisor.  RESIN is carried
#  from one slot to the next on the  Bus_Grant_1_B  backplane circuit.
#  The inverter is powered from VCC_LOGIC supply (as it would need to be).

NET 'VME_BUS_GRANT_1_IN_B'  U1031-17  # RESIN signal from the backplane
                                      # to the inverter input.

NET 'TLC_RESIN_B'  U1031-3  U1351-2   # RESIN* from the inverter output to
                                      # the supervisor input.

NET 'TLC_RESIN_B'  R1352-1            # Pull up resistor on the open collector
                                      # inverter that drives TLC_RESIN_B.
NET 'VCC_LOGIC'    R1352-2            # Pull up to VCC_LOGIC  +5 Volts.



#  Delay Period Timing Capacitor nets.

NET 'TLC_CAP_TIME'  U1351-3  C1352-1   # Timing Capacitor connection TLC 7705

NET 'GROUND'                 C1352-2   # Ground the other end of Timing Cap



#  TLC 7705  Ground Pin.   This is the Ground to the TLC 7705.

NET 'GROUND'     U1351-4              # TLC 7705  Ground pin



#  TLC 7705  RESET* output pin.  This pin goes HIGH at the end of the
#  delay period when it is time that the DC/DC Converters should start up.

NET 'DC_DC_CONVERTER_ENABLE'   U1351-5    # TLC 7705  RESET* Output



#  TLC 7705  RESET output pin.  This pin goes LOW when it is time to
#  tell the next card to begin its delay time period.  This signal is
#  carried to the next card slot on the  Bus_Grant_1_B  backplane circuit.

NET 'VME_BUS_GRANT_1_OUT_B'    U1351-6    # TLC 7705  RESET Output



#  TLC 7705  SENSE Input Pin.   This is the input via which the TLC 7705
#  monitors the VCC_LOGIC supply voltage.  This +5V supply voltage
#  is filtered before it is connected to this SENSE input.  The TLC 7705
#  will not begin its delay time period until this SENSE input is stable
#  and above 4.55 Volts.


NET 'TLC_SENSE'  U1351-7   R1351-1   C1353-1   # TLC 7705 SENSE input and
                                               # filter capacitor and resistor

NET 'VCC_LOGIC'  R1351-2      # VCC_LOGIC supply to the filter resistor

NET 'GROUND'     C1353-2      # Ground the other end of the filter capacitor



#  TLC 7705  VDD Pin.   This is the +5 Volt supply to the TLC 7705
#  and its bypass capacitor.

NET 'VCC_LOGIC'  U1351-8   C1351-1   # VCC_LOGIC supply to the TLC 7705

NET 'GROUND'               C1351-2   # Ground the other end of the bypass cap