#             This is a Key In  Net List  file for
#             the  ADF-2  for the Run IIB Cal Trig

#          Receive Backplane Timing and Control  Nets
#        ----------------------------------------------

#
#                                                 Original Rev.  25-MAY-2004
#                                              Most Recent Rev. 10-SEPT-2004


#  This file includes all the nets that receive the timing and
#  control signals from the ADF-2 Crate Backplane and then distribute
#  these signals on the ADF-2 card.

#  Connection of the nets to the VME-64X Reserved Bused
#  backplane lines is taken care of in the P1 net list file.


#  This file contains the nets for the following components:
#
#     U1041           SN74LVC540A     Octal Inverting OC Buffer Receiver
#
#     U1052           SN65LVDS32      Quad LVDS Receiver
#
#     C1041           0.1 uFd bypass capacitors to Vdd_Logic
#
#     C1042           4.7 nFd bypass capacitors to Vdd_Logic
#
#     C1061           0.1 uFd ceramic   help hold the backplane BX_Clk
#     C1062           4.7 nfd ceramic   common mode at AC Ground
#
#     W1041, W1042    Zero Ohm 0603 jumpers control input to 2 unused
#                                                   sections of U1041
#
#     R1061, R1062    1k Ohm  0603   isolator - divider between open collector
#     R1063, R1064    499 Ohm 0603   backplane and LVDS receiver input
#     R1065           100 Ohm 0603   series terminator for RCVD_BX_CLK


#  Most of the U1052 LVDS Receiver is covered in the file:
#
#      receive_scld_drive_backplane_nets.txt
#
#  One section of the U1041 is used to connect the VME DS1* signal to
#  the Board Control PAL.  Those nets are covered in the file:
#
#      vme_to_board_control_pal_nets.txt



#  Start with the SCL Beginning of Turn Marker signal.

NET 'BKPLN_BEGIN_TURN_B'    U1041-8    # VME-64X Reserved Bus signal 0
                                       # SCL Begin Turn Marker  from Backplane

NET 'RCVD_BEGIN_TURN'       U1041-12   # This is the Received Beginning
                                       # of Turn Marker



#  SCL Live Beam Crossing Marker signal.

NET 'BKPLN_LIVE_BX_B'       U1041-7    # VME-64X Reserved Bus signal 1
                                       # SCL Live BX Marker  from Backplane

NET 'RCVD_LIVE_BX'          U1041-13   # This is the Received Live BX Marker



#  SCL Save Monitoring Data signal.

NET 'BKPLN_SAVE_MONIT_DATA_B'  U1041-6   # VME-64X Reserved Bus signal 2
                                         # Save Monitor Data  from Backplane

NET 'RCVD_SAVE_MONIT_DATA'  U1041-14     # This is the Received Save
                                         # Monitor Data signal



#  SCL Initialize signal.

NET 'BKPLN_SCL_INIT_B'      U1041-5    # VME-64X Reserved Bus signal 3
                                       # SCL Initialize signal  from Backplane

NET 'RCVD_SCL_INIT'         U1041-15   # This is the Received SCL Initialize
                                       # signal.



#  Spare SCLD Control signal.

NET 'BKPLN_SCLD_SPARE_B'    U1041-4    # VME-64X Reserved Bus signal 6
                                       # Spare SCLD signal  from the Backplane

NET 'RCVD_SCLD_SPARE'       U1041-16   # Received Spare signal from SCLD




#  Unused Sections of U1041
#
#  The U1041 octal inverting OC Buffer Receiver has 2 spare sections.
#  These are:  Input on pin 2 - Out on pin 18   and    Input on pin 3 -
#  Out on pin 17.   The inputs to the two unused sections are tied to
#  Ground through  zero Ohm jumpers  W1041  and  W1042.

NET 'LFBT_INV_OC_REC_IN_1'   W1041-1   U1041-2   # Input to 1st unused section
NET 'GROUND'                 W1041-2             # of U1041 Invert OC Receiver

NET 'LFBT_INV_OC_REC_IN_2'   W1042-1   U1041-3   # Input to 2nd unused section
NET 'GROUND'                 W1042-2             # of U1041 Invert OC Receiver




#  Connect the two Enable pins on U1041 to Ground.

NET 'GROUND'   U1041-1  U1041-19     # Enable U1041 Octal Buffer


#  Connect the Vdd_Logic Power and Ground nets to U1041 Octal Buffer

NET 'VDD_LOGIC'  U1041-20

NET 'GROUND'     U1041-10


#  Include the nets for the U1041 bypass capacitors.

NET 'VDD_LOGIC'  C1041-1   C1042-2

NET 'GROUND'     C1041-2   C1042-1




#  Connect the differential Backplane BX_Clock signal to its
#  differential receiver.  This connection is made with an RC
#  network.  The Backplane BX_Clock receiver is the LVDS receiver
#  U1052.  Most of the nets to U1052 are covered in the file
#  referenced at the top of this document.
#
#  Note that this differential receiver is connected so that it
#  inverts the BX_Clock signal as it receives it.  The Backplane
#  BX_Clock signal is inverted to allow the BX_X8_Clock PLL to lock
#  onto it with a 180 degree shift in its phase detector and still
#  line up with the Backplane BX_Clock.


NET 'BKPLN_BX_CLOCK'     R1061-2        # VME-64X Reserved Bus signal 4
                                        # SCL BX_Clock  from the Backplane

NET 'BKPLN_BX_CLOCK_B'   R1062-2        # VME-64X Reserved Bus signal 5
                                        # SCL BX_Clock_B  from the Backplane


NET 'ISO_BX_CLK'       R1061-1   R1063-1   # Resistor divider connects to LVDS

NET 'ISO_BX_CLK_B'     R1062-1   R1064-1   # Resistor divider connects to LVDS

NET 'CAP_ISO_BX_CLK'   R1063-2   R1064-2   C1061-1  C1062-1   # help hold
                                                              # common mode
NET 'GROUND'                               C1061-2  C1062-2   # at AC Ground
                                                              # capacitors


NET 'ISO_BX_CLK'       U1052-15   # Direct backplane signal to the
                                  # inverting input of the LVDS receiver

NET 'ISO_BX_CLK_B'     U1052-14   # Complement backplane signal to the
                                  # non-inverting input of the LVDS receiver

NET 'TERM_RCVD_BX_CLOCK'  U1052-13  R1065-2  # Received BX_Clock signal coming
                                             # out of the LVDS receiver and
                                             # going to the series terminator

NET 'RCVD_BX_CLOCK'    R1065-1    # Series Terminated Received BX Clock
                                  # signal going to the Board Control
                                  # PAL Phase Detector input.