# This is a Key In Net List file for # the ADF-2 for the Run IIB Cal Trig # Receive SCLD - Drive Backplane Nets # ---------------------------------------- # # Original Rev. 24-MAY-2004 # Most Recent Rev. 9-SEPT-2004 # This file includes all the nets that receive the timing and # control signals from the SCLD and drive these signals onto the # P1 VME-64X Reserved Bused backplane lines. # # These circuits are shown in the drawing: # # www.pa.msu.edu/hep/d0/ftp/run2b/l1cal/hardware/adf_2/drawings/ # scld_control_signal_distribution.ps # scld_control_signal_distribution.pdf # Connection of nets to the P0 connector to receive the timing and # control signals from the SCLD is taken care of in the P0 (P3) # net list file. Connection of the nets to the VME-64X Reserved Bused # backplane lines is taken care of in the P1 net list file. # This file contains the nets for the following components: # # U1021 SN74AS760 Non-Inverting O.C. Driver Octal # # U1031 SN74AS756 Inverting O.C. Driver Octal # # U1051, U1052 SN65LVDS32 Quad LVDS Receiver # # R1051:R1057 100 Ohm 0603 resistor 1% Terminate LVDS from SCLD # # W1021:W1027 Zero Ohm 0603 jumpers if installed -> drive backplane # # W1028, W1029 Zero Ohm 0603 jumpers control input to 2 unused # of sections of U1021 # # W1031 Zero Ohm 0603 jumpers control input to unused # of section of U1031 # # C1051, C1052 0.1 uFd bypass capacitors to Vdd_Logic # # C1053, C1054 4.7 nFd bypass capacitors to Vdd_Logic # # C1021, C1031 0.1 uFd bypass capacitors to Vcc_Logic # C1022, C1032 4.7 nFd bypass capacitors to Vcc_Logic # Note that other sections of U1031 are used in the net files: # # vme_to_board_control_pal_nets.txt # drive_crate_status_and_crate_to_scld_nets.txt # power_up_supervisor_nets.txt # In the following notice that the LVDS Receiver is used to invert # the signal from the SCLD. Then a non-inverting open collector # driver is used to put the signal onto the VME-64X Reserved Bused # backplane line. This results in the "standard" for open collector # bused lines, i.e. the asserted state is the lower Voltage state. # Start with the SCL Beginning of Turn Marker signal. NET 'SCL_BEGIN_TURN_P' R1051-1 U1051-1 # SCLD->ADF Begin # of Turn Marker Direct NET 'SCL_BEGIN_TURN_N' R1051-2 U1051-2 # SCLD->ADF Begin # of Turn Marker Comp NET 'SCL_BEGIN_TURN_TTL' U1051-3 U1021-2 # Receiver Out to Driver In NET 'SCL_BEGIN_TURN_DRV' U1021-18 W1021-1 # Driver Out to Jumper NET 'BKPLN_BEGIN_TURN_B' W1021-2 # VME-64X Reserved Bus signal 0 # SCL Begin Turn Marker on Backplane # SCL Live Beam Crossing Marker signal. NET 'SCL_LIVE_BX_P' R1056-1 U1052-9 # SCLD->ADF Live Beam # Crossing Marker Direct NET 'SCL_LIVE_BX_N' R1056-2 U1052-10 # SCLD->ADF Live Beam # Crossing Marker Comp NET 'SCL_LIVE_BX_TTL' U1052-11 U1021-17 # Receiver Out to Driver In NET 'SCL_LIVE_BX_DRV' U1021-3 W1022-1 # Driver Out to Jumper NET 'BKPLN_LIVE_BX_B' W1022-2 # VME-64X Reserved Bus signal 1 # SCL Live BX Marker on Backplane # SCL Save Monitoring Data signal. NET 'SAVE_MONIT_DATA_P' R1053-1 U1051-9 # SCLD->ADF Save # Monitoring Data Direct NET 'SAVE_MONIT_DATA_N' R1053-2 U1051-10 # SCLD->ADF Save # Monitoring Data Comp NET 'SAVE_MONIT_DATA__TTL' U1051-11 U1021-4 # Receiver Out to Driver In NET 'SAVE_MONIT_DATA__DRV' U1021-16 W1023-1 # Driver Out to Jumper NET 'BKPLN_SAVE_MONIT_DATA_B' W1023-2 # VME-64X Reserved Bus signal 2 # Save Monitor Data signal on Backpln # SCL Initialize signal. NET 'SCL_INIT_P' R1057-2 U1052-7 # SCLD->ADF # SCL Initialization Direct NET 'SCL_INIT_N' R1057-1 U1052-6 # SCLD->ADF # SCL Initialization Comp NET 'SCL_INIT_TTL' U1052-5 U1021-6 # Receiver Out to Driver In NET 'SCL_INIT_DRV' U1021-14 W1024-1 # Driver Out to Jumper NET 'BKPLN_SCL_INIT_B' W1024-2 # VME-64X Reserved Bus signal 3 # SCL Initialize signal on Backplane # SCL BX_Clock signal. This signal remains differential on the Backplane. NET 'SCL_BX_CLOCK_P' R1054-1 U1051-15 # SCLD->ADF 7.57 MHz # Beam Cross Clock Direct NET 'SCL_BX_CLOCK_N' R1054-2 U1051-14 # SCLD->ADF 7.57 MHz # Beam Cross Clock Comp NET 'SCL_BX_CLOCK_TTL' U1051-13 U1031-8 # Receiver Out to Driver In NET 'SCL_BX_CLOCK_TTL' U1021-8 # Receiver Out to Driver In NET 'SCL_BX_CLOCK_DRVD' U1031-12 W1025-1 # Driver Out to Jumper NET 'SCL_BX_CLOCK_DRVC' U1021-12 W1026-1 # Driver Out to Jumper NET 'BKPLN_BX_CLOCK' W1025-2 # VME-64X Reserved Bus signal 4 # SCL BX_Clock on the Backplane NET 'BKPLN_BX_CLOCK_B' W1026-2 # VME-64X Reserved Bus signal 5 # SCL BX_Clock_B on the Backplane # Spare SCLD Control signal. NET 'SCLD_SPARE_P' R1052-1 U1051-7 # SCLD->ADF Spare Signal Direct NET 'SCLD_SPARE_N' R1052-2 U1051-6 # SCLD->ADF Spare Signal Comp NET 'SCLD_SPARE_TTL' U1051-5 U1021-11 # Receiver Out to Driver In NET 'SCLD_SPARE_DRV' U1021-9 W1027-1 # Driver Out to Jumper NET 'BKPLN_SCLD_SPARE_B' W1027-2 # VME-64X Reserved Bus signal 6 # Spare SCLD signal on the Backplane # Spare section of the LVDS Receiver U1052: # Put a terminator resistor on its input. This is R1055. # Its inputs are: Comp pin 1 Direct pin 2 Its out is: pin 3. NET 'SPARE_LVDS_REC_P' R1055-2 U1052-2 # Spare LVDS Receiver Direct Input NET 'SPARE_LVDS_REC_N' R1055-1 U1052-1 # Spare LVDS Receiver Comp Input # Connect the two Enable pins on each LVDS Receiver to Ground. NET 'GROUND' U1051-4 U1051-12 U1052-4 U1052-12 # Enable LVDS Receivers # Now connect the Vdd_Logic Power and Ground nets to the LVDS Receivers. NET 'VDD_LOGIC' U1051-16 U1052-16 NET 'GROUND' U1051-8 U1052-8 # Now include the nets for the LVDS Receiver bypass capacitors. NET 'VDD_LOGIC' C1051-2 C1052-2 C1053-2 C1054-2 NET 'GROUND' C1051-1 C1052-1 C1053-1 C1054-1 # Connect the two Enable pins on Drivers U1021 and U1031 to Ground. NET 'GROUND' U1021-1 U1021-19 U1031-1 U1031-19 # Enable Drivers # Now connect the Vcc_Logic Power and Ground nets to both Driver chips. NET 'VCC_LOGIC' U1021-20 U1031-20 NET 'GROUND' U1021-10 U1031-10 # Now include the nets for the Driver bypass capacitors. NET 'VCC_LOGIC' C1021-1 C1022-1 C1031-1 C1032-1 NET 'GROUND' C1021-2 C1022-2 C1031-2 C1032-2 # Spare Sections of Driver U1021 # # There are 2 spare sections of non-inverting open collector driver U1021: # One spare section is Input on pin 13 Output on pin 7 # The other spare section is Input on pin 15 Outout on pin 5. # # The inputs to the two spare sections of U1021 will be tied to # Ground through zero Ohm Jumpers W1028 and W1029. NET 'LFBT_NONIV_OC_DRV_IN_1' W1028-1 U1021-13 # Input to 1 unused section NET 'GROUND' W1028-2 # of U1021 non-inv driver NET 'LFBT_NONIV_OC_DRV_IN_2' W1029-1 U1021-15 # Input to 2 unused section NET 'GROUND' W1029-2 # of U1021 non-inv driver # Spare Section of Driver U1031 # # There is one spare section of inverting open collector driver U1031: # The spare section is Input on pin 15 Outout on pin 5. # # The input to the spare section of U1031 will be tied to # Ground through zero Ohm Jumper W1031. NET 'LFBT_INV_OC_DRV_IN_1' W1031-1 U1031-15 # Input to unused section NET 'GROUND' W1031-2 # of U1031 invert driver