# This is a Key In Net List file for # the ADF-2 for the Run IIB Cal Trig # VME to Board Control PAL Nets # ---------------------------------- # # Original Rev. 25-MAY-2004 # Most Recent Rev. 8-SEPT-2004 # This file includes all the nets that handle most of the VME P1 # backplane signals and connect these signals to the Board Control PAL. # Most of these signls are handled by latches U1001 and U1002 # but there is also one section of U1031 used for driving VME_DTACK_B # and one section of U1041 used for receiving VME_DS1_B. In addition # the VME Geographic Address pins and the VME System Reset pin # connect directly to the Board Control PAL. There are pull up # resistors on the VME Geographic Address pins which are included # in this net list file. # # These circuits are shown in the drawing: # # www.pa.msu.edu/hep/d0/ftp/run2b/l1cal/hardware/adf_2/drawings/ # board_control_pal_vme_interface.ps # board_control_pal_vme_interface.pdf # Connection of the nets to the VME P1 connector itself is taken # care of in the P1 net list file. # This file contains the nets for the following components: # # U1001, U1002 74LVC16374A 16 bit "D" Latch for VME # "adrs" type information # # U1031 74AS756 one section for driving VME_DTACK_B # # U1041 74LVC540A one section for receiving VME_DS1_B # # C1001:C1004, 0.1 uFd bypass capacitors to Vdd_Logic # # C1005:C1008 4.7 nFd bypass capacitors to Vdd_Logic # # R1001:R1005 4.99 k Ohm 0603 1% Pull up on VME Geographic Adrs # # W1006 Zero Ohm 0603 jumper control input to unused section # of U1002 a 74LVC16374A latch # Note that other sections of U1031 appear in the net list files: # # receive_scld_drive_backplane_nets.txt # drive_crate_status_and_crate_to_scld_nets.txt # power_up_supervisor_nets.txt # Note that other sections of U1041 appear in the net list file: # # receive_backplane_timing_and_control_nets.txt # First take care of the 31 VME backplane signals that are received # and latches by U1001 and U1002 before going to the Board Control PAL # and to the On Card Bus. # Latch for VME "adrs type" information U1002 NET 'VME_AM(5)' U1002-46 # 1D1 NET 'LTCHD_AM(5)' U1002-3 # 1Q1 NET 'VME_WRITE_B' U1002-44 # 1D2 NET 'LTCHD_WRITE_B' U1002-5 # 1Q2 NET 'VME_ADDR(23)' U1002-43 # 1D3 NET 'OCB_ADRS(23)' U1002-6 # 1Q3 NET 'VME_ADDR(22)' U1002-41 # 1D4 NET 'OCB_ADRS(22)' U1002-8 # 1Q4 NET 'VME_AM(0)' U1002-40 # 1D5 NET 'LTCHD_AM(0)' U1002-9 # 1Q5 NET 'VME_ADDR(21)' U1002-38 # 1D6 NET 'OCB_ADRS(21)' U1002-11 # 1Q6 NET 'VME_AM(1)' U1002-37 # 1D7 NET 'LTCHD_AM(1)' U1002-12 # 1Q7 NET 'VME_ADDR(20)' U1002-36 # 2D0 NET 'OCB_ADRS(20)' U1002-13 # 2Q0 NET 'VME_AM(2)' U1002-35 # 2D1 NET 'LTCHD_AM(2)' U1002-14 # 2Q1 NET 'VME_ADDR(19)' U1002-33 # 2D2 NET 'OCB_ADRS(19)' U1002-16 # 2Q2 NET 'VME_AM(3)' U1002-32 # 2D3 NET 'LTCHD_AM(3)' U1002-17 # 2Q3 NET 'VME_ADDR(18)' U1002-30 # 2D4 NET 'OCB_ADRS(18)' U1002-19 # 2Q4 NET 'VME_IACK_B' U1002-29 # 2D5 NET 'LTCHD_IACK_B' U1002-20 # 2Q5 NET 'VME_ADDR(17)' U1002-27 # 2D6 NET 'OCB_ADRS(17)' U1002-22 # 2Q6 NET 'VME_ADDR(16)' U1002-26 # 2D7 NET 'OCB_ADRS(16)' U1002-23 # 2Q7 # U1002 has one unused section. Tie its input to Gnd # through a zero Ohm jumper W1006. The output from # this unused section is not connected. NET 'LFBT_LATCH_IN_1' W1006-2 U1002-47 # 1D0 Input to unused section NET 'GROUND' W1006-1 # of U1002 a 16 bit Latch ##NET ' U1002-2 # 1Q0 Output from the unused ## # Latch is not connected # Latch for VME "adrs type" information U1001 NET 'VME_ADDR(15)' U1001-47 # 1D0 NET 'OCB_ADRS(15)' U1001-2 # 1Q0 NET 'VME_AM(4)' U1001-46 # 1D1 NET 'LTCHD_AM(4)' U1001-3 # 1Q1 NET 'VME_ADDR(14)' U1001-44 # 1D2 NET 'OCB_ADRS(14)' U1001-5 # 1Q2 NET 'VME_ADDR(7)' U1001-43 # 1D3 NET 'OCB_ADRS(7)' U1001-6 # 1Q3 NET 'VME_ADDR(13)' U1001-41 # 1D4 NET 'OCB_ADRS(13)' U1001-8 # 1Q4 NET 'VME_ADDR(6)' U1001-40 # 1D5 NET 'OCB_ADRS(6)' U1001-9 # 1Q5 NET 'VME_ADDR(12)' U1001-38 # 1D6 NET 'OCB_ADRS(12)' U1001-11 # 1Q6 NET 'VME_ADDR(5)' U1001-37 # 1D7 NET 'OCB_ADRS(5)' U1001-12 # 1Q7 NET 'VME_ADDR(11)' U1001-36 # 2D0 NET 'OCB_ADRS(11)' U1001-13 # 2Q0 NET 'VME_ADDR(4)' U1001-35 # 2D1 NET 'OCB_ADRS(4)' U1001-14 # 2Q1 NET 'VME_ADDR(10)' U1001-33 # 2D2 NET 'OCB_ADRS(10)' U1001-16 # 2Q2 NET 'VME_ADDR(3)' U1001-32 # 2D3 NET 'OCB_ADRS(3)' U1001-17 # 2Q3 NET 'VME_ADDR(9)' U1001-30 # 2D4 NET 'OCB_ADRS(9)' U1001-19 # 2Q4 NET 'VME_ADDR(2)' U1001-29 # 2D5 NET 'OCB_ADRS(2)' U1001-20 # 2Q5 NET 'VME_ADDR(8)' U1001-27 # 2D6 NET 'OCB_ADRS(8)' U1001-22 # 2Q6 NET 'VME_ADDR(1)' U1001-26 # 2D7 NET 'OCB_ADRS(1)' U1001-23 # 2Q7 # Ground the OE_B pins on the U1001 and U1002 latches: NET 'GROUND' U1001-1 U1001-24 U1002-1 U1002-24 # Connect the clock net to the clock input pins on these latches: NET 'VME_LTCH_CLK' U1001-25 U1001-48 U1002-25 U1002-48 # Connect the Vdd power supply pins to these latches: NET 'VDD_LOGIC' U1001-7 U1001-18 U1001-31 U1001-42 NET 'VDD_LOGIC' U1002-7 U1002-18 U1002-31 U1002-42 # Connect the Ground pins to these latches: NET 'GROUND' U1001-4 U1001-10 U1001-15 U1001-21 NET 'GROUND' U1001-28 U1001-34 U1001-39 U1001-45 NET 'GROUND' U1002-4 U1002-10 U1002-15 U1002-21 NET 'GROUND' U1002-28 U1002-34 U1002-39 U1002-45 # Now include the nets for the bypass capacitors on the latches: # 0.1 uFd Ceramic NET 'VDD_LOGIC' C1001-1 C1002-2 C1003-1 C1004-2 NET 'GROUND' C1001-2 C1002-1 C1003-2 C1004-1 # 4.7 nFd Ceramic NET 'VDD_LOGIC' C1005-2 C1006-1 C1007-2 C1008-1 NET 'GROUND' C1005-1 C1006-2 C1007-1 C1008-2 # The following net connections are for driving the VME_DTACK_B signal. # This VME signal is driven by one section of U1031. NET 'DRV_DTACK' U1031-2 # Connect the DRV_DTACK signal that comes from # the Board Control PAL to the driver input. NET 'VME_DTACK_B' U1031-18 # The driver output connects to the # backplane VME DTACK_B pin. # The following net connections are for receiving the VME_DS1_B signal. # This VME signal is received by one section of U1041. NET 'VME_DS1_B' U1041-9 # Backplane VME DS1_B signal connects # to receiver input. NET 'RCVD_DS1' U1041-11 # The received and inverted VME_DS1_B signal # now goes to the Board Control PAL. # The following nets are the pull up resistors on the VME backplane # Geographic Address lines. These 5 Geographic Address signals are # pulled up before being sent to the Board Control PAL VME Interface. # On the backplane the Geographic Address pins are either floating # or tied to Gnd. The pull up resistors are R1001 : R1005. NET 'VME_GEO_B(0)' R1001-2 # Pull up VME-64X Geographic Adress (0) bar NET 'VME_GEO_B(1)' R1002-2 # Pull up VME-64X Geographic Adress (1) bar NET 'VME_GEO_B(2)' R1003-2 # Pull up VME-64X Geographic Adress (2) bar NET 'VME_GEO_B(3)' R1004-2 # Pull up VME-64X Geographic Adress (3) bar NET 'VME_GEO_B(4)' R1005-2 # Pull up VME-64X Geographic Adress (4) bar # Connect the high side of these pull up resistors to the Vdd_Logic supply. NET 'VDD_LOGIC' R1001-1 R1002-1 R1003-1 R1004-1 R1005-1