ADF-2 Picture Index ----------------------- Original Rev. 12-MAR-2004 Most Recent Rev. 28-FEB-2006 This file provides information about the various pictures of the ADF-2 card that are stored in this directory. The more recent additions to this list of picture descriptions are at the beginning of this file. adf_2_pll_jitter.tif 28-FEB-2006 This scope pictures is a study of the relative jitter between the X8_Clock lines on two ADF_2 cards. The X8_Clock signal on each ADF_2 cards is monitored on pin #33 of its P4 access connector. The lower scope trace, Ch #1, is the X8_Clock from the ADF_2 card in slot #10. This scope input is used to trigger the scope. The upper scope trace, Ch #2, is the X8_Clock from the ADF_2 card in slot #20. There are also ADF_2 cards in slots 11 (Maestro receiving the SCLD) and 19. All 4 of the ADF_2 cards are configured with T7_Phy firmware and are sending out PRN data on their Channel Link outputs. The ADF_2 cards in slots: 10, 19, and 20 have their Channel Link Transmitters set for mid level of pre-emphasis, i.e. 9.09 K Ohm pre-emphasis resistors. Thus each of the monitored ADF_2 cards has another card next to it (either on the right or left) also making digital noise. This scope picture is the integral of about 14 hours of the scope looking at these two signals while it was set for infinite persistence. tek_sidewalk_bls_vs_backplane_7.tif 28-OCT-2005 tek_sidewalk_bls_vs_backplane_6.tif 28-OCT-2005 Both of these scope pictures were taken on the Sidewalk with the new SCLD T5 firmware installed and running. See note book #7 page 169. tek_sidewalk_bls_vs_backplane_7.tif is used just to verify the timing of the backplane control signals vs the X8_Clock_Enb signals on the ADF-2 card. The light blue trace is the backplane LvBX control signal sampled from the backplane with a scope probe. The dark blue signal is the X8_Clock_Enb signal sampled on the ADF-2 card with a scope probe. The implication is that things are adjusted OK. The control signal has some 70 nsec of setup time before the edge of the X8_Clock that will ingest it and it has some 40 nsec of hold time. This was (and should not have been) any change in this wrt SCLD T3 firmware. tek_sidewalk_bls_vs_backplane_6.tif is used to verify the timing of the LvBX crossing control signal in the ADF Crate backplane vs the LvBX crossing in D-Zero signal from the CMC rack front panel. Dark blue is the BOT marker signal from the ADF Crate backplane. Light blue is the LvBX control signal from the ADF Crate backplane. Green is the CMC D-Zero crossing signal from the small panel on the M100 rack as seen through 37 nsec of cable. The raw scope data shows the leading edge of the backplane LvBX control signal to be about 856 nsec after the CMC LvBX crossing signal. Taking cable delays into consideration the real delay from CMC LvBX to ADF Crate LvBX is about 885 nsec. Compare this with note book #7 page 153 and page 161. T5 looks 1175 nsec - (17 x 18.83 nsec) = 855. ===> SCLD T5 looks OK. tek_sidewalk_bls_vs_backplane_5.tif 29-JULY-2005 This shows the: Top in Dirk Blue the Master Clock Time Line #2, Begin of Turn marker, as seen through a 32 nsec cable from the CMC Monitor Output, Middle in Light Blue the Patch Panel Monitor Output of the Hand Pulser set for 360 nsec before the first backplane BX marker as seen through the short monitor cable, Bottom in Green the Backplane BX Marker from the CTFE Crate as seen through a scope probe. This is SCLD T3 firmware. Pg 133 and 155. tek_sidewalk_bls_vs_backplane_3.tif tek_sidewalk_bls_vs_backplane_4.tif 18-MAY-2005 This shows the real BLS signal on the sidewalk vs the raw Begin_of_Turn and Live_BX signals in the ADF-2 Crate backplane. This is with the SCLD_T3 firmware. SCLD_T3 is the first attempt to align the timing in the ADF-2 Crate with the BLS signals. The BLS signal is from TT Eta -9 EM. The pictures show the peak of the BLS signal to be about 360 nsec before the beginning of the 132 nsec long Live_BX signal. Picture #3 is the BLS signal from the first BX in the first Super Bunch. Picture #4 is the BLS signal from the last BX in a Super Bunch. tek_sidewalk_bls_vs_backplane_1.tif tek_sidewalk_bls_vs_backplane_2.tif 6-MAY-2005 This shows the real BLS signal on the sidewalk vs the raw Begin_of_Turn and Live_BX signals in the ADF-2 Crate backplane. This is with SCLD_T2 firmware. The BLS signal is from TT eta -9 EM. These scope pictures were an initial look to see about how long the control signals from SCLD_T2 would need to be delayed in the SCLD before being sent to the ADF-2 Crates. BX_Clk Signal Scope Pictures 12-MAR-2004 All of these scope pictures from March 2004 are from a study of how best to transpost the BX_Clock signal across the ADF Crate backplane using spare bused VME-64X lines. In the final ADF_2 design, the BX_Clock signal was not received as described in these tests but the rest of this study is still valid. The BX_Clk signal scope pictures in this directory were taken with the two VME-64x bus lines that carry the differential BX_Clk signal being driven at 8 MHz by TTL open collector drivers ('38's). The bus is loaded with 21 receiver loads. The driver is in the middle, in slot number 11 (1:21). The loads consist of 10 blocks that each provide twice the normal load. These blocks are made with 500 Ohm and 250 Ohm resistors and 30 pFd capacitors. The capacitors simulate the 10 pFd input capacitance to a Virtex-II I/O block that is specified in the Virtex-II data sheet. These 10 load blocks are placed along the length of the VME bus at every other slot. There is one additional load block that is made with the resistor values that are planned for the BX_Clk input circuit on the ADF-2 card, i.e. 1k Ohm and 500 Ohm resistors. The scope probes are connected to this load block. The scope probes themselves simulate the input capacitance of the Virtex-II I/O block. This load block is moved from slot to slot to make the various measurements. Except for the horizontal sweep rate, the setup of the scope is the same in all cases. In these pictures: Channel #1 trace is at the top and is dark blue. This trace is the non-inverted side of the BX_Clk signal as it enters the LVDS Receiver. Channel #2 trace is at the bottom and is light blue. This trace is the inverted side of the BX_Clk signal as it enters the LVDS Receiver. The difference (Ch#1 - Ch#2) is in the middle and is red. This is the differential BX_Clk signal as seen by the LVDS Receiver. The small arrows on the left of the screen "1" "2" "M" show the zero Volt levels for each of these 3 traces. Just above the center horizontal graticule is a solid dark blue line. This indicates where the differential input to the LVDS Receiver has reached + 100 mV. Just below the center horizontal graticule is a dashed dark blue line. This indicates where the differential input to the LVDS Receiver has reached - 100 mV. The horizontal sweep rate per division is shown near the bottom center. The scope pictures in this series are: bx_clk_signal_end_slot_40_ns.tif # Looking at the end of the bus. bx_clk_signal_mid_slot_40_ns.tif # Looking mid way between bx_clk_signal_mid_slot_20_ns.tif # the driver and the end bx_clk_signal_mid_slot_10_ns.tif # of the bus. bx_clk_signal_next_to_slot_40_ns.tif # Looking next to the driver.