Bit-3 DMA Read Problem with the ADF-2 Cards --------------------------------------------- Original Rev. 26-MAR-2009 Current Rev. 2-APR-2009 This note describes the problem that we had getting the model 618 Bit-3 cards to work when doing DMA reads from readout buffers in the ADF-2 cards. This problem is in the VME card of the Bit-3 card pair. This problem is present only in the more recent examples of the Bit-3 model 618 interface that we have access to. Specifically: In House Date on its Does it work Bit-3 Labels Name of the Optical Doing DMA Reads on the Bit-3 Interface Transceiver from the ADF-2 J2 Connector --------------- ----------- --------------- ------------ L1 Cal Spare Nov 2002 Yes - (now running in the L1 Cal since 17-FEB-2009) "Ours" MSU Aug 2003 Yes S/N 623453 Test Stand 85853630 Revision B "Broken" July 2004 No S/N 710262 L1 Cal 85853630 Revision E T962 #1 Aug 2007 No S/N 826467 85853630 Revision F T962 #2 Aug 2007 No - A typical test command used to exercise the DMA writes and reads to memory in the VME crate was the following: > CD SBS Technologies > CD Model_984 > CD bin > datachk -t a24 -a 0x282000 -w 2 -l 1024 As shown this test is doing A24 addressing, starting at address $282000, moving 16 bit words, and writing and reading a 1024 byte long buffer. All of the cycles that we are interested in are A24, D16. Note that if you set a very low buffer length, e.g. 2, then the Bit-3 interface may choose to do it via PIO. I know that if you specify a 20 byte buffer length that it will use DMA. These tests worked OK with a MVME-214 card in the crate using either an "old" or a "new" Bit-3 interface. We could watch both the DMA write cycles and the DMA read cycles on the scope. These cycles looked the same for both the "old" and "new" interfaces. These tests worked OK with an ADF-2 card if one of the older Bit-3 interfaces was used. These tests failed if one of the newer Bit-3 interfaces was used. When the test failed we could see that it completed its DMA writes OK and then it stopped after doing just one DMA read. The one DMA read cycle would complete correctly but the software would said, "Remote bus timeout.. \src\datachk.c line 351:". Note that there was no problem with the one DMA read cycle that was done by the Bit-3 - that cycle completed correctly. After much investigation it was determined that the "new" Bit-3 VME cards will fail doing DMA Reads if the slave does not set its DTACK* line back to the non-asserted voltage Hi state within about 80 nsec of the Bit-3 master settings its DS1* line back to the non-asserted voltage Hi state at the end of the cycle. - The "old" Bit-3 VME cards do not place this requirement on the slave that is responding to the DMA read cycle. - Neither the "old" or "new" Bit-3 VME cards place this requirement on PIO read or write cycles or on DMA write cycles. - There is no requirement in the VME Specification that the slave must release its DTACK* line within a certain amount of time after the Data Strobes go back to the the non-asserted state. GE Fanuc Bit-3 offered no help for this problem. Bit-3 is now part of a big company and it appears that you can no longer talk with any one there who knows anything. The only people there that one can talk with showed no interest in the fact that their interface does not match the VME specification. To get the T962 system running, without requiring us to find more "old" type Bit-3 VME interfaces, an adaptor was made to go between the Bit-3 VME card and the VME Bus. This adaptor does the following: 1. The adaptor terminates the DTACK* signal that is sent to the Bit-3 VME card as soon as the Bit-3 VME card drops the Data Strobe. This step is to satisfy the requirement made by the "new" type Bit-3 VME cards that the DTACK* signal terminate within 80 nsec of the rising edge of the Data Strobe. 2. When the Bit-3 VME card asserts the Data Strobe for the N+1 cycle the adaptor does not assert the Data Strobe on the VME bus until after it sees that the DTACK* signal on the bus from the Nth cycle has actually gone back to its no-asserted state. That is, the adaptor waits until it sees that the ADF-2 card is actually finished with the Nth cycle before letting the Data Strobe for the N+1 cycle onto the bus. This step prevents the potential problem caused by the first step that the Bit-3 VME card could start the N+1 cycle before the ADF-2 card had finished the Nth cycle. Scope pictures in this directory: new_bit3_with_adaptor_dma_read.tif 16:45 on 25-Mar-09 This is the T962 #1 Bit-3 with the adaptor card doing DMA reads from an ADF-2 card. These DMA read cycles are from the test shown in the command line above. Trace #1 is DS1* from the backplane Trace #2 is DTACK* from the backplane Trace #3 is DS1* coming from the Bit-3 VME card Trace #4 is the DTACK* signal going to the Bit-3 VME card The average cycle time in the middle of this burst of DMA reads is about 1.19 usec. new_bit3_with_adaptor_pio_write.tif 9:47 on 26-Mar-09 This is the T962 #1 Bit-3 with the adaptor card doing PIO writes to an ADF-2 card. These cycles are from the configuration command for the FPGAs on the ADF-2. The scope traces are the same as described for the scope picture above. The average cycle time in the middle of this FPGA configuration write sequence is about 2.44 usec. old_bit3_wo_adaptor_dma_read.tif 10:14 on 26-Mar-09 This is the "Our MSU" Bit-3 without the adaptor card doing DMA reads from an ADF-2 card. These DMA read cycles are from the test shown in the command line above. Trace #1 is DS1* from the backplane Trace #2 is DTACK* from the backplane Trace #4 is AS* from the backplane The average cycle time in the middle of this burst of DMA reads is about 1.19 usec. old_bit3_wo_adaptor_pio_write.tif 10:22 on 26-Mar-09 This is the "Our MSU" Bit-3 without the adaptor card doing PIO writes to an ADF-2 card. These cycles are from the configuration command for the FPGAs on the ADF-2. The scope traces are the same as described for the scope picture above. The average cycle time in the middle of this FPGA configuration write sequence is about 2.25 usec.