ADF Prototype to Version 2  Recommended Changes
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The following is the list of changes that I would like to see made in
the ADF design before the layout of version 2 takes place.  The following
are the motivations for these changes:

  Guarantee as much as possible that version 2 will be full functional.

  Minimize the complications in raw pcb manufacture and board assembly.

  Make this card easier to debug during production testing and easier
  to maintain.

  Give the lowest ADC noise and widest operating margins to minimize
  problems during normal use of the Run 2B L1 Cal Trig.

                                               Original Rev.  12-JAN-2004
                                               Current Rev.   15-MAR-2004


Design Changes:

Changes to the Analog-ADC Section:

  Remove the input attenuators and instead operate the Diff Amp at
  a gain of 1/3.

  Flip the sense of the DAC and use 1/2 FS ADC range from the DAC.

  Move the DAC's to the South side of the FPGA's.

  Do not use the ADC Ref to make a 2.5 V reference.

  Use a separate reference supply for the DAC's.

  Do not distribute 2.5 V reference into the front-ends.

  Remove the LM324's.

  Common Mode Ref for Diff Amp output is a 2R/R split of Vdd.

  Scale up all R's to 499 Ohm feedback.

  Use a 3 capacitor ADC input filter.

  Pick ADC filter input R's to provide  ADC input current limit protection.

  Use a Unit Cell array layout for the Analog-ADC section.

  Use clean differential input and analog layout routing.

  Re-map the P2 BLS cable pinout to fit a rational eta,phi unit-cell layout.

  Use series resistors in the ADC digital output lines to control noise.

  Tie THS4141 pin #7 to Gnd.

  Use correct Power Pad connection to the Gnd Plane.



Changes to the Power Supplies:

  Both DC-DC converters should use the same layout.

  Shrink or move slightly the DC-DC converter layout to get the
  front panel space for the LED's.

  Get all of the signal traces out of the DC-DC converter area.

  Moat the Gnd planes around the DC-DC converters.

  Moat the used power plane around the DC-DC converters.

  Remove the unused power plane under the DC-DC converters.

  Separate the analog and digital power supplies.

     Bus +5V        will run 5 volt logic and both DC-DC converters
     Bus +3V3       will run 3V3 Analog
     Bus +12V,-12V  will be made into +5V,-5V Analog



Changes to the Clock Distribution:

  Need to find a clean way to implement backplane distribution
  of the BX clock.  Use differential transmission and LVDS reception.

  Remove the 2 loads per card on the backplane BX clock line.

  Need to use a clean and the correct layout for the CY2308.

  Move the CY2308 out of the DC-DC converter section.



Changes to the FPGA Layout and Pinout:

  Remove the massive North/South crossover.

  Layout the FPGA so that it ingests the ADC lines in a rational
  layout order.

  Plan the use of the I/O Banks:

     Will require changes to the circuit design.

     Will require changes to the FPGA ucf file.

  ADF-2 will make the "DONE" signal from each FPGA visible to a board level
  control status register in the Complex PAL instead of tying all the DONE's
  together and making just that visible in a single bit.



Changes to the General Layout:

  Place all LED's are on the front panel and move them North of the
  Analog-ADC section.

  Add the rows of Gnd pins in P0 to isolate the 3 Channel Link outputs.

  Connect the shield over P0 to Gnd.

  Put the Reference Designators into a rational order:
     DC-DC Converters
     Analog-ADC unit cells
     4x FPGA
     3x Serializers

  Implement the correct full recommended bypass decoupling.

  Stop sharing via's to Gnd and Power planes

  Connect the Extended Length pins and remove the useless "bussing
  of those traces".

  Fix the bypass layout around the 64 MHz crystal oscillator.

  Pull off the VME Debug connector.

  Verify the FPGA size to use.

  Verify the  Analog Input range and test the raw BLS Cable to P2 Cable
  before committing to the design.