Notes on ADF usage of VME address space Mainly based on 041102_adf_design.ppt 16-MAR-2004 ************************************************************************** Each card uses two sections of address space. One for configuring the FPGAs, and one for communicating with the FPGA logic ************************************************************************** ADF Configuration Space Address =============================== The configuration Registers are accessible with A24/D8 transfers (while some registers are in fact only 4 bits wide). +---+------+---------------+------+-----------------------------+--------------+ | A | A A | A A A A A | A A | A A A A A A A A A A A A A A | | | 2 | 2 2 | 2 1 1 1 1 | 1 1 | 1 1 1 1 0 0 0 0 0 0 0 0 0 0 | | | 3 | 2 1 | 0 9 8 7 6 | 5 4 | 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | | +---+------+---------------+------+-----------------------------+--------------+ | | | Slot ID # | | | | | | | [1..21] | | | | | | | S S S S S | | | | | X | 1 1 | 2 1 0 4 3 | 0 0 | X X X X X X X X X X X X X X | Config Reg A | | | | | | | | | X | | bits | 0 1 | X X X X X X X X X X X X X X | Config Reg B | | | | NOT IN ORDER! | | | | | X | | | 1 0 | X X X X X X X X X X X X X X | Config Reg C | | | | | | | | | X | | | 1 1 | X X X X X X X X X X X X X X | Config Reg D | | | | | | | | +---+------+---------------+------+-----------------------------+--------------+ Note: Slot ID bits are not in order for the configuration space. The location of Slot ID bits 0,1,2 are in the same position as User Space. Configuration Space Base Address = 0x600000 -------------------------------- If A23 is not decoded, this is also at 0xE00000 This was verified for Config Reg D at slot 11: [0]>peekb 0 0x6dc000 Crate 0 Address = 0x6dc000 Data Byte = 0xf (15) (Slot[11].FPGA_BUSY_DONE ??) [1]>peekb 0 0xedc000 Crate 0 Address = 0xedc000 Data Byte = 0xf (15) (Slot[11].FPGA_BUSY_DONE ??) Card Configuration Space Address Offset: --------------------------------------- The 2 upper hexadecimal digits depend on slot ID: address bit 16 slot ID bit 3 address bit 17 slot ID bit 4 address bit 18 slot ID bit 0 address bit 19 slot ID bit 1 address bit 20 slot ID bit 2 This bit ordering may look a bit strange, but this was done to overcome some hardware limitations in the address map and decoding. This means that the base address of the VME configuration registers for each card slot is: Slot ID Configuration Space Base Address If A23 is not decoded, also at ------------------------------------------------------------------------------ 1 Slot reserved for crate controller 2 0x680000 0xE80000 3 0x6C0000 0xEC0000 4 0x700000 0xF00000 5 0x740000 0xF40000 6 0x780000 0xF80000 7 0x7C0000 0xFC0000 8 0x610000 0xE10000 9 0x650000 0xE50000 10 0x690000 0xE90000 11 0x6D0000 0xED0000 12 0x710000 0xF10000 13 0x750000 0xF50000 14 0x790000 0xF90000 15 0x7D0000 0xFD0000 16 0x620000 0xE20000 17 0x660000 0xE60000 18 0x6A0000 0xEA0000 19 0x6E0000 0xEE0000 20 0x720000 0xF20000 21 0x760000 0xF60000 ------------------------------------------------------------------------------ Configuration Registers: ----------------------- The CPLD implements two 8 bit output ports (write only) and one 4 bit output ports (write only) and one 4 bit input port (read only). These ports implement 4 registers used to drive the configuration pins of the 4 FPGA's. The last 4 hexadecimal digits of the address select the configuration registers as discribed in the table below: Address Offset Width R/W Register Content (MSB .. LSB) ------------------------------------------------------------ 0x0000 8 W Conf Reg A PCS_B<3..0> PROG_B<3..0> 0x4000 8 W Conf Reg B FPGA_DATA<7..0> 0x8000 4 W Conf Reg C Unused RESET RD_WR_B CCLK 0xC000 4 R Conf Reg D Unused INIT_B DONE BUSY ------------------------------------------------------------ These registers are implemented in the CPLD and defined in vmeglue.vhd where these Configuration Registers are called Output Port #0,1,2 and Input Port #0. Configuration Register A ------------------------ Address: Configuration Space Base Address + Config Address Offset (Card Slot) + 0x0000 This register is visible at 16k consecutive D8 addresses (offsets 0x0000 thru 0x3FFF) This register is 8 bit wide and Write Only Data Bit Function ------ ---------------------------------- 0 ProgG_B FPGA #0 1 ProgG_B FPGA #1 2 ProgG_B FPGA #2 3 ProgG_B FPGA #3 4 CS_B FPGA #0 5 CS_B FPGA #1 6 CS_B FPGA #2 7 CS_B FPGA #3 Configuration Register B ------------------------ Address: Configuration Space Base Address + Config Address Offset (Card Slot) + 0x4000 This register is visible at 16k consecutive D8 addresses (offsets 0x4000 thru 0x7FFF) This register is 8 bit wide and Write Only Data Bit Function ------ ---------------------------------- 0 Configuration Data Bit 0 1 Configuration Data Bit 1 2 Configuration Data Bit 2 3 Configuration Data Bit 3 4 Configuration Data Bit 4 5 Configuration Data Bit 5 6 Configuration Data Bit 6 7 Configuration Data Bit 7 Configuration Register C ------------------------ Address: Configuration Space Base Address + Config Address Offset (Card Slot) + 0x8000 This register is visible at 16k consecutive D8 addresses (offsets 0x8000 thru 0xBFFF) This register is 4 bit wide and Write Only Data Bit Function ------ ---------------------------------- 0 Clock 1 RD/WR* 2 Reset used as a RESET signal for the user application logic implemented in the FPGA's. 3 Reserved 4 Unused 5 Unused 6 Unused 7 Unused Configuration Register D ------------------------ Address: Configuration Space Base Address + Config Address Offset (Card Slot) + 0xC000 This register is visible at 16k consecutive D8 addresses (offsets 0xC000 thru 0xFFFF) This register is 8 bit wide and Read Only Data Bit Function ------ ---------------------------------- 0 BUSY 1 DONE 2 INIT_B 3 Unused 4 Unused 5 Unused 6 Unused 7 Unused ************************************************************************** ADF user Address Space ====================== Each FPGA is connected to a 16 address lines / 16 data lines local bus that can be accessed via VME through the CY7C960A bridge and some glue logic. Each FPGA is allocated 64 KBytes of address space; an ADF board takes 256 KB and 8 MB are reserved for a whole ADF crate (32 x 64 kB - although only 21 cards can actually be present). For the complete system with 4 ADF crates, 32 MB of address space is needed - which is the limit of what can be allocated with the PCI/VME Bit3 interface. +---+---------------+------+---------------------------------+-----------------+ | A | A A A A A | A A | A A A A A A A A A A A A A A A A | | | 2 | 2 2 2 1 1 | 1 1 | 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 | | | 3 | 2 1 0 9 8 | 7 6 | 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | | +---+---------------+------+---------------------------------+-----------------+ | | Slot ID # | FPGA#| | | | |[1.21] in order|[0..3]| | FPGA Resource | | X | S S S S S | F F | FPGA Resource Address 15..0 | Registers | +---+---------------+------+---------------------------------+-----------------+ SSSSS = Slot ID Number 1..21 (but Slot #1 is used by crate controller) FF = FPGA Number 0..3 The base address for each card is decoded by matching the slot ID to address bits 22 downto 18. Card Slot Card Base Address If A23 is not decoded, also at --------- ------------------ ------------------------------ 1 Slot reserved for crate controller 2 0x080000 0x880000 3 0x0C0000 0x8C0000 4 0x100000 0x900000 5 0x140000 0x940000 6 0x180000 0x980000 7 0x1C0000 0x9C0000 8 0x200000 0xA00000 9 0x240000 0xA40000 10 0x280000 0xA80000 11 0x2C0000 0xAC0000 12 0x300000 0xB00000 13 0x340000 0xB40000 14 0x380000 0xB80000 15 0x3C0000 0xBC0000 16 0x400000 0xC00000 17 0x440000 0xC40000 18 0x480000 0xC80000 19 0x4C0000 0xCC0000 20 0x500000 0xD00000 21 0x540000 0xD40000 Each FPGA is then selected by decoding address bits 17 and 16. Fpga Num Fpga Base Address Offset --------- ---------------------------- 0 0x000000 1 0x010000 2 0x020000 3 0x030000 The base address for each FPGA on all 20 ADF cards is given below. Slot ID Base FPGA#0 Base FPGA#1 Base FPGA#2 Base FPGA#3 --------------------------------------------------------------------------- 1 Slot reserved for crate controller 2 0x080000 0x090000 0x0A0000 0x0B0000 3 0x0C0000 0x0D0000 0x0E0000 0x0F0000 4 0x100000 0x110000 0x120000 0x130000 5 0x140000 0x150000 0x160000 0x170000 6 0x180000 0x190000 0x1A0000 0x1B0000 7 0x1C0000 0x1D0000 0x1E0000 0x1F0000 8 0x200000 0x210000 0x220000 0x230000 9 0x240000 0x250000 0x260000 0x270000 10 0x280000 0x290000 0x2A0000 0x2B0000 11 0x2C0000 0x2D0000 0x2E0000 0x2F0000 12 0x300000 0x310000 0x320000 0x330000 13 0x340000 0x350000 0x360000 0x370000 14 0x380000 0x390000 0x3A0000 0x3B0000 15 0x3C0000 0x3D0000 0x3E0000 0x3F0000 16 0x400000 0x410000 0x420000 0x430000 17 0x440000 0x450000 0x460000 0x470000 18 0x480000 0x490000 0x4A0000 0x4B0000 19 0x4C0000 0x4D0000 0x4E0000 0x4F0000 20 0x500000 0x510000 0x520000 0x530000 21 0x540000 0x550000 0x560000 0x570000 --------------------------------------------------------------------------- FPGA User Address Space ----------------------- +-------+---+---+---+---+---+---+---+---+---+---+---+---+---+------------------+ | A A A | A | A | A | A | A | A | A | A | A | A | A | A | A | | | 1 1 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | | 5 4 3 | 2 | 1 | 0 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | | +-------+---+---+---+---+---+---+---+---+---+---+---+---+---+------------------+ | Chan# | | | | | | [0..7]| | | | | | C C C | 0 | RAM Address bits 10..0 | 0 |Et LUT 2048x 9b| | +---+---+---+---+---+---+---+---+---+---+---+---+---+------------------| | | 1 | 0 0 | RAM Address bits 8..0 | 0 |Raw Sampl 512x10b| | | +---+---+---+---+---+---+---+---+---+---+---+---+------------------| | | | 0 1 | RAM Address bits 8..0 | 0 |Convol Out 256x16b| | | +---+---+---+---+---+---+---+---+---+---+---+---+------------------| | | | 1 0 | RAM Address bits 8..0 | 0 |Filter Out 128x 8b| | | +---+---+---+---+---+---+---+---+---+---+---+---+------------------| | | | 1 1 | 0 0 0 | X X X | Addr 2..0 | 0 |Filt Coeff 8x 6b| | | | +---+---+---+---+---+---+---+---+---+---+------------------| | | | | 0 0 1 | X X X X X X | 0 |LFSR Seed | | | | +---+---+---+---+---+---+---+---+---+---+------------------| | | | | 0 1 0 | X X X X X X | 0 |Channel Reg A | | | | +---+---+---+---+---+---+---+---+---+---+------------------| | | | | 0 1 1 | X X X X X X | 0 |Channel Reg B | | | | +---+---+---+---+---+---+---+---+---+---+------------------| | | | | 1 0 0 0 | X X X X X | 0 |Global Reg A | | | | +---+---+---+---+---+---+---+---+---+---+------------------| | | | | 1 0 0 1 | X X X X X | 0 |Global Reg B | | | | +---+---+---+---+---+---+---+---+---+---+------------------| | | | | 1 0 1 0 | X X X X X | 0 |Global Reg C | | | | +---+---+---+---+---+---+---+---+---+---+------------------| | | | | 1 0 1 1 | X X X X X | 0 |Global Reg D | | | | +---+---+---+---+---+---+---+---+---+---+------------------| | | | | 1 1 0 0 | X X X X X | 0 |Global Reg E | | | | +---+---+---+---+---+---+---+---+---+---+------------------| | | | | 1 1 0 1 | X X X X X | 0 |Global Reg F | +-------+---+---+---+---+---+---+---+---+---+---+---+---+---+------------------+ CCC = Channel Number 0..7 Verified that A23 is not decoded, by writing/reading the LFSR register of Slot #11, FPGA#0, Channel #0 First read the default value (0) [5]>peeks 0 0x2c1c80 Crate 0 Address = 0x2c1c80 Data Short = 0x0 (0) (Slot[11].FPGA[0].Channel[0].LFS R_Seed ??) Write a different value [6]>pokes 0 0x2c1c80 0xaaaa Read it back [7]>peeks 0 0x2c1c80 Crate 0 Address = 0x2c1c80 Data Short = 0xaaaa (43690) (Slot[11].FPGA[0].Channel [0].LFSR_Seed ??) The same value can be read at address where A23 is set to 1 [10]>peeks 0 0xac1c80 Crate 0 Address = 0xac1c80 Data Short = 0xaaaa (43690) (Slot[11].FPGA[0].Channel [0].LFSR_Seed ??) Chan Num Channel Base Address Offset --------- ---------------------------- 0 0x000000 1 0x002000 2 0x004000 3 0x006000 4 0x008000 5 0x00A000 6 0x00C000 7 0x00E000 RAM Et Lookup Table ------------------- 2048 x 9 bit LUT to convert peak to final transverse energy (only the 8 LSB's are used in reality) There is one such RAM per ADC Channel, i.e. 32 per card. Address: Card Base Address + Fpga Base Address + Channel Base Address + 0x0000 to +0x0FFE RAM Raw ADC Sample ------------------ 512 x 10 bit RAM storing the last 512 ADC samples There is one such RAM per ADC Channel, i.e. 32 per card. Address: Card Base Address + Fpga Base Address + Channel Base Address + 0x1000 to +0x13FE RAM Convolver Output -------------------- 512 x 16 bit RAM storing the 256 last outputs of the convolver (only the 16 MSB's are kept and each result is written twice at consecutive addresses) There is one such RAM per ADC Channel, i.e. 32 per card. Address: Card Base Address + Fpga Base Address + Channel Base Address + 0x1400 to + 0x177E RAM Filter Et Result -------------------- 512 x 8 bit RAM storing the last 128 output of the final result of the digital filter, after peak detection and and final Et look-up. Each result is written four times at consecutive addresses. Note that only the 6 LSB can be written; and when writing, these six bit MUST be placed on the 6 MSBs of the short data word. When reading-back, these bits are placed on the 8 LSBs of the short word. This comes from hardware implementation; and is not a real issue because this memory is normally read-only. There is one such RAM per ADC Channel, i.e. 32 per card. Address: Card Base Address + Fpga Base Address + Channel Base Address + 0x1800 to + 0x1B7E [these RAM descritpion found in adf_board.c :: ADFboard_RamOperation] Filter Coefficients ------------------- 8 x 6 bit There is one such RAM per ADC Channel, i.e. 32 per card. Address: Card Base Address + Fpga Base Address + Channel Base Address + 0x1C00 to + 0x1C0E not clear about the rest of the address space up to + 0x1C7E most likely just not decoded, and same data appears 8 times LFSR Seed Register ------------------ There is one such register per ADC Channel, i.e. 32 per card. Address: Card Base Address + Fpga Base Address + Channel Base Address + 0x1C80 This register is visible at 64 consecutive addresses (offsets 0x1C80 thru 0x1CFE) Verified that the lower address bits of the misc registers are not decoded, by writing/reading the LFSR register of Slot #11, FPGA#0, Channel #0 First read the default value (0) [5]>peeks 0 0x2c1c80 Crate 0 Address = 0x2c1c80 Data Short = 0x0 (0) (Slot[11].FPGA[0].Channel[0].LFS R_Seed ??) Write a different value [6]>pokes 0 0x2c1c80 0xaaaa Read it back [7]>peeks 0 0x2c1c80 Crate 0 Address = 0x2c1c80 Data Short = 0xaaaa (43690) (Slot[11].FPGA[0].Channel [0].LFSR_Seed ??) The same value can be read at successive addresses [9]>peeks 0 0x2c1c88 Crate 0 Address = 0x2c1c88 Data Short = 0xaaaa (43690) (Slot[11].FPGA[0].Channel [0].LFSR_Seed ??) Data Bit R/W Function ------ --- ---------------------------------- 0..15 R/W LFSR Seed Channel Register A ----------------- There is one such register per ADC Channel, i.e. 8 per fpga and 32 per card. Address: Card Base Address + Fpga Base Address + Channel Base Address + 0x1D00 This register is visible at 64 consecutive addresses (offsets 0x1D00 thru 0x1D7E) Data Bit R/W Function ------ --- ---------------------------------- 0..1 R/W Input Decimator Phase Select 00: Select Phase #0 01: Select Phase #1 10: Select Phase #2 11: Select Phase #3 2 R/W Output Decimator Phase Select 0: Select Phase #0 1: Select Phase #1 3 R/W Peak Detector: 0: ON 1: OFF 4..5 R/W Convolver Post-Divisor 00: 01: 10: 11: 6 R/W Input Selector: 0: Real Data ADC 1: Raw Sample RAM 7..8 R/W Coarse Latency Adjustment: 00: +0 Beam X Ticks 01: +1 Beam X Ticks 10: +2 Beam X Ticks 11: +3 Beam X Ticks 9..10 R/W Serializer Source: 00: Filter Et Output 01: Constant Value Register 10: LFSR Value 11: Raw ADC Sample 11..15 R/W Spare The signal for this register are defined in FilterC.vhd line 1516 note: comments say bit 2 is "Peak detector output select" bit 4..5 "post multiplicand after peak detector" all bits are preset to 0 Channel Register B ------------------ There is one such register per ADC Channel, i.e. 32 per card. Address: Card Base Address + Fpga Base Address + Channel Base Address + 0x1D80 This register is visible at 64 consecutive addresses (offsets 0x1D80 thru 0x1DFE) Data Bit R/W Function ------ --- ---------------------------------- 0..7 R/W Constant Value Register 8..15 R/W Self Trigger Threshold 8 MSBits of ADC Raw Samples is compared to this Threshold The signal for this register are defined in FilterC.vhd line 1524 note: comments say bit 0..7 is "Constant Et value" constant value is preset to 0x00 threshold is preset to 0xff Global Register A ----------------- ?? There is one such register per FPGA, i.e. 4 per card. Address: Card Base Address + Fpga Base Address + Channel Base Address + 0x1E00 This register is visible at 32 consecutive addresses (offsets 0x1E00 thru 0x1E3E) and 8 separate address blocks (once for each Channel Base Address) Verified that a Global Register A appears on address blocks for multiple channels Read Global Register A within Slot #11, FPGA#0, Channel #0 [1]>peeks 0 0x2c1e00 Crate 0 Address = 0x2c1e00 Data Short = 0x0 (0) (Slot[11].FPGA[0].Glo_Reg_A ??) Write Global Register A within Channel #0 [2]>pokes 0 0x2c1e00 0x7 Read Global Register A within Channel #0, 1, 2 [4]>peeks 0 0x2c1e00 Crate 0 Address = 0x2c1e00 Data Short = 0x7 (7) (Slot[11].FPGA[0].Glo_Reg_A ??) [5]>peeks 0 0x2c3e00 Crate 0 Address = 0x2c3e00 Data Short = 0x7 (7) (Slot[11].FPGA[0].Glo_Reg_A ??) [6]>peeks 0 0x2c5e00 Crate 0 Address = 0x2c5e00 Data Short = 0x7 (7) (Slot[11].FPGA[0].Glo_Reg_A ??) Write Global Register A within Channel #2 [7]>pokes 0 0x2c5e00 0x5 Read Global Register A within Channel #2, 0 [8]>peeks 0 0x2c5e00 Crate 0 Address = 0x2c5e00 Data Short = 0x5 (5) (Slot[11].FPGA[0].Glo_Reg_A ??) [9]>peeks 0 0x2c1e00 Crate 0 Address = 0x2c1e00 Data Short = 0x5 (5) (Slot[11].FPGA[0].Glo_Reg_A ??) Data Bit R/W Function ------ --- ---------------------------------- 0..9 R/W Latency Offset Count (L) for Raw ADC sample RAM operation: - Write starts at: address 0 - Read (for send) starts at: (last_wr_address + L) mod 1024 10..12 R/W Fine latency adjust: 00: + 0/8 Beam X Ticks 01: + 1/8 Beam X Ticks 10: + 2/8 Beam X Ticks 11: + 3/8 Beam X Ticks 13 R/W ADC Output Enable Driven from each FPGA to its 4x input AD9218 ADC pin "S1" while pin "S0" is fixed low 0: Power-Down Both Channels. 1: Normal Operation 14 R/W Serializer DC Balanced Mode Inverted and driven from FPGA#0 to all DS90CR483 Serializer pin "BAL" 0: Enable Serializer DC Balance 1: DC Balance function is disabled. The purpose of DC Balance is to minimize the short- and long-term DC bias on the signal lines. This is achieved by selectively sending the data either unmodified or inverted. A DC Balance Bit in the data identifies 15 R/W Serializer Deskew Inverted and driven from FPGA#0 to Serializer pin "DS_OPT" 0: Normal operation 1: Cable Deskew performed. No Transmit data is sampled during Deskew. The Deskew operation is normally conducted after the TX and RX PLLs have locked. It should also be conducted after a system reset, or a reconfiguration event. It must be performed at least once when ’DESKEW’ is enabled. Deskew is only supported in the DC Balance mode. The signal for this register are defined in FilterD.vhd line 1710 Global Register B ----------------- Address: Card Base Address + Fpga Base Address + Channel Base Address + 0x1E40 This register is visible at 32 consecutive addresses (offsets 0x1E40 thru 0x1E7E) and 8 separate address blocks (once for each Channel Base Address) Data Bit R/W Function ------ --- ---------------------------------- 0..9 R/W Raw ADC sample send burst length (B) When send: - Start: (last_wr_addr + L) mod 1024 - End: (last_wr_addr + L + B) mod 1024 10 R/W Send raw ADC sample after L1 accept 0: Disable 1: Enable 11 R/W Convolver Enable 0: Disable 1: Enable 12 R/W Enable L1 Accept 0: Disable 1: Enable 13 R/W Enable L1 monitoring 0: Disable 1: Enable 14 R/W Enable L1 software 0: Disable 1: Enable 15 R/W Enable self L1 0: Disable 1: Enable Defined in FilterD.vhd line 1720 Comments in code for bits 12..15 are e.g. "Mask ...", not "Enable ..." Global Register C ----------------- Address: Card Base Address + Fpga Base Address + Channel Base Address + 0x1E80 This register is visible at 32 consecutive addresses (offsets 0x1E80 thru 0x1EBE) and 8 separate address blocks (once for each Channel Base Address) Data Bit R/W Function ------ --- ---------------------------------- 0 R/W Serial DAC CLOCK 1 R/W Serial DAC CS_B 2 R/W Serial DAC CS_B 3 R Serial DAC Data OUT 4..8 R Raw Sample RAM Sequencer State: bit 4: FROZEN bit 5: RESUMING bit 6: RECORDING bit 7: SUSPENDING bit 8: SENDING 9..10 R FPGA chip ID 00: Chip #0 01: Chip #1 10: Chip #2 11: Chip #3 11 R SCL Cable detect 0: Connected 1: Unplugged 12 R Generator Clock x 4 Locked 0: Not Locked 1: Locked 13 R Generator Clock x 8 Locked 0: Not Locked 1: Locked 14..15 R Spare (always 0) The signal for this register are defined in FilterD.vhd line 1799 but only lower 3 bits are defined "greg_C" other bits are most likely readonly, and defined as "glro_A" line 1789 Global Register D ----------------- Address: Card Base Address + Fpga Base Address + Channel Base Address + 0x1EC0 This register is visible at 32 consecutive addresses (offsets 0x1EC0 thru 0x1EFE) and 8 separate address blocks (once for each Channel Base Address) Data Bit R/W Function ------ --- ---------------------------------- 0 R/W Reserved (Geo. Section init ack.) 1 R/W Resume ADC raw sample recording 0: 1: 2 R/W Software L1 trigger accept 0: 1: 3..7 R/W Spare command bits 8 R/W Send new command to all ADF’s R/W When transition from 0 to 1 9 R/W Spare 10 R/W DCM Reset 0: 1: 11 R/W Invert serializer clock 0: 1: 12..13 R/W BX count serializer latency adjust 14..15 R Spare (always 0) The signal for this register are defined in FilterD.vhd line 1732 vhdl code comments calls bit 0..7 "Command to send to SCL Interface" Global Register E ----------------- Address: Card Base Address + Fpga Base Address + Channel Base Address + 0x1F00 This register is visible at 32 consecutive addresses (offsets 0x1F00 thru 0x1F3E) and 8 separate address blocks (once for each Channel Base Address) Data Bit R/W Function ------ --- ---------------------------------- 0..15 R Last L1 Accept Turn Count (maybe) defined as glro_B in FilterD.vhd line 1806 Global Register F ----------------- Address: Card Base Address + Fpga Base Address + Channel Base Address + 0x1F40 This register is visible at 32 consecutive addresses (offsets 0x1F40 thru 0x1F7E) and 8 separate address blocks (once for each Channel Base Address) Data Bit R/W Function ------ --- ---------------------------------- 0..15 R Last L1 Accept Bunch Crossing Count probably really: 0..7 R Last L1 Accept Bunch Crossing Count 8..15 R always 0 (maybe) defined as glro_C in FilterD.vhd line 1807