18-FEB-2004 Look at the VME_RSVBUS(8) signal. This is the bus line used to distribute the 7.59 MHz Beam Crossing clock. This signal comes from FPGA "F0" on an ADF card in the center of the crate and is distributed to the other 19 ADF cards on the backplane VME_RSVBUS(8) line. For this test this beam crossing clock signal comes from the on card 8 MHz WCLK_D8_F0 clock. All files in this section have names: vme_rsvbus8_**.tif File Conditions ---- ------------------------------------------------------------------ 00 Signal on the ADF card no bus loads ADF in slot 11 20 ns/div 01 Signal at slot 21 no bus loads ADF in slot 11 20 ns/div 02 Signal at slot 21 17 bus loads ADF in slot 11 20 ns/div 03 Signal at slot 07 17 bus loads ADF in slot 11 20 ns/div 04 Signal at slot 02 17 bus loads ADF in slot 11 20 ns/div 05 Signal on the ADF card 17 bus loads ADF in slot 11 20 ns/div 06 Signal at slot 10 17 bus loads ADF in slot 11 20 ns/div 07 Signal at slot 12 17 bus loads ADF in slot 11 20 ns/div 08 Signal at slot 16 17 bus loads ADF in slot 11 20 ns/div 09 Gnd pin at slot 16 17 bus loads ADF in slot 11 20 ns/div 10 Rising edge at slot 21 17 bus loads ADF in slot 11 10 ns/div 11 Falling edge at slot 21 17 bus loads ADF in slot 11 10 ns/div 12 Rising edge on ADF card 17 bus loads ADF in slot 11 10 ns/div 13 Falling edge on ADF card 17 bus loads ADF in slot 11 10 ns/div 14 Delay from rising edge on ADF card to slot 21 17 bus loads ADF in slot 11 10 ns/div In all the above files, expect for 09, the scope is looking at the VME_RSVBUS(8) signal. The ground lead on the scope probe was short and attached to a jig that picked up all 8 "normal" P1 grounds at the point where the signal was being measured or at the next slot. File 09 is just probing pin P1 Z28 to verify that the probe grounding setup was clean.