-- PROJECT: D0 Run IIb Trigger L1 Calorimeter upgrade
--
-- MODULE: RS232 to generic bus converter
--
-- ELEMENT: bus_control 
--
-- DESCRIPTION: drives the external bus according to command received over RS232
--
-- AUTHOR: J.Marquet marquet@efrei.fr
--
-- DATE AND HISTORY:
-- July 2004: created
-- September 2004: revised by D. Calvet
--------------------------------------------------------------------------------

--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

library work;
use work.utility_pkg.all;
use work.constant_package.all;
--------------------------------------------------------------------------------

--
-- Bus controller
--
entity bus_control is
	generic (
		ADDR_BUS_SIZE : integer := 12;
		DATA_BUS_SIZE : integer := 8
	);
	port (
		--
		-- General control signals
		--
		RESET    : in std_logic;                                  -- Asynch. Reset		
		CLK      : in std_logic;                                  -- Reference Clock
		
		--
		-- Signal from command line analysis block
		--
		NEW_LINE : in std_logic;                                  -- new command ready
		IS_W_CMD : in std_logic;                                  -- indicates a write command
		IS_I_CMD : in std_logic;                                  -- indicates an init command
		IS_Q_CMD : in std_logic;                                  -- line is quit command
		ERROR    : in std_logic;                                  -- syntax error in command
		ADDR_CMD : in std_logic_vector(ADDR_BUS_SIZE-1 downto 0); -- address supplied by command
		BYTE_SEL : in std_logic_vector(3 downto 0);               -- byte select supplied by command
		DATA_CMD : in std_logic_vector(DATA_BUS_SIZE-1 downto 0); -- data supplied by command
		
		--
		-- External bus signals
		--
		ADDR     : out std_logic_vector(ADDR_BUS_SIZE-1 downto 0); -- address bus
		DBE_B    : out std_logic_vector(3 downto 0);               -- byte selection
		WE       : out std_logic;                                  -- active high write enable
		CS_B     : out std_logic;                                  -- active low chip select
		DATA_OUT : out std_logic_vector(DATA_BUS_SIZE-1 downto 0); -- data bus output (write)
		DTACK_B  : in std_logic;                                   -- active low transfer acknowledge
		
		--
		-- Signals for command reply serializer block
		--
		NEW_CMD     : out std_logic;                                  -- new command available
		ERROR_H     : out std_logic                                   -- cycle had syntax error or timed-out
	);
end bus_control;

Architecture behavioral of bus_control is

signal time_out : std_logic_vector(3 downto 0); -- time out counter
signal cs_b_bis : std_logic;                    -- delay to assert CS_B after other bus signals
signal wait_for : std_logic;                    -- indicates that bus cycle is in progress

begin

-------------------------------------------------------------------------------------------
-- Control_pro affects values to various control signals.
-------------------------------------------------------------------------------------------
Control_pro: process (RESET, CLK)
begin
	if RESET = '1' then
		CS_B     <= '1';
		cs_b_bis <= '1';
		wait_for <= '0';
		ERROR_H  <= '0';
		NEW_CMD  <= '0';
	elsif rising_edge(CLK)  then
		CS_B     <= cs_b_bis;
		if NEW_LINE = '1' then 
			ERROR_H <= ERROR;
			NEW_CMD <= IS_I_CMD or IS_Q_CMD or ERROR;
			if IS_I_CMD = '0' and IS_Q_CMD = '0' and ERROR = '0' then 
				cs_b_bis <= '0';
				wait_for <= '1';
			end if;
		else
			NEW_CMD <= '0';
		end if; 
		if wait_for = '1' then
			if DTACK_B = '0'  then
				cs_b_bis <= '1';
				wait_for <= '0';
				ERROR_H  <= '0';
				NEW_CMD  <= '1';
			else
				if time_out = "1111"  then
					cs_b_bis <= '1';
					ERROR_H  <= '1';
					wait_for <= '0';
					NEW_CMD  <= '1';
				end if;
			end if;
		end if;	
	end if; 
end process Control_pro; 

----------------------------------------------------------------------------------------
-- Bus_out process affects values to external busses when a complete command line 
-- has been received without error.
----------------------------------------------------------------------------------------
bus_out: process (RESET, CLK)
begin
	if RESET = '1' then
		ADDR     <= (others => '0');
		DBE_B    <= (others => '1');
		DATA_OUT <= (others => '0');
		WE       <= '0';
	elsif rising_edge(CLK) then
		if NEW_LINE = '1' and IS_I_CMD = '0' and IS_Q_CMD = '0' and ERROR = '0' then
			ADDR     <= ADDR_CMD;
			DATA_OUT <= DATA_CMD;
			DBE_B    <= BYTE_SEL;
			WE       <= IS_W_CMD;
		end if;
	end if;
end process bus_out;

----------------------------------------------------------------------------------------
-- Time_out_pro process is used to detect if a transaction on the external bus is not
-- acknowledged. In such case, an error character will be generated by the next block.
----------------------------------------------------------------------------------------
Time_out_pro: process (RESET, CLK)
begin
	if RESET = '1' then 
		time_out <= "0000";
	elsif rising_edge(CLK)  then
		if cs_b_bis = '1' then
			time_out <= "0000";
		else
			time_out <= time_out + 1;
		end if;
	end if;
end process Time_out_pro;

end behavioral;