-- PROJECT: D0 Run IIb Trigger L1 Calorimeter upgrade -- -- MODULE: Channel Link Receiver Test Card -- -- ELEMENT: ChalinkR_FPGA -- -- DESCRIPTION: Top level component for the Channel Link -- Receiver Tester. This is designed to fit in a Virtex II -- evaluation kit (Memec Design) that has a XC2V1000 FG256 -- chip on it. A custom mezzanine card equipped with a 48-bit -- Channel Link deserializer is plugged ontop of the kit. -- The ChalinkR_FPGA component adds all the I/O pads to the -- ChalinkR component. See ChalinkR.vhd for details. -- -- AUTHOR: D. Calvet calvet@hep.saclay.cea.fr -- -- DATE AND HISTORY: -- June 2003 : created -- April 2004 : added some synchronous logic to delay the falling edge -- of CS_B. The problem comes when using a digital I/O card to generate -- the control signals that drive the bus interface. With National -- Instruments PCIDIO96 board, it is not possible to modify 1 bit on -- an output port without causing glitches on the other ones. For -- example, when asserting WE low, then asserting CS_B low, a 4 ns glitch -- on WE 16 ns after the falling edge on CS_B was seen with a logic analyzer. -- This is sufficient to corrupt the content of the location being read -- with random data. This "feature" probably comes from the structure of -- the 8255 PIO. The datasheet says that on port C, individual bit can -- be set/reset without affecting the state of other bits; but it does -- not say anything on port A and B (the tester is designed so that we -- use lines on port A for WE and CS_B lines). It is possible that glitch-free -- operations on output ports A and B cannot be guaranteed. To solve the -- problem, we add some logic to de-glitch WE -- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.all; library unisim; use unisim.all; -------------------------------------------------------------------------------- ENTITY ChalinkR_FPGA IS port ( ----------------------------------------------------------------------- -- -- Miscellaneous signals -- RESET : in std_logic; -- Register RESET ----------------------------------------------------------------------- ----------------------------------------------------------------------- -- -- LED indicators -- LED_USER : out std_logic; -- LED indicator ----------------------------------------------------------------------- ----------------------------------------------------------------------- -- -- Bus interface signals -- WE : in std_logic; -- Write Enable CS_B : in std_logic; -- Chip Select active low ADDR : in std_logic_vector(11 downto 0); -- Address bus DATA : inout std_logic_vector(7 downto 0); -- Data bus WCLK : in std_logic; -- Write Clock DTACK_B : out std_logic; -- Data acknowledge active low ----------------------------------------------------------------------- ----------------------------------------------------------------------- -- -- Clock signals -- CLK_BC_PLL : out std_logic; -- BC clock ouptut for board level PLL CLK_BC_OUT : out std_logic; -- BC clock ouptut for board level distribution CLK_BC_IN : in std_logic; -- BC clock input from board level distribution CLK_BC4X_IN : in std_logic; -- BCX4 clock input from board level distribution ----------------------------------------------------------------------- ----------------------------------------------------------------------- -- -- Channel Link Deserializer interface signals -- RX_CLK : in std_logic; -- Received clock RX_DATA : in std_logic_vector(35 downto 0); -- Received data ----------------------------------------------------------------------- ----------------------------------------------------------------------- -- -- SCL interface cable signals -- ----------------------------------------------------------------------- SCLIF_CLK7_P : in std_logic; -- Bunch crossing clock input LVDS Positive SCLIF_CLK7_N : in std_logic; -- Bunch crossing clock input LVDS Negative SCLIF_BUSY_B_OUT_P : out std_logic; -- Busy signal (active low) upstream ADF -> SCL receiver LVDS Positive SCLIF_BUSY_B_OUT_N : out std_logic; -- Busy signal (active low) upstream ADF -> SCL receiver LVDS Negative SCLIF_CMDU_OUT_P : out std_logic; -- Command upstream ADF's -> SCL receiver LVDS Positive SCLIF_CMDU_OUT_N : out std_logic; -- Command upstream ADF's -> SCL receiver LVDS Negative SCLIF_CMDD_IN_P : in std_logic; -- Command downstream ADF's <- SCL receiver LVDS Positive SCLIF_CMDD_IN_N : in std_logic; -- Command downstream ADF's <- SCL receiver LVDS Negative SCLIF_ERR_B_OUT_P : out std_logic; -- Error signal (active low) upstream ADF -> SCL receiver LVDS Positive SCLIF_ERR_B_OUT_N : out std_logic; -- Error signal (active low) upstream ADF -> SCL receiver LVDS Negative SCLIF_STRIG_B_P : out std_logic; -- Self trigger ADF -> SCLIF LVDS Positive SCLIF_STRIG_B_N : out std_logic; -- Self trigger ADF -> SCLIF LVDS Negative SCLIF_SPARE_P : in std_logic; -- Spare wire LVDS Positive SCLIF_SPARE_N : in std_logic; -- Spare wire LVDS Negative ------------------------------------------------------------------------- -- Debug Port -- DBG_IN : in std_logic_vector(0 downto 0); -- Debug port Input pads DBG_OUT : out std_logic_vector(1 downto 0); -- Debug port Output pads ------------------------------------------------------------------------- ----------------------------------------------------------------------- -- -- Pins specific to debug implementation -- ----------------------------------------------------------------------- SCL_CLK : in std_logic -- (100 MHz clock from Evaluation Kit) ); END ChalinkR_FPGA; architecture structure of ChalinkR_FPGA is -- -- Channel Link Tester Logic -- component ChalinkR port ( ----------------------------------------------------------------------- -- -- Miscellaneous signals -- RESET : in std_logic; -- Register RESET ----------------------------------------------------------------------- ----------------------------------------------------------------------- -- -- LED indicators -- LED_USER : out std_logic; -- LED indicator ----------------------------------------------------------------------- ----------------------------------------------------------------------- -- -- Bus interface signals -- WE : in std_logic; -- Write Enable CS_B : in std_logic; -- Chip Select active low ADDR : in std_logic_vector(11 downto 0); -- Address bus DATA_IN : in std_logic_vector(7 downto 0); -- Data bus Input DATA_OUT : out std_logic_vector(7 downto 0); -- Data bus Output DATA_Z : out std_logic; -- Control High Z Data Bus WCLK : in std_logic; -- Write Clock DTACK_B : out std_logic; -- Data acknowledge active low ----------------------------------------------------------------------- ----------------------------------------------------------------------- -- -- Clock signals -- CLK_BC_PLL : out std_logic; -- BC clock ouptut for board level PLL CLK_BC_OUT : out std_logic; -- BC clock ouptut for board level distribution CLK_BC_IN : in std_logic; -- BC clock input from board level distribution CLK_BC4X_IN : in std_logic; -- BCX4 clock input from board level distribution ----------------------------------------------------------------------- ----------------------------------------------------------------------- -- -- Channel Link Deserializer interface signals -- RX_CLK : in std_logic; -- Received clock RX_DATA : in std_logic_vector(35 downto 0); -- Received data ----------------------------------------------------------------------- ----------------------------------------------------------------------- -- -- SCL interface cable signals -- ----------------------------------------------------------------------- SCLIF_CLK7 : in std_logic; -- Bunch crossing clock input SCLIF_BUSY_B_OUT : out std_logic; -- Busy signal (active low) upstream ADF -> SCL receiver SCLIF_CMDU_OUT : out std_logic; -- Command upstream ADF's -> SCL receiver SCLIF_CMDD_IN : in std_logic; -- Command downstream ADF's <- SCL receiver SCLIF_ERR_B_OUT : out std_logic; -- Error signal (active low) upstream ADF -> SCL receiver SCLIF_STRIG_B : out std_logic; -- Self trigger ADF -> SCLIF SCLIF_SPARE : in std_logic; -- Spare wire ------------------------------------------------------------------------- -- Debug Port -- DBG_IN : in std_logic_vector(0 downto 0); -- Debug port Input pads DBG_OUT : out std_logic_vector(1 downto 0); -- Debug port Output pads ------------------------------------------------------------------------- ----------------------------------------------------------------------- -- -- Pins specific to debug implementation -- ----------------------------------------------------------------------- SCL_CLK : in std_logic -- (100 MHz clock from Evaluation Kit) ); END component; -- -- Input buffer LVDS 0.33V extended -- component IBUFDS_LVDSEXT_33 port ( I : in std_logic; IB : in std_logic; O : out std_logic ); end component; -- -- Clock input buffer LVDS 0.33V extended -- component IBUFGDS_LVDSEXT_33 port ( I : in std_logic; IB : in std_logic; O : out std_logic ); end component; -- -- Output buffer LVDS 0.33V extended -- component OBUFDS_LVDSEXT_33 port ( I : in std_logic; O : out std_logic; OB : out std_logic ); end component; -- -- Input buffer LVCMOS 3.3V -- component IBUF_LVCMOS33 port ( I : in std_logic; O : out std_logic ); end component; -- -- Clock Input buffer LVCMOS 3.3V -- component IBUFG_LVCMOS33 port ( I : in std_logic; O : out std_logic ); end component; -- -- Output buffer LVCMOS 3.3V slow 4 mA drive capability -- component OBUF_LVCMOS33_S_4 port ( I : in std_logic; O : out std_logic ); end component; -- -- Output buffer LVCMOS 3.3V slow 24 mA drive capability -- component OBUF_LVCMOS33_S_24 port ( I : in std_logic; O : out std_logic ); end component; -- -- Output buffer LVCMOS 3.3V fast 4 mA drive capability -- component OBUF_LVCMOS33_F_4 port ( I : in std_logic; O : out std_logic ); end component; -- -- Output buffer LVCMOS 3.3V fast 16 mA drive capability -- component OBUF_LVCMOS33_F_16 port ( I : in std_logic; O : out std_logic ); end component; -- -- Tristate Output buffer LVCMOS 3.3V fast 4 mA drive capability -- component OBUFT_LVCMOS33_F_4 port ( O : out std_logic; I : in std_logic; T : in std_logic ); end component; -- -- Tristate Output buffer LVCMOS 3.3V fast 16 mA drive capability -- component OBUFT_LVCMOS33_F_16 port ( O : out std_logic; I : in std_logic; T : in std_logic ); end component; -- -- Input/Output buffer LVCMOS 3.3V slow 2 mA drive capability -- component IOBUF_LVCMOS33_S_2 port ( O : out std_logic; IO : inout std_logic; I : in std_logic; T : in std_logic ); end component; -- -- Input/Output buffer LVCMOS 3.3V slow 12 mA drive capability -- component IOBUF_LVCMOS33_S_12 port ( O : out std_logic; IO : inout std_logic; I : in std_logic; T : in std_logic ); end component; -- -- Input/Output buffer LVCMOS 3.3V slow 24 mA drive capability -- component IOBUF_LVCMOS33_S_24 port ( O : out std_logic; IO : inout std_logic; I : in std_logic; T : in std_logic ); end component; ----------------------------------------------------------------------- -- -- Miscellaneous signals -- ----------------------------------------------------------------------- signal I_RESET : std_logic; -- Register RESET active HIGH signal RESET_A : std_logic; -- RESET active LOW because on board push button is active LOW ----------------------------------------------------------------------- ----------------------------------------------------------------------- -- -- LED indicators -- signal O_LED_USER : std_logic; ----------------------------------------------------------------------- ----------------------------------------------------------------------- -- -- Bus interface signals -- signal I_WE : std_logic; -- Write Enable signal WE_D1 : std_logic; -- Write Enable delayed 1 signal WE_D2 : std_logic; -- Write Enable delayed 1 signal WE_C : std_logic; -- Write Enable cleaned signal I_CS_B : std_logic; -- Chip Select active low signal I_ADDR : std_logic_vector(11 downto 0); -- Address bus signal I_DATA_IN : std_logic_vector(7 downto 0); -- data IN signal O_DATA_OUT : std_logic_vector(7 downto 0); -- data OUT signal O_DATA_Z : std_logic; -- data OUT tristate control signal I_WCLK : std_logic; -- Write Clock signal O_DTACK_B : std_logic; ----------------------------------------------------------------------- ----------------------------------------------------------------------- -- -- Clock signals -- signal O_CLK_BC_PLL : std_logic; -- BC clock ouptut for external PLL signal O_CLK_BC_OUT : std_logic; -- BC clock ouptut for board level buffering signal I_CLK_BC_IN : std_logic; -- BC clock input from board level distribution signal I_CLK_BC4X_IN : std_logic; -- BCX4 clock input from board level distribution ----------------------------------------------------------------------- ----------------------------------------------------------------------- -- -- Output Link interface signals -- signal I_RX_CLK : std_logic; -- Received clock signal II_RX_CLK : std_logic; -- Received clock signal I_RX_DATA : std_logic_vector(35 downto 0); -- Received data ----------------------------------------------------------------------- ----------------------------------------------------------------------- -- -- SCL interface cable and backplane bus interface signals -- ----------------------------------------------------------------------- signal I_SCLIF_CLK7 : std_logic; -- Bunch crossing clock input signal O_SCLIF_BUSY_B_OUT : std_logic; -- Busy signal upstream ADF -> SCL receiver signal O_SCLIF_CMDU_OUT : std_logic; -- Command upstream ADF's -> SCL receiver signal I_SCLIF_CMDD_IN : std_logic; -- Command downstream ADF's <- SCL receiver signal O_SCLIF_ERR_B_OUT : std_logic; signal O_SCLIF_STRIG_B : std_logic; signal I_SCLIF_SPARE : std_logic; ------------------------------------------------------------------------- -- Debug Port -- signal I_DBG_IN : std_logic_vector(0 downto 0); -- Input pads signal O_DBG_OUT : std_logic_vector(1 downto 0); -- Output pads ------------------------------------------------------------------------- ------------------------------------------------------------------------- -- Signal specific to debug implementation -- signal I_SCL_CLK : std_logic; -- SCL master clock received from input pad ------------------------------------------------------------------------- begin -- -- Channel Link Tester Logic -- Tester: ChalinkR port map ( ----------------------------------------------------------------------- -- -- Miscellaneous signals -- RESET => I_RESET, ----------------------------------------------------------------------- ----------------------------------------------------------------------- -- -- LED indicators -- LED_USER => O_LED_USER, ----------------------------------------------------------------------- ----------------------------------------------------------------------- -- -- Bus interface signals -- WE => WE_C, --I_WE, CS_B => I_CS_B, ADDR => I_ADDR, DATA_IN => I_DATA_IN, DATA_OUT => O_DATA_OUT, DATA_Z => O_DATA_Z, WCLK => I_WCLK, DTACK_B => O_DTACK_B, ----------------------------------------------------------------------- ----------------------------------------------------------------------- -- -- Clock signals -- CLK_BC_PLL => O_CLK_BC_PLL, CLK_BC_OUT => O_CLK_BC_OUT, CLK_BC_IN => I_CLK_BC_IN, CLK_BC4X_IN => I_CLK_BC4X_IN, ----------------------------------------------------------------------- ----------------------------------------------------------------------- -- -- Channel Link Deserializer interface signals -- RX_CLK => I_RX_CLK, RX_DATA => I_RX_DATA, ----------------------------------------------------------------------- ----------------------------------------------------------------------- -- -- SCL interface cable signals -- ----------------------------------------------------------------------- SCLIF_CLK7 => I_SCLIF_CLK7, SCLIF_BUSY_B_OUT => O_SCLIF_BUSY_B_OUT, SCLIF_CMDU_OUT => O_SCLIF_CMDU_OUT, SCLIF_CMDD_IN => I_SCLIF_CMDD_IN, SCLIF_ERR_B_OUT => O_SCLIF_ERR_B_OUT, SCLIF_STRIG_B => O_SCLIF_STRIG_B, SCLIF_SPARE => I_SCLIF_SPARE, ------------------------------------------------------------------------- -- Debug Port -- DBG_IN => I_DBG_IN, DBG_OUT => O_DBG_OUT, ------------------------------------------------------------------------- ----------------------------------------------------------------------- -- -- Pins specific to debug implementation -- ----------------------------------------------------------------------- SCL_CLK => I_SCL_CLK ); ----------------------------------------------------------------------- -- -- Miscellaneous signals -- ----------------------------------------------------------------------- -- -- LVCMOS 3.3 V input pad -- U_CRESET: IBUF_LVCMOS33 port map( I => RESET, O => RESET_A ); I_RESET <= not RESET_A; -- RESET_A is active LOW because on board push button is active LOW ----------------------------------------------------------------------- ----------------------------------------------------------------------- -- -- LED indicators -- ----------------------------------------------------------------------- -- -- A LVCMOS 3.3 V output pad with 24mA capability for LED User -- U_LED_USER: OBUF_LVCMOS33_S_24 port map( I => O_LED_USER, O => LED_USER ); ----------------------------------------------------------------------- ----------------------------------------------------------------------- -- -- Bus interface signals -- ----------------------------------------------------------------------- -- -- A series of LVCMOS 3.3 V input pads -- U_WE: IBUF_LVCMOS33 port map( I => WE, O => I_WE ); U_CS_B: IBUF_LVCMOS33 port map( I => CS_B, O => I_CS_B ); -- -- Some logic to de-glitch WE -- Clean_WE : process(I_RESET, I_WCLK) begin if I_RESET = '1' then WE_D1 <= '0'; WE_D2 <= '0'; elsif I_WCLK'event and I_WCLK = '0' then WE_D1 <= I_WE; WE_D2 <= WE_D1; end if; end process; WE_C <= I_WE and WE_D1 and WE_D2; U_ADDR: for i in 11 downto 0 generate UU_ADDR: IBUF_LVCMOS33 port map( I => ADDR(i), O => I_ADDR(i) ); end generate; -- -- Bi-directional 3 state lvcmos 3.3V buffers -- U_DATA: for i in 7 downto 0 generate UU_DATA: IOBUF_LVCMOS33_S_12 port map ( O => I_DATA_IN(i), IO => DATA(i), I => O_DATA_OUT(i), T => O_DATA_Z ); end generate; -- -- A Clock Input buffer lvcmos 3.3V for interface write clock -- U_WCLK: IBUFG_LVCMOS33 port map( I => WCLK, O => I_WCLK ); -- -- A lvcmos 3.3V tristate buffer to drive DTACK_B -- U_DTACK_B: OBUFT_LVCMOS33_F_16 port map( I => O_DTACK_B, O => DTACK_B, T => O_DTACK_B ); ----------------------------------------------------------------------- ----------------------------------------------------------------------- -- -- External Clocks signals -- ----------------------------------------------------------------------- -- -- A Clock Input buffer lvcmos 3.3V for CLK BC X 4 -- -- U_CLK_BCX4_IN: IBUFG_LVCMOS33 port map( I => CLK_BC4X_IN, O => I_CLK_BC4X_IN ); -- -- A Clock Input buffer lvcmos 3.3V for CLK BC -- -- U_CLK_BC_IN: IBUFG_LVCMOS33 port map( I => CLK_BC_IN, O => I_CLK_BC_IN ); -- -- A LVCMOS 3.3 V output pads for CLK_BC_PLL -- U_CLK_BC_PLL: OBUF_LVCMOS33_F_16 port map( I => O_CLK_BC_PLL, O => CLK_BC_PLL ); -- -- A LVCMOS 3.3 V output pads for CLK_BC_OUT -- U_CLK_BC_OUT: OBUF_LVCMOS33_F_16 port map( I => O_CLK_BC_OUT, O => CLK_BC_OUT ); ----------------------------------------------------------------------- ----------------------------------------------------------------------- -- -- Channel Link interface signals -- ----------------------------------------------------------------------- -- -- A Clock Input buffer lvcmos 3.3V for received CLK -- -- U_RX_CLK: IBUFG_LVCMOS33 port map( I => RX_CLK, O => II_RX_CLK ); I_RX_CLK <= II_RX_CLK; -- -- A series of LVCMOS 3.3 V input pads for received data -- U_RX_DATA: for i in 35 downto 0 generate UU_RX_DATA : IBUF_LVCMOS33 port map( I => RX_DATA(i), O => I_RX_DATA(i) ); end generate; ----------------------------------------------------------------------- ----------------------------------------------------------------------- -- -- SCL interface cable and backplane bus interface signals -- ----------------------------------------------------------------------- -- -- A Clock Input buffer LVDS .33V extended for Beam Crossing clock (comes from cable) -- U_CLK7: IBUFDS_LVDSEXT_33 port map( I => SCLIF_CLK7_P, IB => SCLIF_CLK7_N, O => I_SCLIF_CLK7 ); -- -- An output buffer LVDS .33V extended for BUSY (goes to cable) -- U_SCLIF_BUSY_B_OUT: OBUFDS_LVDSEXT_33 port map( I => O_SCLIF_BUSY_B_OUT, O => SCLIF_BUSY_B_OUT_P, OB => SCLIF_BUSY_B_OUT_N ); -- -- An output buffer LVDS .33V extended for CMD upstream (goes to cable) -- U_SCLIF_CMDU_OUT: OBUFDS_LVDSEXT_33 port map( I => O_SCLIF_CMDU_OUT, O => SCLIF_CMDU_OUT_P, OB => SCLIF_CMDU_OUT_N ); -- -- An Input buffer LVDS .33V extended for CMD downstream (comes from cable) -- U_SCLIF_CMDD_IN: IBUFDS_LVDSEXT_33 port map( I => SCLIF_CMDD_IN_P, IB => SCLIF_CMDD_IN_N, O => I_SCLIF_CMDD_IN ); -- -- An output buffer LVDS .33V extended for SCLIF_ERR_B_OUT (goes to cable) -- U_SCLIF_ERR_B_OUT: OBUFDS_LVDSEXT_33 port map( I => O_SCLIF_ERR_B_OUT, O => SCLIF_ERR_B_OUT_P, OB => SCLIF_ERR_B_OUT_N ); -- -- An output buffer LVDS .33V extended for local self trigger (goes to cable) -- U_SCLIF_STRIG_B: OBUFDS_LVDSEXT_33 port map( I => O_SCLIF_STRIG_B, O => SCLIF_STRIG_B_P, OB => SCLIF_STRIG_B_N ); -- -- An Input buffer LVDS .33V extended for spare signal (comes from cable) -- U_SCLIF_SPARE: IBUFDS_LVDSEXT_33 port map( I => SCLIF_SPARE_P, IB => SCLIF_SPARE_N, O => I_SCLIF_SPARE ); ------------------------------------------------------------------------- -- Debug Port -- -- -- A series of LVCMOS 3.3 V input pads for test -- U_DBG_IN: for i in 0 downto 0 generate UU_DBG_IN : IBUF_LVCMOS33 port map( I => DBG_IN(i), O => I_DBG_IN(i) ); end generate; -- -- A series of LVCMOS 3.3 V output pads for logic analyzer -- U_DBG_OUT: for i in 1 downto 0 generate UU_DBG_OUT: OBUF_LVCMOS33_F_16 port map( I => O_DBG_OUT(i), O => DBG_OUT(i) ); end generate; ------------------------------------------------------------------------- ------------------------------------------------------------------------- -- Pads for signal specific to debug implementation -- -- -- A Clock Input buffer lvcmos 3.3V for SCL CLK BC -- -- U_SCL_CLK: IBUFG_LVCMOS33 port map( I => SCL_CLK, O => I_SCL_CLK ); end;