-- PROJECT: D0 Run IIb Trigger L1 Calorimeter upgrade -- -- MODULE: Channel Link Receiver Test Card -- -- ELEMENT: ChalinkR_RS232 -- -- DESCRIPTION: ChalinkR interface to bus2rs232 -- -- -- AUTHOR: D. Calvet calvet@hep.saclay.cea.fr and J.Marquet marquet@efrei.fr -- -- DATE AND HISTORY: -- -- June 2003 : created -- March 2004: added logic to capture the address where data is being written -- upon a trigger. This helps to locate the word that caused a trigger. -- March 2004: Permanently Enable port B of RAMs. These were -- changed dynamically by the address decoding logic, but set to the wrong state. -- April 2004: added logic to generate local signals for FRAME and BX_COUNT -- bit pattern comparison is now be made on the 36-bit received -- -- April 2004: fixed De-multiplexing for we_ram signal: this was determined -- by the state of some address lines instead of the PAGE selection bits. -- Note that only data in page 0 to 3 can be written. Page 4 is the 9th bit -- of the 4 block RAMS; it cannot be written independently of the 8 other bits. -- -- July 2004: bus2rs232 is added to Chalinkr to make ChalinR_RS232. -- This implements the control of the Channel link Receiver Test Card -- via a serial RS232 connection. -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_ARITH.all; use IEEE.STD_LOGIC_UNSIGNED.all; library unisim; use unisim.all; library work; use work.utility_pkg.all; -------------------------------------------------------------------------------- -- -- Channel Link Tester Logic with control via RS232 -- ENTITY ChalinkR_RS232 is generic ( ADDR_BUS_SIZE : integer := 12; DATA_BUS_SIZE : integer := 8; BAUD_RATE : integer := 307200 ); port ( ----------------------------------------------------------------------- -- -- Miscellaneous signals -- RESET : in std_logic; -- Register RESET WCLK : in std_logic; -- Write Clock ----------------------------------------------------------------------- ----------------------------------------------------------------------- -- -- LED indicators -- LED_USER : out std_logic; -- LED indicator ----------------------------------------------------------------------- ----------------------------------------------------------------------- -- -- RS232 interface -- TX_OUT : out std_logic; -- TX serial output RX_IN : in std_logic; -- RX serial input ----------------------------------------------------------------------- ----------------------------------------------------------------------- -- -- Clock signals -- CLK_BC_PLL : out std_logic; -- BC clock ouptut for board level PLL CLK_BC_OUT : out std_logic; -- BC clock ouptut for board level distribution CLK_BC_IN : in std_logic; -- BC clock input from board level distribution CLK_BC4X_IN : in std_logic; -- BCX4 clock input from board level distribution ----------------------------------------------------------------------- ----------------------------------------------------------------------- -- -- Channel Link Deserializer interface signals -- RX_CLK : in std_logic; -- Received clock RX_DATA : in std_logic_vector(35 downto 0); -- Received data ----------------------------------------------------------------------- ----------------------------------------------------------------------- -- -- SCL interface cable signals -- ----------------------------------------------------------------------- SCLIF_CLK7 : in std_logic; -- Bunch crossing clock input SCLIF_BUSY_B_OUT : out std_logic; -- Busy signal (active low) upstream ADF -> SCL receiver SCLIF_CMDU_OUT : out std_logic; -- Command upstream ADF's -> SCL receiver SCLIF_CMDD_IN : in std_logic; -- Command downstream ADF's <- SCL receiver SCLIF_ERR_B_OUT : out std_logic; -- Error signal (active low) upstream ADF -> SCL receiver SCLIF_STRIG_B : out std_logic; -- Self trigger ADF -> SCLIF SCLIF_SPARE : in std_logic; -- Spare wire ------------------------------------------------------------------------- -- Debug Port -- DBG_IN : in std_logic_vector(0 downto 0); -- Debug port Input pads DBG_OUT : out std_logic_vector(1 downto 0); -- Debug port Output pads ------------------------------------------------------------------------- ----------------------------------------------------------------------- -- -- Pins specific to debug implementation -- ----------------------------------------------------------------------- SCL_CLK : in std_logic -- (100 MHz clock from Evaluation Kit) ); end ChalinkR_RS232; architecture structure of ChalinkR_RS232 is -- -- Channel Link Tester Logic -- component ChalinkR port ( ----------------------------------------------------------------------- -- -- Miscellaneous signals -- RESET : in std_logic; -- Register RESET ----------------------------------------------------------------------- ----------------------------------------------------------------------- -- -- LED indicators -- LED_USER : out std_logic; -- LED indicator ----------------------------------------------------------------------- ----------------------------------------------------------------------- -- -- Bus interface signals -- WE : in std_logic; -- Write Enable CS_B : in std_logic; -- Chip Select active low ADDR : in std_logic_vector(11 downto 0); -- Address bus DATA_IN : in std_logic_vector(7 downto 0); -- Data bus Input DATA_OUT : out std_logic_vector(7 downto 0); -- Data bus Output DATA_Z : out std_logic; -- Control High Z Data Bus WCLK : in std_logic; -- Write Clock DTACK_B : out std_logic; -- Data acknowledge active low ----------------------------------------------------------------------- ----------------------------------------------------------------------- -- -- Clock signals -- CLK_BC_PLL : out std_logic; -- BC clock ouptut for board level PLL CLK_BC_OUT : out std_logic; -- BC clock ouptut for board level distribution CLK_BC_IN : in std_logic; -- BC clock input from board level distribution CLK_BC4X_IN : in std_logic; -- BCX4 clock input from board level distribution ----------------------------------------------------------------------- ----------------------------------------------------------------------- -- -- Channel Link Deserializer interface signals -- RX_CLK : in std_logic; -- Received clock RX_DATA : in std_logic_vector(35 downto 0); -- Received data ----------------------------------------------------------------------- ----------------------------------------------------------------------- -- -- SCL interface cable signals -- ----------------------------------------------------------------------- SCLIF_CLK7 : in std_logic; -- Bunch crossing clock input SCLIF_BUSY_B_OUT : out std_logic; -- Busy signal (active low) upstream ADF -> SCL receiver SCLIF_CMDU_OUT : out std_logic; -- Command upstream ADF's -> SCL receiver SCLIF_CMDD_IN : in std_logic; -- Command downstream ADF's <- SCL receiver SCLIF_ERR_B_OUT : out std_logic; -- Error signal (active low) upstream ADF -> SCL receiver SCLIF_STRIG_B : out std_logic; -- Self trigger ADF -> SCLIF SCLIF_SPARE : in std_logic; -- Spare wire ------------------------------------------------------------------------- -- Debug Port -- DBG_IN : in std_logic_vector(0 downto 0); -- Debug port Input pads DBG_OUT : out std_logic_vector(1 downto 0); -- Debug port Output pads ------------------------------------------------------------------------- ----------------------------------------------------------------------- -- -- Pins specific to debug implementation -- ----------------------------------------------------------------------- SCL_CLK : in std_logic -- (100 MHz clock from Evaluation Kit) ); end component; -- -- RS 232 to generic bus converter -- component bus2rs232 generic ( ADDR_BUS_SIZE : integer := 12; DATA_BUS_SIZE : integer := 8; BAUD_RATE : integer := 307200 ); port ( -- -- General control signals -- RESET : in std_logic; -- Asynch. Reset CLK : in std_logic; -- Reference Clock -- -- RS232 signals -- RX_IN : in std_logic; TX_OUT : out std_logic; -- -- External bus signals -- ADDR : out std_logic_vector(ADDR_BUS_SIZE-1 downto 0); -- address bus DBE_B : out std_logic_vector(3 downto 0); -- byte selection WE : out std_logic; -- active high write enable CS_B : out std_logic; -- active low chip select DATA_OUT : out std_logic_vector(DATA_BUS_SIZE-1 downto 0); -- data bus output (write) DATA_IN : in std_logic_vector(DATA_BUS_SIZE-1 downto 0); -- data bus input (read) DTACK_B : in std_logic -- active low transfer acknowledge ); end component; -- -- Bus interface signals -- signal we : std_logic; signal cs_b : std_logic; signal addr : std_logic_vector(ADDR_BUS_SIZE-1 downto 0); signal dbe_b : std_logic_vector(3 downto 0); signal data_in : std_logic_vector(DATA_BUS_SIZE-1 downto 0); signal data_out : std_logic_vector(DATA_BUS_SIZE-1 downto 0); signal data_z : std_logic; signal dtack_b : std_logic; begin -- -- RS 232 to generic bus converter -- Bus_Converter: bus2rs232 generic map ( ADDR_BUS_SIZE, DATA_BUS_SIZE, BAUD_RATE ) port map ( -- -- General control signals -- RESET => RESET, CLK => WCLK, -- -- RS232 signals -- RX_IN => RX_IN, TX_OUT => TX_OUT, -- -- External bus signals -- ADDR => addr, DBE_B => dbe_b, WE => we, CS_B => cs_b, DATA_OUT => data_out, DATA_IN => data_in, DTACK_B => dtack_b ); -- -- Channel Link Tester Logic -- CL_Tester: ChalinkR port map ( ----------------------------------------------------------------------- -- -- Miscellaneous signals -- RESET => RESET, ----------------------------------------------------------------------- ----------------------------------------------------------------------- -- -- LED indicators -- LED_USER => LED_USER, ----------------------------------------------------------------------- ----------------------------------------------------------------------- -- -- Bus interface signals -- WE => we, CS_B => cs_b, ADDR => addr, DATA_IN => data_out, -- output of bus interface is input for this block DATA_OUT => data_in, -- input of bus interface is output of this block DATA_Z => data_z, WCLK => WCLK, DTACK_B => dtack_b, ----------------------------------------------------------------------- ----------------------------------------------------------------------- -- -- Clock signals -- CLK_BC_PLL => CLK_BC_PLL, CLK_BC_OUT => CLK_BC_OUT, CLK_BC_IN => CLK_BC_IN, CLK_BC4X_IN => CLK_BC4X_IN, ----------------------------------------------------------------------- ----------------------------------------------------------------------- -- -- Channel Link Deserializer interface signals -- RX_CLK => RX_CLK, RX_DATA => RX_DATA, ----------------------------------------------------------------------- ----------------------------------------------------------------------- -- -- SCL interface cable signals -- ----------------------------------------------------------------------- SCLIF_CLK7 => SCLIF_CLK7, SCLIF_BUSY_B_OUT => SCLIF_BUSY_B_OUT, SCLIF_CMDU_OUT => SCLIF_CMDU_OUT, SCLIF_CMDD_IN => SCLIF_CMDD_IN, SCLIF_ERR_B_OUT => SCLIF_ERR_B_OUT, SCLIF_STRIG_B => SCLIF_STRIG_B, SCLIF_SPARE => SCLIF_SPARE, ----------------------------------------------------------------------- ------------------------------------------------------------------------- -- Debug Port -- DBG_IN => DBG_IN, DBG_OUT => DBG_OUT, ------------------------------------------------------------------------- ----------------------------------------------------------------------- -- -- Pins specific to debug implementation -- ----------------------------------------------------------------------- SCL_CLK => SCL_CLK ); end;