-- PROJECT: D0 Run IIb Trigger L1 Calorimeter upgrade
--
-- MODULE: Channel Link Receiver Test Card
--
-- ELEMENT: lfsr
--
-- DESCRIPTION: LFSR similar to that implemented in the ADF card.
-- This version has a 16 bit seed split in 2 8-bit words to ease
-- integration with an 8-bit wide data bus. 
--
-- AUTHOR: D. Calvet calvet@hep.saclay.cea.fr
--
-- DATE AND HISTORY:
--  June 2003 : created
--
--
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library ieee;
use ieee.std_logic_1164.all;
--------------------------------------------------------------------------------

--
-- 16-bit LFSR
--
entity lfsr is
	port (
		RESET     : in std_logic; -- Asynchronous RESET
		CLK       : in std_logic; -- Clock
		SE        : in std_logic; -- Synchronous Shift Enable
		LOAD_L    : in std_logic; -- Load Lower byte of Seed
		LOAD_H    : in std_logic; -- Load Higher byte of Seed
		SEED      : in std_logic_vector(15 downto 0); -- Seed
		Q         : out std_logic_vector(15 downto 0) -- Output
		);
end lfsr;


architecture behavior of lfsr is

	--
	-- N bit parallel load and serial IN, parallel OUT shift right register
	-- with asynchronous RESET and synchronous shift enable
	--
	component sr_pl_po
	generic(
		LENG : INTEGER := 8
	);
	port (
		RESET  : in std_logic; -- Asynchronous RESET
		SE     : in std_logic; -- Shift Enable
		CLK    : in std_logic; -- Clock
		LOAD   : in std_logic; -- Parallel Load
		SIN    : in std_logic; -- Serial Input
		DATA   : in std_logic_vector((LENG-1) downto 0); -- Input Data
		Q      : out std_logic_vector((LENG-1) downto 0) -- Output
	);
	end component;
	
	signal lfsr_sin  : std_logic;
	signal lfsr_sta  : std_logic_vector(15 downto 0);
	
	signal gnd : std_logic;
	
begin

	--
	-- A Pseudo-random Generator made with a 16 bit Linear Feedback Shift Register
	-- composed of 2 8 bit registers
	LFSR_low : sr_pl_po
	generic map (8)
	port map (
		RESET => RESET,
		SE    => SE,
		CLK   => CLK,
		LOAD  => LOAD_L,
		SIN   => lfsr_sta(8),
		DATA  => SEED(7 downto 0),
		Q     => lfsr_sta(7 downto 0)
	);
	
	LFSR_high : sr_pl_po
	generic map (8)
	port map (
		RESET => RESET,
		SE    => SE,
		CLK   => CLK,
		LOAD  => LOAD_H,
		SIN   => lfsr_sin,
		DATA  => SEED(15 downto 8),
		Q     => lfsr_sta(15 downto 8)
	);
		
	LFSR_Loopback : process(lfsr_sta(0), lfsr_sta(1), lfsr_sta(3), lfsr_sta(12))
	begin
		lfsr_sin <= not(lfsr_sta(0) xor lfsr_sta(1) xor lfsr_sta(3) xor lfsr_sta(12)) ;	
	end process;
	
	Q <= lfsr_sta;
	

			
end behavior;