--------------------------------------------------------------------------------
--
-- PROJECT: D0 Run IIb Trigger L1 Calorimeter upgrade
--
-- MODULE: SRLC64E_MACRO_INIT
--
-- ELEMENT: 
--
-- DESCRIPTION: Shift Register macro
--		64 bits Shift Register cascadable with Clock Enable
--		Use template "SHIFT_REGISTER_C_16.vhd"
-- 
-- AUTHOR: D. Calvet calvet@hep.saclay.cea.fr
--
-- DATE AND HISTORY:
-- Date:	JLB / 05-21-2000 - XILINX
--
-- Modification: Denis Calvet / 02-05-2002 - Added generic to set
-- the initial content of the shift register
----------------------------------------------------------------------------------

----------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
--
-- pragma translate_off
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
-- pragma translate_on
--
----------------------------------------------------------------------------------

entity SRLC64E_MACRO is
-- pragma translate_off
  generic (
-- Shift Register initialization ("0" by default) for functional simulation:
        INIT64 : bit_vector(63 downto 0) := X"0000000000000000"
	);
-- pragma translate_on
  port (
  	D    : in std_logic;
        CE   : in std_logic; 
        CLK  : in std_logic;
        A0   : in std_logic;
        A1   : in std_logic;
        A2   : in std_logic;
        A3   : in std_logic;
        A4   : in std_logic;
        A5   : in std_logic;
        Q    : out std_logic;
        Q63  : out std_logic 
       ); 
end SRLC64E_MACRO;
--
architecture SRLC64E_MACRO_arch of SRLC64E_MACRO is
--
-- Components Declarations:
component SRLC16E 
-- pragma translate_off
  generic (
-- Shift Register initialization ("0" by default) for functional simulation:
        INIT : bit_vector := X"0000"
	);
-- pragma translate_on
  port (
  	D    : in std_logic;
        CE   : in std_logic;
        CLK  : in std_logic;
        A0   : in std_logic;
        A1   : in std_logic;
        A2   : in std_logic;
        A3   : in std_logic;
        Q    : out std_logic;
        Q15  : out std_logic
	); 
end component;
--
component MUXF5_L
  port (
  	I0   : in std_logic;
  	I1   : in std_logic;
  	S    : in std_logic;
  	LO    : out std_logic
  	);
end component;
--
component MUXF6
  port (
  	I0   : in std_logic;
  	I1   : in std_logic;
  	S    : in std_logic;
  	O    : out std_logic
  	);
end component;
--
-- signal declarations
signal SHIFT_CHAIN : std_logic_vector (4 downto 0);
signal SHIFT_OUT : std_logic_vector (3 downto 0);
signal F5_OUT : std_logic_vector (1 downto 0);
--
begin
--
SHIFT_CHAIN(0) <= D;
--
-- ShiftRegister Instantiations
U_SRLC16E_INST: for i in 0 to 3 generate
-- 
U_SRLC16E: SRLC16E
  generic map ( INIT64((16*i+15) downto (16*i)) )
  port map (
	D      => SHIFT_CHAIN(i),
	CE     => CE, 
	CLK    => CLK, 
	A0     => A0, 
	A1     => A1, 
	A2     => A2, 
	A3     => A3, 
	Q      => SHIFT_OUT(i),
	Q15    => SHIFT_CHAIN (i+1)  
	);
end generate;
--
Q63 <= SHIFT_CHAIN (4);
--
-- Local Slice output
U_MUXF5_INST: for i in 0 to 1 generate
--
U_MUXF5: MUXF5_L
  port map (
  	I0     => SHIFT_OUT(i*2),
  	I1     => SHIFT_OUT(i*2 + 1),
  	S      => A4,
  	LO     => F5_OUT(i)
  	);	
end generate;	
--
U_MUXF6: MUXF6
  port map (
         I0    => F5_OUT(0),
         I1    => F5_OUT(1),
         S     => A5,
         O     => Q
         );
--		
end SRLC64E_MACRO_arch;
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