SCLD Operation with the ADF-2 in Run 2B ------------------------------------------- Original Rev. 27-OCT-2006 Current Rev. 29-MAY-2007 The purpose of this file is to describe the setup of the SCLD card for use with the ADF-2 cards in D-Zero Run 2B. We have a total of 3 SCLD cards. They are numbered SN#1:SN#3. Operation of the D-Zero Run 2B Level 1 Calorimeter Trigger requires one SCLD card. 1. SCLD Firmware for use with ADF-2 The current firmware to use with the SCLD cards is scld_t5.exo The date of this firmware is 9-May-2006. It is on the web in the following directory: www.pa.msu.edu/hep/d0/ftp/run2b/l1cal/hardware/adf_2/firmware/scld_fpga/test/ In that directory you will also find a file that gives a description of this firmware. It is called, description_of scld_test_fws.txt 2. Loading Firmware onto the SCLD Card Firmware can be loaded onto the SCLD card using the JTAG pod and the Xilinx "Impact" tool. I have been loading the firmware into both the "firmware PROM" and into the "parameters PROM" that way I do not have to remember which PROM is which. The "parameters PROM" is not used with the firmware for ADF-2 operation so it does not matter what is loaded into it. Remember that when using "Impact" to load these PROMs you must tell it that this is "Parallel" data for FPGA Configuration. For reference the order of the devices on the JTAG chain is: TDI >----- Configuration ----- Parameter ----- FPGA -----> TDO PROM PROM The JTAG pod is connected to the JTAG connector on the SCLD card via a cable. The same cable that is used to configure the Board Control PAL on the ADF-2 card can be used to connect the JTAG pod to the SCLD card. To use this cable you must break out the top narrow edge of the JTAG connector on the SCLD card. This edge is easy to snap out. 2. LVDS Terminator Resistors on the SCLD Card A number of LVDS terminator resistors must be removed from the SCLD card for operation with the ADF-2 cards. These must be removed because with ADF-2 operation most of the LVDS lines between the SCLD and the Maestro ADF-2 card in each ADF Crate are used to send information from the SCLD to the ADF-2 (and therefore these lines should not be terminated on the SCLD card). The resistors that need to be removed are listed below. They are listed in the order that they appear on the SCLD card. To keep these resistors in the order that they physically appear on the card I have listed both the resistors that should be removed and the ones that must stay on the card. Top Side Bottom Side --------------- --------------- Ref Ref Desig Remove? Desig Remove? ----- ------- ----- ------- R18 yes R45 -- NO R19 yes R46 yes R20 yes R47 -- NO R21 yes R48 yes R22 yes R49 yes R23 yes R50 yes R24 -- NO R51 yes R25 yes R52 -- NO --> R17 yes R53 yes R26 yes R54 -- NO R27 yes R28 yes R37 -- NO R29 -- NO R38 -- NO R30 yes R39 -- NO R31 -- NO R41 yes R42 yes R40 -- NO R43 -- NO R44 -- NO 3. LVDS signals that are not correctly terminated. What lines are not correctly terminated after the above resistors have been removed ?? All of the lines are correctly terminated except for the "Crate_to_SCLD_0" signal which carries information from the ADF Crate to the SCLD card. But it is OK that this signal is not terminated in the ADF-2 application because this line carries only very slowly changing information and its arrival time and edge count at the SCLD card are not critical. 4. LVDS Signals that Criss Cross (invert the polarity of the signal) Are any of the LVDS pairs between the SCLD and the ADF Crates criss crossed ?? Yes, the SCLD printed circuit board is not consistent in the way that the signals that it calls REMx and LOCx were layed out. For the prototype ADF-1 application these were two separate signals that were carried single ended but were on a P,N pair of LVDS pins on the SCLD FPGA. Their layout was not consistent for all 5 crates. Specifically the SCLD layout for these two signals is: REM_0 N LOC_0 P REM_1 N LOC_1 P REM_2 P LOC_2 N REM_3 P LOC_3 N REM_4 N LOC_4 P The rational natural order for these two signals was to put LOC the P side of the differential pair and to put REM on the on the N side. These the traces on the SCLD card for ADF Crates #2 and #3 are wired criss cross. In the ADF-2 Run 2B application this LVDS differential pair carries the "Crate_to_SCLD_0" signal and this is only used from ADF Crate "A" i.e. ADF Crate #0. So these runs from ADF Crates #2 and #3 do not matter. If these signals are ever needed this could be "fixed" with an inverter in the SCLD FPGA. 5. What LED Is What. Loc Ref Col T5 SCLD Firmware Usage Saclay Usage --- --- --- ---------------------------------- ---------------- Top D2 Red +5 Volt Power +5 Volt Power D3 Grn FPGA Configuration DONE FPGA Config DONE D4 Grn Mode of Save_Mon_Data Normal vs Dean Clock Locked D5 Grn Delayed L2_Period stretched 10 msec Delays Loaded D6 Yel Save_Monit_Data stretched 10 msec Cable 0 Plugged D7 Yel ADF Crt 0 Sig 0 Enb Trig Save Monit Cable 1 Plugged D8 Yel ADF Crt 0 Sig 1 Force Save Monit Cable 2 Plugged D9 Yel SCL_SYNCERROR signal from SCL Rcvr Cable 3 Plugged D10 Yel SCL_READY signal from SCL Rcvr Cable 4 Plugged Bot D11 Grn SCL_ACK signal to SCL Rcvr User LED LEDs D4 and D5 are only used in the scld_t5_dean firmware. LED D4 is illuminated in the special Dean Mode of generating the Save_Monitor_Data signal. LED D5 is also used in the LArTPC firmware design. 6. What Button Does What There are 3 buttons on the SCLD card. - On the surface of the SCLD card, near its P2 connector, there is a push button with the reference designator SW1. Pushing this button will cause the FPGA to configure from the Configuration PROM. - Push button reference designator PO1 is at the top of the front panel of the SCLD card. This switch sends both N.O. and N.C. signals that swing between GND and 4.7 k Ohm pull up resistors to 3.3 Volt to pins on the SCLD FPGA. With the scld_t5.exo firmware, pushing this button causes the SCL_ACK signal to be sent to the SCL Receiver, i.e. it tells the SCL Receiver to again lock onto the SCL serial data stream. - On the front panel, PO2 is right below PO1. It has the same N.O. and N.C. connections to the SCLD FPGA. In the scld_t5.exo firmware the signals from this push button are not used. 7. How to Set the SCLD Card DIP Switch Keys On the SCLD card there is a 4 key DIP switch right below its FPGA. - Key #1 controls the M1 configuration signal to the FPGA and key #2 controls the M2 configuration signal to the FPGA. The M1 and M2 signals going to the FPGA are pulled up to 3.3 Volts by external resistors but may be pulled down to GND by closing these keys on this DIP Switch. The M0 configuration signal to the FPGA is also pulled up to 3.3 Volts but there is no provision for pulling it down to GND. With keys #1 and #2 down (open) then the FPGA is in the "Master Select Map" mode of configuration and will configure from the SCLD Configuration PROM. With keys #1 and #2 up (closed) then you can configure the SCLD FPGA from the JTAG port. - Key #3 is not used and is not usable because both sides of it have been tied to internal GND plane on the SCLD card. To provide a standard defined setup, leave key #3 set down (open). - Key #4 can GND a pin on the FPGA that is otherwise pulled up to 3.3 Volts via and external 390 Ohm resistor. This is FPGA pin is number B12 and in the Saclay SCLD card schematics it is called CLK_SEL. Key #4 should be set down (open). - It's simple, for normal operation all 4 key on the SCLD card DIP switch sould be set down (open). 8. Special Operation with the SCLD_T5_Dean Firmware The only difference between SCLD_T5 firmware and SCLD_T5_Dean firmware is that the SCLD_T5_Dean firmware provides a special "Dean" mode of generating the Save_Monitor_Data signal. This special mode only effects the Monitor Data that is collected by the L1 Cal Trig TCC. There is no difference in the way that these two versions of SCLD firmware operate the ADF-2 cards as far as how they send their Et data to the TAB cards. The SCLD_T5_Dean firmware provides two modes for generating the Save_Monitor_Data signal. In the "Normal Physics" mode the SCLD_T5_Dean firmware generates the Save_Monitor_Data signal just like the SCLD_T5 firmware does, i.e. when enabled to do so the L1_Period signal with the L1_Qualifier_7 will cause the Save_Monitor_Data signal to be issued. The SCLD_T5_Dean firmware provides a second mode where the Save_Monitor_Data signal is generated a programmable length of time after the L2_Period signal is received from the SCL Receiver. The mode of generating the Save_Monitor_Data signal is controlled by the SCLD front panel toggle switch labeled "Dean" up and "Normal Physics" down. Note that the front panel toggle switch that allows selection of the "Normal Physics" mode or the "Dean" mode is just a switch across key #4 of the SCLD card 4 key DIP switch. See item #7 above. For this front panel toggle switch to be able to control the mode of generating the Save_Monitor_Data signal, key #4 of the SCLD card 4 key DIP switch must be down (open). When in the Dean mode of generating the Save_Monitor_Data signal, the length of time between receiving the L2_Period signal and issuing the Save_Monitor_Data signal is controlled by an 8 key DIP switch which plugges into the DeBug connector on the SCLD Card. The setup of this DIP switch is shown in the following table: Time Interval Key Number Comparator Number of Controlled on DIP SW Reference Value Bit 132 nsec Ticks by this Key ---------- ------------------- -------------- ------------- 1 bit #4 16 2.1 usec 2 bit #5 32 4.2 usec 3 bit #6 64 8.4 usec 4 bit #7 128 16.9 usec 5 bit #8 256 33.7 usec 6 bit #9 512 67.5 usec 7 bit #10 1024 135.0 usec 8 bit #11 2048 270.0 usec With a key set OPEN it means that the total delay time includes the time interval controlled by that key. For example with just keys #6 and #7 set OPEN, and all the other keys CLOSED, then the total delay between receiving the L2_Period signal and issuing the Save_Monitor_Data signal would be 405 usec. For initial tests with the SCLD_T5_Dean firmware we will have just key #4 OPEN and all other keys CLOSED. This will provide 16.9 usec of delay between the L2_Period signal and issuing the Save_Monitor_Data signal. For the SCLD_T5_Dean firmware to operate the L2_Period signal must be routed from the SCL Receiver socket to a pin on the SCLD FPGA. For some reason this signal was not routed in trace on the SCLD card. The L2_Period signal comes out of pin #44 on connector P1 of the SCL Receiver. It is routed to the SCLD FPGA by connecting to pin #8 of the DeBug connector. Pin #8 of the DeBug connector is connected via trace to pin P22 of the SCLD FPGA.