ADF-2 Initialization 13-Jan-2006 An ADF-2 card can be individually and manually Initialized via the L1Cal_IIb_GUI Interface by specifying its Crate and Slot numbers. All ADF-2 Cards within the currently defined Eta/Phi coverage are initialized during the L1Cal system initialization, for example in response to an "INIT" request from COOR. I) Initialize the Board Control FPGA ==================================== I.1) Start Up the ADCs While at the same time Lock out the possibility of FPGA Configuration Lock out the possibility of Pedestal DAC download Disable BC PAL Access signals At Register Address 0 Write 0x81 I.2) Channel Link in DC_Balance Mode (DeSkew Operation NOT running) At Register Address 0 Write 0x83 I.3) Channel Link in DC_Balance Mode and DeSkew Operation Running. At Register Address 0 Write 0x82 I.4) Channel Link in DC_Balance Mode (DeSkew Operation NOT running) At Register Address 0 Write 0x83 I.5) BC PAL LED #1 ON. This register will be left with DeSkew Operation NOT running Channel Link in DC_Balance Mode BC PAL LED #1 ON Lock out the possibility of FPGA Configuration Lock out the possibility of Pedestal DAC download Disable BC PAL Access signals ADCs running At Register Address 0 Write 0x8b I.6) Setup to the Configuration Control Register Disable the Configuration of both FPGAs Set CNFG_RDWR_B to a "0" --> Voltage Low. This is now a User I/O line and setting CNFG_RDWR_B low now controls the 32 Pseudo Random Number generators on this ADF-2 card which will now all be stopped from running. At Register Address 5 Write 0x0f I.7) Write to the Board Level Control Register #2 Set the Crate Status Lines. 3:0 to No Contribution. Set the Crate to SCLD signals 1:0 to Zero. Do not set the Pedestal DAC's Chip Select to the active state. At Register Address 1 Write 0x40 II) Initialize Data Path FPGA #0 ================================ II.1) Set the Raw ADC Mem Blk Address Generator Highest Address During one full turn, the Raw ADC Mem Blk uses 4 * 159 = 636 memory locations. The value that needs to be loaded into the Highest Address register is 2 less than this. It is 1 less because the address sequence starts at zero. It is another 1 less because the generator will stop on the cycle after it reaches this count. After loading this register we can be guaranteed that the Address Generator will actually stop within one turn, i.e. within 21 usec after you negate its control bit that enables it to make multiple passes through its address sequence. At Register Address 0x201=513 Write 634 II.2) Stop the Raw ADC Mem Blk Address Generator The intent of this step is to Stop the Address Generator and to put it into a default state. Do not enable the Address Generator to play multiple passes through its address sequence. Set bit #1 to low. Do not enable the Save Monitor Data signal to stop the Address Generator. Set bit #2 to low. Do not allow the Address Generator to assert its Raw ADC Mem Blk GLOBAL A-Port Write Enable signal. Set bit #3 to low. At Register Address 0x200=512 Write 0x0000 Note that TCC has no convenient way to actually force the Address Generator to Stop. All that TCC can do is to let it finish playing through the current cycle of its address sequence. At this point, to be absolutely safe, we must wait 21 usec. The issue here is that to be guaranteed that the Address Generator will not be running and continue to run after you execute the next step, you must first be certain that it has stopped. TCC can not conveniently force it to stop so you must let the current cycle of the address sequence play through. The above register write also implies one post-write read-check. We write the same value again, and there will thus be one pre-write read-check, one write, and one post-write read-check. Before the value is cahnged in the next step, here will also be another pre-write read-check. This gives a total of 5 VME IOs before the register value is changed. One extra write should be enough to cover 5x5=25us, but we write it twice anyway, for good measure. At Register Address 0x200=512 Write 0x0000 2 more times II.3) Setup the Raw ADC Mem Blk Address Generator Now we want to prepare the Address Generator so that when it is started sometime later, it will be in the correct mode to collect Monitoring Data. We do it in this order, i.e. first setting the various options in the Address Generator and then later start it running, so that we are not setting options and starting it running all on the same clock edge. Do Not start the Address Generator. Set bit #0 low. DO enable the Address Generator to play multiple passes through its address sequence. Set bit #1 high. DO enable the Save Monitor Data signal to stop the Address Generator. Set bit #2 high. DO allow the Address Generator to assert its Raw ADC Mem Blk GLOBAL A-Port Write Enable signal while it is running. Set bit #3 high. At Register Address 0x200=512 Write 0x000E II.4) Set the Final Output Mem Blk Address Generator Highest Address The Final Output Address Generator is handled in the same way as the Raw ADC Address Generator except that its Highest Address register is loaded with 157 i.e. 159 - 2. At Register Address 0x204=516 Write 157 II.5) Stop the Final Output Mem Blk Address Generator At Register Address 0x203=515 Write 0x0000 3 times II.6) Setup the Final Output Mem Blk Address Generator At Register Address 0x200=515 Write 0x000E II.7) Per TT Registers These actions are repeated for both EM and HD channels of all 2 x eta and 4 x phi coordinates handled by this FPGA. note: the initialization order is collapsed below, as each step #a through #d below is first performed on the EM channel, then each step is repeated for the HD channel of each tower. II.7.a) TT Reg #2 for TT = 0,0 0,0 EM INPUT Section Control TT Reg #3 for TT = 0,0 0,0 HD INPUT Section Control bits 7:0 set to 00 Set the top Comparator Reference to zero. bits 11:8 set to 0 Set the ADC Data Alignment Delay to the minimum value. bit 12 set to 0 Select the ADC Data to send to the Filter bit 14 set to 0 Set the Raw ADC Mem Blk A-Port Write Enable for the EM part of this TT to follow the Global Raw ADC Mem Blk Wrt Enable. At Register Address 0x302=770 (for the relative (0,0) EM tower) Write 0x0000 At Register Address 0x303=771 (for the relative (0,0) HD tower) Write 0x0000 II.7.b) TT Reg #4 for TT = 0,0 0,0 EM OUTPUT Section Control TT Reg #5 for TT = 0,0 0,0 HD OUTPUT Section Control bits 7:0 set to 08 Set the value of the "Constant" EM Et Data. bits 10:8 set to 4 Set Output Mux Control to select Filter Output data for Live Crossings and to select "Constant" Et data for all other Ticks. bit 12 set to 0 Setthe Output Data Mem Blk A-Port Write Enable for the EM part of this TT to follow the Global Output Data Mem Blk Wrt Enable. At Register Address 0x304=772 (for the relative (0,0) EM tower) Write 0x0408 At Register Address 0x305=773 (for the relative (0,0) HD tower) Write 0x0408 II.7.c) TT Reg #6 for TT = 0,0 0,0 EM PRN Seed TT Reg #7 for TT = 0,0 0,0 HD PRN Seed Set the PRN Seed to $FFFF i.e. lock the PRN Generator at Hi. The PRN Generator is not running but let's load this register to be extra safe. At Register Address 0x306=774 (for the relative (0,0) EM tower) Write 0xffff At Register Address 0x307=775 (for the relative (0,0) HD tower) Write 0xffff II.7.d) Initialize Et Lookup Memory This step is executed only when the card is initialized directly from the GUI menu, given by its card slot coordinates. In this casethe memory is loaded with the default one-to-one memory lookup (with saturation at 255). This step is skipped if the ADF card initialized as part of the high level COOR initialization command. The Lookup Et initialization will happen (shortly after) during the initialization of the trigger towers. cf. Appendix A. III) Initialize Data Path FPGA #1 ================================= Same as for FPGA#0 above. ------------------------------------------------------------------------------- Appendix A) Trigger Tower Initialization ========================================= When the L1Cal system is intialized (e.g. by COOR), all ADF cards are first initialized as described above to bring the ADF cards to a "generic" operational state. The ADF-2 Cards are initialized in eta order with all positive eta first, then negative eta, and in phi order for each eta segment. Each Trigger Tower is then initialized to program the resources of the corresponding ADF Channel for the correct TT(eta,phi) "physics" operation. The Trigger Towers are also initialized in eta order with all positive eta first, then negative eta, and in phi order for each eta value. The parameters defining the Trigger Tower specific Coefficients should have been previously specified to TCC by executing one of more Trigger Tower Information Command Files (TTI files) e.g. at boot time during the execution of the Auxiliary Boot command file (Boot_Auxi.mcf) The Trigger Tower initialization steps are: A.1) Load the Pedestal Control DAC The default value is 0 Different values can be specified in TTI command files via the keyword "Pedestal_Control_DAC:" Find_DAC can automatically produce an output in the form of a TTI command file suited to define Pedestal Control values over a range of trigger towers. A.2) Load the Et Lookup Memory The default is a one-to-one lookup with Output Et saturation at 255 Different lookups can be specified using TTI command files via the keywords "Zero_Energy_Adc_E:", "Zero_Energy_Output_Et:", and ""Lookup_Slope:" A.3) Load the Alignment Delay The value programmed is the sum of a Base Alignment Delay value common to all Trigger Towers and a Relative Alighment Delay value specific to each Trigger Tower. The default Relative Alignment Delay value is 0 Different RELATIVE Alignment Delay values must be specified in TTI command files via the keyword "Alignment_Delay:" The default Base Alignment Delay value is 0 The Global BASE Alignment Delay value is specified in a Master Command file via the keyword "BaseAlignmentDelay:", e.g. as part of the Auxiliary Boot command file (Boot_Auxi.mcf) The Global Base Alignment Delay value can also be specified or modified on the fly with a COOR-like command "TrgMgr_BaseAlignmentDelay " ------------------------------------------------------------------------------- Appendix B) Collecting Monitoring Information ============================================== After a full system initialization (e.g. after an "INIT" command from COOR) all the Address Generator are setup for collecting monitoring information, but are all left in a stopped state. The Monitoring Data collection process will periodically start all Raw ADC and Output Et Address Generators running again, including starting them for the first time after an initialization. Starting the Address Generators happens after all the relevant monitoring data from a previously captured sample has been read out, and before the SCLD is signaled to watch for and capture the next monitoring data sample. Start the Raw ADC Address Generator Set the start bit low At Register Address 0x200=512 Write 0x000E Set the start bit high At Register Address 0x200=512 Write 0x000F Start the Final Output Et Address Generator Set the start bit low At Register Address 0x200=515 Write 0x000E Set the start bit high At Register Address 0x200=515 Write 0x000F Note: Raw ADC monitoring data is currently NOT read out during Monitoring Data Collection and the management of Raw ADC data Address generators may change in the future.